This source file includes following definitions.
- early_init_dt_scan_chosen_arch
- early_init_dt_add_memory_arch
- add_dtb
- add_bus_probe
- pcibios_get_phb_of_node
- x86_of_pci_irq_enable
- x86_of_pci_irq_disable
- x86_of_pci_init
- dtb_setup_hpet
- dtb_cpu_setup
- dtb_lapic_setup
- dt_irqdomain_alloc
- dtb_add_ioapic
- dtb_ioapic_setup
- dtb_ioapic_setup
- dtb_apic_setup
- x86_flattree_get_config
- x86_flattree_get_config
- x86_dtb_init
1
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3
4
5 #include <linux/export.h>
6 #include <linux/io.h>
7 #include <linux/interrupt.h>
8 #include <linux/list.h>
9 #include <linux/of.h>
10 #include <linux/of_fdt.h>
11 #include <linux/of_address.h>
12 #include <linux/of_platform.h>
13 #include <linux/of_irq.h>
14 #include <linux/libfdt.h>
15 #include <linux/slab.h>
16 #include <linux/pci.h>
17 #include <linux/of_pci.h>
18 #include <linux/initrd.h>
19
20 #include <asm/irqdomain.h>
21 #include <asm/hpet.h>
22 #include <asm/apic.h>
23 #include <asm/pci_x86.h>
24 #include <asm/setup.h>
25 #include <asm/i8259.h>
26 #include <asm/prom.h>
27
28 __initdata u64 initial_dtb;
29 char __initdata cmd_line[COMMAND_LINE_SIZE];
30
31 int __initdata of_ioapic;
32
33 void __init early_init_dt_scan_chosen_arch(unsigned long node)
34 {
35 BUG();
36 }
37
38 void __init early_init_dt_add_memory_arch(u64 base, u64 size)
39 {
40 BUG();
41 }
42
43 void __init add_dtb(u64 data)
44 {
45 initial_dtb = data + offsetof(struct setup_data, data);
46 }
47
48
49
50
51 static struct of_device_id __initdata ce4100_ids[] = {
52 { .compatible = "intel,ce4100-cp", },
53 { .compatible = "isa", },
54 { .compatible = "pci", },
55 {},
56 };
57
58 static int __init add_bus_probe(void)
59 {
60 if (!of_have_populated_dt())
61 return 0;
62
63 return of_platform_bus_probe(NULL, ce4100_ids, NULL);
64 }
65 device_initcall(add_bus_probe);
66
67 #ifdef CONFIG_PCI
68 struct device_node *pcibios_get_phb_of_node(struct pci_bus *bus)
69 {
70 struct device_node *np;
71
72 for_each_node_by_type(np, "pci") {
73 const void *prop;
74 unsigned int bus_min;
75
76 prop = of_get_property(np, "bus-range", NULL);
77 if (!prop)
78 continue;
79 bus_min = be32_to_cpup(prop);
80 if (bus->number == bus_min)
81 return np;
82 }
83 return NULL;
84 }
85
86 static int x86_of_pci_irq_enable(struct pci_dev *dev)
87 {
88 u32 virq;
89 int ret;
90 u8 pin;
91
92 ret = pci_read_config_byte(dev, PCI_INTERRUPT_PIN, &pin);
93 if (ret)
94 return ret;
95 if (!pin)
96 return 0;
97
98 virq = of_irq_parse_and_map_pci(dev, 0, 0);
99 if (virq == 0)
100 return -EINVAL;
101 dev->irq = virq;
102 return 0;
103 }
104
105 static void x86_of_pci_irq_disable(struct pci_dev *dev)
106 {
107 }
108
109 void x86_of_pci_init(void)
110 {
111 pcibios_enable_irq = x86_of_pci_irq_enable;
112 pcibios_disable_irq = x86_of_pci_irq_disable;
113 }
114 #endif
115
116 static void __init dtb_setup_hpet(void)
117 {
118 #ifdef CONFIG_HPET_TIMER
119 struct device_node *dn;
120 struct resource r;
121 int ret;
122
123 dn = of_find_compatible_node(NULL, NULL, "intel,ce4100-hpet");
124 if (!dn)
125 return;
126 ret = of_address_to_resource(dn, 0, &r);
127 if (ret) {
128 WARN_ON(1);
129 return;
130 }
131 hpet_address = r.start;
132 #endif
133 }
134
135 #ifdef CONFIG_X86_LOCAL_APIC
136
137 static void __init dtb_cpu_setup(void)
138 {
139 struct device_node *dn;
140 u32 apic_id, version;
141 int ret;
142
143 version = GET_APIC_VERSION(apic_read(APIC_LVR));
144 for_each_of_cpu_node(dn) {
145 ret = of_property_read_u32(dn, "reg", &apic_id);
146 if (ret < 0) {
147 pr_warn("%pOF: missing local APIC ID\n", dn);
148 continue;
149 }
150 generic_processor_info(apic_id, version);
151 }
152 }
153
154 static void __init dtb_lapic_setup(void)
155 {
156 struct device_node *dn;
157 struct resource r;
158 unsigned long lapic_addr = APIC_DEFAULT_PHYS_BASE;
159 int ret;
160
161 dn = of_find_compatible_node(NULL, NULL, "intel,ce4100-lapic");
162 if (dn) {
163 ret = of_address_to_resource(dn, 0, &r);
164 if (WARN_ON(ret))
165 return;
166 lapic_addr = r.start;
167 }
168
169
170 if (!boot_cpu_has(X86_FEATURE_APIC)) {
171 if (apic_force_enable(lapic_addr))
172 return;
173 }
174 smp_found_config = 1;
175 pic_mode = 1;
176 register_lapic_address(lapic_addr);
177 }
178
179 #endif
180
181 #ifdef CONFIG_X86_IO_APIC
182 static unsigned int ioapic_id;
183
184 struct of_ioapic_type {
185 u32 out_type;
186 u32 trigger;
187 u32 polarity;
188 };
189
190 static struct of_ioapic_type of_ioapic_type[] =
191 {
192 {
193 .out_type = IRQ_TYPE_EDGE_RISING,
194 .trigger = IOAPIC_EDGE,
195 .polarity = 1,
196 },
197 {
198 .out_type = IRQ_TYPE_LEVEL_LOW,
199 .trigger = IOAPIC_LEVEL,
200 .polarity = 0,
201 },
202 {
203 .out_type = IRQ_TYPE_LEVEL_HIGH,
204 .trigger = IOAPIC_LEVEL,
205 .polarity = 1,
206 },
207 {
208 .out_type = IRQ_TYPE_EDGE_FALLING,
209 .trigger = IOAPIC_EDGE,
210 .polarity = 0,
211 },
212 };
213
214 static int dt_irqdomain_alloc(struct irq_domain *domain, unsigned int virq,
215 unsigned int nr_irqs, void *arg)
216 {
217 struct irq_fwspec *fwspec = (struct irq_fwspec *)arg;
218 struct of_ioapic_type *it;
219 struct irq_alloc_info tmp;
220 int type_index;
221
222 if (WARN_ON(fwspec->param_count < 2))
223 return -EINVAL;
224
225 type_index = fwspec->param[1];
226 if (type_index >= ARRAY_SIZE(of_ioapic_type))
227 return -EINVAL;
228
229 it = &of_ioapic_type[type_index];
230 ioapic_set_alloc_attr(&tmp, NUMA_NO_NODE, it->trigger, it->polarity);
231 tmp.ioapic_id = mpc_ioapic_id(mp_irqdomain_ioapic_idx(domain));
232 tmp.ioapic_pin = fwspec->param[0];
233
234 return mp_irqdomain_alloc(domain, virq, nr_irqs, &tmp);
235 }
236
237 static const struct irq_domain_ops ioapic_irq_domain_ops = {
238 .alloc = dt_irqdomain_alloc,
239 .free = mp_irqdomain_free,
240 .activate = mp_irqdomain_activate,
241 .deactivate = mp_irqdomain_deactivate,
242 };
243
244 static void __init dtb_add_ioapic(struct device_node *dn)
245 {
246 struct resource r;
247 int ret;
248 struct ioapic_domain_cfg cfg = {
249 .type = IOAPIC_DOMAIN_DYNAMIC,
250 .ops = &ioapic_irq_domain_ops,
251 .dev = dn,
252 };
253
254 ret = of_address_to_resource(dn, 0, &r);
255 if (ret) {
256 printk(KERN_ERR "Can't obtain address from device node %pOF.\n", dn);
257 return;
258 }
259 mp_register_ioapic(++ioapic_id, r.start, gsi_top, &cfg);
260 }
261
262 static void __init dtb_ioapic_setup(void)
263 {
264 struct device_node *dn;
265
266 for_each_compatible_node(dn, NULL, "intel,ce4100-ioapic")
267 dtb_add_ioapic(dn);
268
269 if (nr_ioapics) {
270 of_ioapic = 1;
271 return;
272 }
273 printk(KERN_ERR "Error: No information about IO-APIC in OF.\n");
274 }
275 #else
276 static void __init dtb_ioapic_setup(void) {}
277 #endif
278
279 static void __init dtb_apic_setup(void)
280 {
281 #ifdef CONFIG_X86_LOCAL_APIC
282 dtb_lapic_setup();
283 dtb_cpu_setup();
284 #endif
285 dtb_ioapic_setup();
286 }
287
288 #ifdef CONFIG_OF_EARLY_FLATTREE
289 static void __init x86_flattree_get_config(void)
290 {
291 u32 size, map_len;
292 void *dt;
293
294 if (!initial_dtb)
295 return;
296
297 map_len = max(PAGE_SIZE - (initial_dtb & ~PAGE_MASK), (u64)128);
298
299 dt = early_memremap(initial_dtb, map_len);
300 size = fdt_totalsize(dt);
301 if (map_len < size) {
302 early_memunmap(dt, map_len);
303 dt = early_memremap(initial_dtb, size);
304 map_len = size;
305 }
306
307 early_init_dt_verify(dt);
308 unflatten_and_copy_device_tree();
309 early_memunmap(dt, map_len);
310 }
311 #else
312 static inline void x86_flattree_get_config(void) { }
313 #endif
314
315 void __init x86_dtb_init(void)
316 {
317 x86_flattree_get_config();
318
319 if (!of_have_populated_dt())
320 return;
321
322 dtb_setup_hpet();
323 dtb_apic_setup();
324 }