This source file includes following definitions.
- cpu_has_xfeatures
- xfeature_is_supervisor
- xfeature_is_user
- fpstate_sanitize_xstate
- fpu__init_cpu_xstate
- xfeature_enabled
- setup_xstate_features
- print_xstate_feature
- print_xstate_features
- xfeature_is_aligned
- setup_xstate_comp
- print_xstate_offset_size
- setup_init_fpu_buf
- xfeature_uncompacted_offset
- xfeature_size
- using_compacted_format
- validate_xstate_header
- __xstate_dump_leaves
- check_xstate_against_struct
- do_extra_xstate_size_checks
- get_xsaves_size
- get_xsave_size
- is_supported_xstate_size
- init_xstate_size
- fpu__init_disable_system_xstate
- fpu__init_system_xstate
- fpu__resume_cpu
- __raw_xsave_addr
- get_xsave_addr
- get_xsave_field_ptr
- arch_set_user_pkey_access
- xfeatures_mxcsr_quirk
- fill_gap
- copy_part
- copy_xstate_to_kernel
- __copy_xstate_to_user
- copy_xstate_to_user
- copy_kernel_to_xstate
- copy_user_to_xstate
- avx512_status
- proc_pid_arch_status
1
2
3
4
5
6
7 #include <linux/compat.h>
8 #include <linux/cpu.h>
9 #include <linux/mman.h>
10 #include <linux/pkeys.h>
11 #include <linux/seq_file.h>
12 #include <linux/proc_fs.h>
13
14 #include <asm/fpu/api.h>
15 #include <asm/fpu/internal.h>
16 #include <asm/fpu/signal.h>
17 #include <asm/fpu/regset.h>
18 #include <asm/fpu/xstate.h>
19
20 #include <asm/tlbflush.h>
21 #include <asm/cpufeature.h>
22
23
24
25
26
27
28 static const char *xfeature_names[] =
29 {
30 "x87 floating point registers" ,
31 "SSE registers" ,
32 "AVX registers" ,
33 "MPX bounds registers" ,
34 "MPX CSR" ,
35 "AVX-512 opmask" ,
36 "AVX-512 Hi256" ,
37 "AVX-512 ZMM_Hi256" ,
38 "Processor Trace (unused)" ,
39 "Protection Keys User registers",
40 "unknown xstate feature" ,
41 };
42
43 static short xsave_cpuid_features[] __initdata = {
44 X86_FEATURE_FPU,
45 X86_FEATURE_XMM,
46 X86_FEATURE_AVX,
47 X86_FEATURE_MPX,
48 X86_FEATURE_MPX,
49 X86_FEATURE_AVX512F,
50 X86_FEATURE_AVX512F,
51 X86_FEATURE_AVX512F,
52 X86_FEATURE_INTEL_PT,
53 X86_FEATURE_PKU,
54 };
55
56
57
58
59 u64 xfeatures_mask __read_mostly;
60
61 static unsigned int xstate_offsets[XFEATURE_MAX] = { [ 0 ... XFEATURE_MAX - 1] = -1};
62 static unsigned int xstate_sizes[XFEATURE_MAX] = { [ 0 ... XFEATURE_MAX - 1] = -1};
63 static unsigned int xstate_comp_offsets[sizeof(xfeatures_mask)*8];
64
65
66
67
68
69
70 unsigned int fpu_user_xstate_size;
71
72
73
74
75
76
77 int cpu_has_xfeatures(u64 xfeatures_needed, const char **feature_name)
78 {
79 u64 xfeatures_missing = xfeatures_needed & ~xfeatures_mask;
80
81 if (unlikely(feature_name)) {
82 long xfeature_idx, max_idx;
83 u64 xfeatures_print;
84
85
86
87
88
89
90
91 if (xfeatures_missing)
92 xfeatures_print = xfeatures_missing;
93 else
94 xfeatures_print = xfeatures_needed;
95
96 xfeature_idx = fls64(xfeatures_print)-1;
97 max_idx = ARRAY_SIZE(xfeature_names)-1;
98 xfeature_idx = min(xfeature_idx, max_idx);
99
100 *feature_name = xfeature_names[xfeature_idx];
101 }
102
103 if (xfeatures_missing)
104 return 0;
105
106 return 1;
107 }
108 EXPORT_SYMBOL_GPL(cpu_has_xfeatures);
109
110 static int xfeature_is_supervisor(int xfeature_nr)
111 {
112
113
114
115
116
117
118
119
120 u32 eax, ebx, ecx, edx;
121
122 cpuid_count(XSTATE_CPUID, xfeature_nr, &eax, &ebx, &ecx, &edx);
123 return !!(ecx & 1);
124 }
125
126 static int xfeature_is_user(int xfeature_nr)
127 {
128 return !xfeature_is_supervisor(xfeature_nr);
129 }
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146 void fpstate_sanitize_xstate(struct fpu *fpu)
147 {
148 struct fxregs_state *fx = &fpu->state.fxsave;
149 int feature_bit;
150 u64 xfeatures;
151
152 if (!use_xsaveopt())
153 return;
154
155 xfeatures = fpu->state.xsave.header.xfeatures;
156
157
158
159
160
161 if ((xfeatures & xfeatures_mask) == xfeatures_mask)
162 return;
163
164
165
166
167 if (!(xfeatures & XFEATURE_MASK_FP)) {
168 fx->cwd = 0x37f;
169 fx->swd = 0;
170 fx->twd = 0;
171 fx->fop = 0;
172 fx->rip = 0;
173 fx->rdp = 0;
174 memset(&fx->st_space[0], 0, 128);
175 }
176
177
178
179
180 if (!(xfeatures & XFEATURE_MASK_SSE))
181 memset(&fx->xmm_space[0], 0, 256);
182
183
184
185
186
187 feature_bit = 0x2;
188 xfeatures = (xfeatures_mask & ~xfeatures) >> 2;
189
190
191
192
193
194
195 while (xfeatures) {
196 if (xfeatures & 0x1) {
197 int offset = xstate_comp_offsets[feature_bit];
198 int size = xstate_sizes[feature_bit];
199
200 memcpy((void *)fx + offset,
201 (void *)&init_fpstate.xsave + offset,
202 size);
203 }
204
205 xfeatures >>= 1;
206 feature_bit++;
207 }
208 }
209
210
211
212
213
214 void fpu__init_cpu_xstate(void)
215 {
216 if (!boot_cpu_has(X86_FEATURE_XSAVE) || !xfeatures_mask)
217 return;
218
219
220
221
222
223 WARN_ONCE((xfeatures_mask & XFEATURE_MASK_SUPERVISOR),
224 "x86/fpu: XSAVES supervisor states are not yet implemented.\n");
225
226 xfeatures_mask &= ~XFEATURE_MASK_SUPERVISOR;
227
228 cr4_set_bits(X86_CR4_OSXSAVE);
229 xsetbv(XCR_XFEATURE_ENABLED_MASK, xfeatures_mask);
230 }
231
232
233
234
235
236
237 static int xfeature_enabled(enum xfeature xfeature)
238 {
239 return !!(xfeatures_mask & (1UL << xfeature));
240 }
241
242
243
244
245
246 static void __init setup_xstate_features(void)
247 {
248 u32 eax, ebx, ecx, edx, i;
249
250 unsigned int last_good_offset = offsetof(struct xregs_state,
251 extended_state_area);
252
253
254
255
256
257 xstate_offsets[0] = 0;
258 xstate_sizes[0] = offsetof(struct fxregs_state, xmm_space);
259 xstate_offsets[1] = xstate_sizes[0];
260 xstate_sizes[1] = FIELD_SIZEOF(struct fxregs_state, xmm_space);
261
262 for (i = FIRST_EXTENDED_XFEATURE; i < XFEATURE_MAX; i++) {
263 if (!xfeature_enabled(i))
264 continue;
265
266 cpuid_count(XSTATE_CPUID, i, &eax, &ebx, &ecx, &edx);
267
268
269
270
271
272 if (xfeature_is_user(i))
273 xstate_offsets[i] = ebx;
274
275 xstate_sizes[i] = eax;
276
277
278
279
280
281 WARN_ONCE(last_good_offset > xstate_offsets[i],
282 "x86/fpu: misordered xstate at %d\n", last_good_offset);
283 last_good_offset = xstate_offsets[i];
284 }
285 }
286
287 static void __init print_xstate_feature(u64 xstate_mask)
288 {
289 const char *feature_name;
290
291 if (cpu_has_xfeatures(xstate_mask, &feature_name))
292 pr_info("x86/fpu: Supporting XSAVE feature 0x%03Lx: '%s'\n", xstate_mask, feature_name);
293 }
294
295
296
297
298 static void __init print_xstate_features(void)
299 {
300 print_xstate_feature(XFEATURE_MASK_FP);
301 print_xstate_feature(XFEATURE_MASK_SSE);
302 print_xstate_feature(XFEATURE_MASK_YMM);
303 print_xstate_feature(XFEATURE_MASK_BNDREGS);
304 print_xstate_feature(XFEATURE_MASK_BNDCSR);
305 print_xstate_feature(XFEATURE_MASK_OPMASK);
306 print_xstate_feature(XFEATURE_MASK_ZMM_Hi256);
307 print_xstate_feature(XFEATURE_MASK_Hi16_ZMM);
308 print_xstate_feature(XFEATURE_MASK_PKRU);
309 }
310
311
312
313
314
315 #define CHECK_XFEATURE(nr) do { \
316 WARN_ON(nr < FIRST_EXTENDED_XFEATURE); \
317 WARN_ON(nr >= XFEATURE_MAX); \
318 } while (0)
319
320
321
322
323
324 static int xfeature_is_aligned(int xfeature_nr)
325 {
326 u32 eax, ebx, ecx, edx;
327
328 CHECK_XFEATURE(xfeature_nr);
329 cpuid_count(XSTATE_CPUID, xfeature_nr, &eax, &ebx, &ecx, &edx);
330
331
332
333
334
335 return !!(ecx & 2);
336 }
337
338
339
340
341
342
343 static void __init setup_xstate_comp(void)
344 {
345 unsigned int xstate_comp_sizes[sizeof(xfeatures_mask)*8];
346 int i;
347
348
349
350
351
352
353 xstate_comp_offsets[0] = 0;
354 xstate_comp_offsets[1] = offsetof(struct fxregs_state, xmm_space);
355
356 if (!boot_cpu_has(X86_FEATURE_XSAVES)) {
357 for (i = FIRST_EXTENDED_XFEATURE; i < XFEATURE_MAX; i++) {
358 if (xfeature_enabled(i)) {
359 xstate_comp_offsets[i] = xstate_offsets[i];
360 xstate_comp_sizes[i] = xstate_sizes[i];
361 }
362 }
363 return;
364 }
365
366 xstate_comp_offsets[FIRST_EXTENDED_XFEATURE] =
367 FXSAVE_SIZE + XSAVE_HDR_SIZE;
368
369 for (i = FIRST_EXTENDED_XFEATURE; i < XFEATURE_MAX; i++) {
370 if (xfeature_enabled(i))
371 xstate_comp_sizes[i] = xstate_sizes[i];
372 else
373 xstate_comp_sizes[i] = 0;
374
375 if (i > FIRST_EXTENDED_XFEATURE) {
376 xstate_comp_offsets[i] = xstate_comp_offsets[i-1]
377 + xstate_comp_sizes[i-1];
378
379 if (xfeature_is_aligned(i))
380 xstate_comp_offsets[i] =
381 ALIGN(xstate_comp_offsets[i], 64);
382 }
383 }
384 }
385
386
387
388
389 static void __init print_xstate_offset_size(void)
390 {
391 int i;
392
393 for (i = FIRST_EXTENDED_XFEATURE; i < XFEATURE_MAX; i++) {
394 if (!xfeature_enabled(i))
395 continue;
396 pr_info("x86/fpu: xstate_offset[%d]: %4d, xstate_sizes[%d]: %4d\n",
397 i, xstate_comp_offsets[i], i, xstate_sizes[i]);
398 }
399 }
400
401
402
403
404 static void __init setup_init_fpu_buf(void)
405 {
406 static int on_boot_cpu __initdata = 1;
407
408 WARN_ON_FPU(!on_boot_cpu);
409 on_boot_cpu = 0;
410
411 if (!boot_cpu_has(X86_FEATURE_XSAVE))
412 return;
413
414 setup_xstate_features();
415 print_xstate_features();
416
417 if (boot_cpu_has(X86_FEATURE_XSAVES))
418 init_fpstate.xsave.header.xcomp_bv = (u64)1 << 63 | xfeatures_mask;
419
420
421
422
423 copy_kernel_to_xregs_booting(&init_fpstate.xsave);
424
425
426
427
428
429 copy_xregs_to_kernel_booting(&init_fpstate.xsave);
430 }
431
432 static int xfeature_uncompacted_offset(int xfeature_nr)
433 {
434 u32 eax, ebx, ecx, edx;
435
436
437
438
439
440
441 if (XFEATURE_MASK_SUPERVISOR & BIT_ULL(xfeature_nr)) {
442 WARN_ONCE(1, "No fixed offset for xstate %d\n", xfeature_nr);
443 return -1;
444 }
445
446 CHECK_XFEATURE(xfeature_nr);
447 cpuid_count(XSTATE_CPUID, xfeature_nr, &eax, &ebx, &ecx, &edx);
448 return ebx;
449 }
450
451 static int xfeature_size(int xfeature_nr)
452 {
453 u32 eax, ebx, ecx, edx;
454
455 CHECK_XFEATURE(xfeature_nr);
456 cpuid_count(XSTATE_CPUID, xfeature_nr, &eax, &ebx, &ecx, &edx);
457 return eax;
458 }
459
460
461
462
463
464
465
466
467
468
469 int using_compacted_format(void)
470 {
471 return boot_cpu_has(X86_FEATURE_XSAVES);
472 }
473
474
475 int validate_xstate_header(const struct xstate_header *hdr)
476 {
477
478 if (hdr->xfeatures & (~xfeatures_mask | XFEATURE_MASK_SUPERVISOR))
479 return -EINVAL;
480
481
482 if (hdr->xcomp_bv)
483 return -EINVAL;
484
485
486
487
488
489 BUILD_BUG_ON(sizeof(hdr->reserved) != 48);
490
491
492 if (memchr_inv(hdr->reserved, 0, sizeof(hdr->reserved)))
493 return -EINVAL;
494
495 return 0;
496 }
497
498 static void __xstate_dump_leaves(void)
499 {
500 int i;
501 u32 eax, ebx, ecx, edx;
502 static int should_dump = 1;
503
504 if (!should_dump)
505 return;
506 should_dump = 0;
507
508
509
510
511 for (i = 0; i < XFEATURE_MAX + 10; i++) {
512 cpuid_count(XSTATE_CPUID, i, &eax, &ebx, &ecx, &edx);
513 pr_warn("CPUID[%02x, %02x]: eax=%08x ebx=%08x ecx=%08x edx=%08x\n",
514 XSTATE_CPUID, i, eax, ebx, ecx, edx);
515 }
516 }
517
518 #define XSTATE_WARN_ON(x) do { \
519 if (WARN_ONCE(x, "XSAVE consistency problem, dumping leaves")) { \
520 __xstate_dump_leaves(); \
521 } \
522 } while (0)
523
524 #define XCHECK_SZ(sz, nr, nr_macro, __struct) do { \
525 if ((nr == nr_macro) && \
526 WARN_ONCE(sz != sizeof(__struct), \
527 "%s: struct is %zu bytes, cpu state %d bytes\n", \
528 __stringify(nr_macro), sizeof(__struct), sz)) { \
529 __xstate_dump_leaves(); \
530 } \
531 } while (0)
532
533
534
535
536
537
538 static void check_xstate_against_struct(int nr)
539 {
540
541
542
543 int sz = xfeature_size(nr);
544
545
546
547
548 XCHECK_SZ(sz, nr, XFEATURE_YMM, struct ymmh_struct);
549 XCHECK_SZ(sz, nr, XFEATURE_BNDREGS, struct mpx_bndreg_state);
550 XCHECK_SZ(sz, nr, XFEATURE_BNDCSR, struct mpx_bndcsr_state);
551 XCHECK_SZ(sz, nr, XFEATURE_OPMASK, struct avx_512_opmask_state);
552 XCHECK_SZ(sz, nr, XFEATURE_ZMM_Hi256, struct avx_512_zmm_uppers_state);
553 XCHECK_SZ(sz, nr, XFEATURE_Hi16_ZMM, struct avx_512_hi16_state);
554 XCHECK_SZ(sz, nr, XFEATURE_PKRU, struct pkru_state);
555
556
557
558
559
560
561 if ((nr < XFEATURE_YMM) ||
562 (nr >= XFEATURE_MAX) ||
563 (nr == XFEATURE_PT_UNIMPLEMENTED_SO_FAR)) {
564 WARN_ONCE(1, "no structure for xstate: %d\n", nr);
565 XSTATE_WARN_ON(1);
566 }
567 }
568
569
570
571
572
573
574 static void do_extra_xstate_size_checks(void)
575 {
576 int paranoid_xstate_size = FXSAVE_SIZE + XSAVE_HDR_SIZE;
577 int i;
578
579 for (i = FIRST_EXTENDED_XFEATURE; i < XFEATURE_MAX; i++) {
580 if (!xfeature_enabled(i))
581 continue;
582
583 check_xstate_against_struct(i);
584
585
586
587
588 if (!using_compacted_format())
589 XSTATE_WARN_ON(xfeature_is_supervisor(i));
590
591
592 if (xfeature_is_aligned(i))
593 paranoid_xstate_size = ALIGN(paranoid_xstate_size, 64);
594
595
596
597
598
599
600 if (!using_compacted_format())
601 paranoid_xstate_size = xfeature_uncompacted_offset(i);
602
603
604
605
606 paranoid_xstate_size += xfeature_size(i);
607 }
608 XSTATE_WARN_ON(paranoid_xstate_size != fpu_kernel_xstate_size);
609 }
610
611
612
613
614
615
616
617
618
619
620
621
622
623 static unsigned int __init get_xsaves_size(void)
624 {
625 unsigned int eax, ebx, ecx, edx;
626
627
628
629
630
631
632
633
634 cpuid_count(XSTATE_CPUID, 1, &eax, &ebx, &ecx, &edx);
635 return ebx;
636 }
637
638 static unsigned int __init get_xsave_size(void)
639 {
640 unsigned int eax, ebx, ecx, edx;
641
642
643
644
645
646
647
648 cpuid_count(XSTATE_CPUID, 0, &eax, &ebx, &ecx, &edx);
649 return ebx;
650 }
651
652
653
654
655
656 static bool is_supported_xstate_size(unsigned int test_xstate_size)
657 {
658 if (test_xstate_size <= sizeof(union fpregs_state))
659 return true;
660
661 pr_warn("x86/fpu: xstate buffer too small (%zu < %d), disabling xsave\n",
662 sizeof(union fpregs_state), test_xstate_size);
663 return false;
664 }
665
666 static int __init init_xstate_size(void)
667 {
668
669 unsigned int possible_xstate_size;
670 unsigned int xsave_size;
671
672 xsave_size = get_xsave_size();
673
674 if (boot_cpu_has(X86_FEATURE_XSAVES))
675 possible_xstate_size = get_xsaves_size();
676 else
677 possible_xstate_size = xsave_size;
678
679
680 if (!is_supported_xstate_size(possible_xstate_size))
681 return -EINVAL;
682
683
684
685
686
687 fpu_kernel_xstate_size = possible_xstate_size;
688 do_extra_xstate_size_checks();
689
690
691
692
693 fpu_user_xstate_size = xsave_size;
694 return 0;
695 }
696
697
698
699
700
701 static void fpu__init_disable_system_xstate(void)
702 {
703 xfeatures_mask = 0;
704 cr4_clear_bits(X86_CR4_OSXSAVE);
705 setup_clear_cpu_cap(X86_FEATURE_XSAVE);
706 }
707
708
709
710
711
712 void __init fpu__init_system_xstate(void)
713 {
714 unsigned int eax, ebx, ecx, edx;
715 static int on_boot_cpu __initdata = 1;
716 int err;
717 int i;
718
719 WARN_ON_FPU(!on_boot_cpu);
720 on_boot_cpu = 0;
721
722 if (!boot_cpu_has(X86_FEATURE_FPU)) {
723 pr_info("x86/fpu: No FPU detected\n");
724 return;
725 }
726
727 if (!boot_cpu_has(X86_FEATURE_XSAVE)) {
728 pr_info("x86/fpu: x87 FPU will use %s\n",
729 boot_cpu_has(X86_FEATURE_FXSR) ? "FXSAVE" : "FSAVE");
730 return;
731 }
732
733 if (boot_cpu_data.cpuid_level < XSTATE_CPUID) {
734 WARN_ON_FPU(1);
735 return;
736 }
737
738 cpuid_count(XSTATE_CPUID, 0, &eax, &ebx, &ecx, &edx);
739 xfeatures_mask = eax + ((u64)edx << 32);
740
741 if ((xfeatures_mask & XFEATURE_MASK_FPSSE) != XFEATURE_MASK_FPSSE) {
742
743
744
745
746
747 pr_err("x86/fpu: FP/SSE not present amongst the CPU's xstate features: 0x%llx.\n", xfeatures_mask);
748 goto out_disable;
749 }
750
751
752
753
754 for (i = 0; i < ARRAY_SIZE(xsave_cpuid_features); i++) {
755 if (!boot_cpu_has(xsave_cpuid_features[i]))
756 xfeatures_mask &= ~BIT(i);
757 }
758
759 xfeatures_mask &= fpu__get_supported_xfeatures_mask();
760
761
762 fpu__init_cpu_xstate();
763 err = init_xstate_size();
764 if (err)
765 goto out_disable;
766
767
768
769
770
771 update_regset_xstate_info(fpu_user_xstate_size, xfeatures_mask & ~XFEATURE_MASK_SUPERVISOR);
772
773 fpu__init_prepare_fx_sw_frame();
774 setup_init_fpu_buf();
775 setup_xstate_comp();
776 print_xstate_offset_size();
777
778 pr_info("x86/fpu: Enabled xstate features 0x%llx, context size is %d bytes, using '%s' format.\n",
779 xfeatures_mask,
780 fpu_kernel_xstate_size,
781 boot_cpu_has(X86_FEATURE_XSAVES) ? "compacted" : "standard");
782 return;
783
784 out_disable:
785
786 fpu__init_disable_system_xstate();
787 }
788
789
790
791
792 void fpu__resume_cpu(void)
793 {
794
795
796
797 if (boot_cpu_has(X86_FEATURE_XSAVE))
798 xsetbv(XCR_XFEATURE_ENABLED_MASK, xfeatures_mask);
799 }
800
801
802
803
804
805
806 static void *__raw_xsave_addr(struct xregs_state *xsave, int xfeature_nr)
807 {
808 if (!xfeature_enabled(xfeature_nr)) {
809 WARN_ON_FPU(1);
810 return NULL;
811 }
812
813 return (void *)xsave + xstate_comp_offsets[xfeature_nr];
814 }
815
816
817
818
819
820
821
822
823
824
825
826
827
828
829
830
831
832
833 void *get_xsave_addr(struct xregs_state *xsave, int xfeature_nr)
834 {
835
836
837
838 if (!boot_cpu_has(X86_FEATURE_XSAVE))
839 return NULL;
840
841
842
843
844
845
846 WARN_ONCE(!(xfeatures_mask & BIT_ULL(xfeature_nr)),
847 "get of unsupported state");
848
849
850
851
852
853
854
855
856
857
858
859 if (!(xsave->header.xfeatures & BIT_ULL(xfeature_nr)))
860 return NULL;
861
862 return __raw_xsave_addr(xsave, xfeature_nr);
863 }
864 EXPORT_SYMBOL_GPL(get_xsave_addr);
865
866
867
868
869
870
871
872
873
874
875
876
877
878
879
880
881
882
883 const void *get_xsave_field_ptr(int xfeature_nr)
884 {
885 struct fpu *fpu = ¤t->thread.fpu;
886
887
888
889
890
891 fpu__save(fpu);
892
893 return get_xsave_addr(&fpu->state.xsave, xfeature_nr);
894 }
895
896 #ifdef CONFIG_ARCH_HAS_PKEYS
897
898 #define NR_VALID_PKRU_BITS (CONFIG_NR_PROTECTION_KEYS * 2)
899 #define PKRU_VALID_MASK (NR_VALID_PKRU_BITS - 1)
900
901
902
903
904 int arch_set_user_pkey_access(struct task_struct *tsk, int pkey,
905 unsigned long init_val)
906 {
907 u32 old_pkru;
908 int pkey_shift = (pkey * PKRU_BITS_PER_PKEY);
909 u32 new_pkru_bits = 0;
910
911
912
913
914
915 if (!boot_cpu_has(X86_FEATURE_OSPKE))
916 return -EINVAL;
917
918
919 if (init_val & PKEY_DISABLE_ACCESS)
920 new_pkru_bits |= PKRU_AD_BIT;
921 if (init_val & PKEY_DISABLE_WRITE)
922 new_pkru_bits |= PKRU_WD_BIT;
923
924
925 new_pkru_bits <<= pkey_shift;
926
927
928 old_pkru = read_pkru();
929 old_pkru &= ~((PKRU_AD_BIT|PKRU_WD_BIT) << pkey_shift);
930
931
932 write_pkru(old_pkru | new_pkru_bits);
933
934 return 0;
935 }
936 #endif
937
938
939
940
941
942
943
944 static inline bool xfeatures_mxcsr_quirk(u64 xfeatures)
945 {
946 if (!(xfeatures & (XFEATURE_MASK_SSE|XFEATURE_MASK_YMM)))
947 return false;
948
949 if (xfeatures & XFEATURE_MASK_FP)
950 return false;
951
952 return true;
953 }
954
955 static void fill_gap(unsigned to, void **kbuf, unsigned *pos, unsigned *count)
956 {
957 if (*pos < to) {
958 unsigned size = to - *pos;
959
960 if (size > *count)
961 size = *count;
962 memcpy(*kbuf, (void *)&init_fpstate.xsave + *pos, size);
963 *kbuf += size;
964 *pos += size;
965 *count -= size;
966 }
967 }
968
969 static void copy_part(unsigned offset, unsigned size, void *from,
970 void **kbuf, unsigned *pos, unsigned *count)
971 {
972 fill_gap(offset, kbuf, pos, count);
973 if (size > *count)
974 size = *count;
975 if (size) {
976 memcpy(*kbuf, from, size);
977 *kbuf += size;
978 *pos += size;
979 *count -= size;
980 }
981 }
982
983
984
985
986
987
988
989
990 int copy_xstate_to_kernel(void *kbuf, struct xregs_state *xsave, unsigned int offset_start, unsigned int size_total)
991 {
992 struct xstate_header header;
993 const unsigned off_mxcsr = offsetof(struct fxregs_state, mxcsr);
994 unsigned count = size_total;
995 int i;
996
997
998
999
1000 if (unlikely(offset_start != 0))
1001 return -EFAULT;
1002
1003
1004
1005
1006 memset(&header, 0, sizeof(header));
1007 header.xfeatures = xsave->header.xfeatures;
1008 header.xfeatures &= ~XFEATURE_MASK_SUPERVISOR;
1009
1010 if (header.xfeatures & XFEATURE_MASK_FP)
1011 copy_part(0, off_mxcsr,
1012 &xsave->i387, &kbuf, &offset_start, &count);
1013 if (header.xfeatures & (XFEATURE_MASK_SSE | XFEATURE_MASK_YMM))
1014 copy_part(off_mxcsr, MXCSR_AND_FLAGS_SIZE,
1015 &xsave->i387.mxcsr, &kbuf, &offset_start, &count);
1016 if (header.xfeatures & XFEATURE_MASK_FP)
1017 copy_part(offsetof(struct fxregs_state, st_space), 128,
1018 &xsave->i387.st_space, &kbuf, &offset_start, &count);
1019 if (header.xfeatures & XFEATURE_MASK_SSE)
1020 copy_part(xstate_offsets[XFEATURE_MASK_SSE], 256,
1021 &xsave->i387.xmm_space, &kbuf, &offset_start, &count);
1022
1023
1024
1025 copy_part(offsetof(struct fxregs_state, sw_reserved), 48,
1026 xstate_fx_sw_bytes, &kbuf, &offset_start, &count);
1027
1028
1029
1030 copy_part(offsetof(struct xregs_state, header), sizeof(header),
1031 &header, &kbuf, &offset_start, &count);
1032
1033 for (i = FIRST_EXTENDED_XFEATURE; i < XFEATURE_MAX; i++) {
1034
1035
1036
1037 if ((header.xfeatures >> i) & 1) {
1038 void *src = __raw_xsave_addr(xsave, i);
1039
1040 copy_part(xstate_offsets[i], xstate_sizes[i],
1041 src, &kbuf, &offset_start, &count);
1042 }
1043
1044 }
1045 fill_gap(size_total, &kbuf, &offset_start, &count);
1046
1047 return 0;
1048 }
1049
1050 static inline int
1051 __copy_xstate_to_user(void __user *ubuf, const void *data, unsigned int offset, unsigned int size, unsigned int size_total)
1052 {
1053 if (!size)
1054 return 0;
1055
1056 if (offset < size_total) {
1057 unsigned int copy = min(size, size_total - offset);
1058
1059 if (__copy_to_user(ubuf + offset, data, copy))
1060 return -EFAULT;
1061 }
1062 return 0;
1063 }
1064
1065
1066
1067
1068
1069
1070
1071 int copy_xstate_to_user(void __user *ubuf, struct xregs_state *xsave, unsigned int offset_start, unsigned int size_total)
1072 {
1073 unsigned int offset, size;
1074 int ret, i;
1075 struct xstate_header header;
1076
1077
1078
1079
1080 if (unlikely(offset_start != 0))
1081 return -EFAULT;
1082
1083
1084
1085
1086 memset(&header, 0, sizeof(header));
1087 header.xfeatures = xsave->header.xfeatures;
1088 header.xfeatures &= ~XFEATURE_MASK_SUPERVISOR;
1089
1090
1091
1092
1093 offset = offsetof(struct xregs_state, header);
1094 size = sizeof(header);
1095
1096 ret = __copy_xstate_to_user(ubuf, &header, offset, size, size_total);
1097 if (ret)
1098 return ret;
1099
1100 for (i = 0; i < XFEATURE_MAX; i++) {
1101
1102
1103
1104 if ((header.xfeatures >> i) & 1) {
1105 void *src = __raw_xsave_addr(xsave, i);
1106
1107 offset = xstate_offsets[i];
1108 size = xstate_sizes[i];
1109
1110
1111 if (offset + size > size_total)
1112 break;
1113
1114 ret = __copy_xstate_to_user(ubuf, src, offset, size, size_total);
1115 if (ret)
1116 return ret;
1117 }
1118
1119 }
1120
1121 if (xfeatures_mxcsr_quirk(header.xfeatures)) {
1122 offset = offsetof(struct fxregs_state, mxcsr);
1123 size = MXCSR_AND_FLAGS_SIZE;
1124 __copy_xstate_to_user(ubuf, &xsave->i387.mxcsr, offset, size, size_total);
1125 }
1126
1127
1128
1129
1130 offset = offsetof(struct fxregs_state, sw_reserved);
1131 size = sizeof(xstate_fx_sw_bytes);
1132
1133 ret = __copy_xstate_to_user(ubuf, xstate_fx_sw_bytes, offset, size, size_total);
1134 if (ret)
1135 return ret;
1136
1137 return 0;
1138 }
1139
1140
1141
1142
1143
1144 int copy_kernel_to_xstate(struct xregs_state *xsave, const void *kbuf)
1145 {
1146 unsigned int offset, size;
1147 int i;
1148 struct xstate_header hdr;
1149
1150 offset = offsetof(struct xregs_state, header);
1151 size = sizeof(hdr);
1152
1153 memcpy(&hdr, kbuf + offset, size);
1154
1155 if (validate_xstate_header(&hdr))
1156 return -EINVAL;
1157
1158 for (i = 0; i < XFEATURE_MAX; i++) {
1159 u64 mask = ((u64)1 << i);
1160
1161 if (hdr.xfeatures & mask) {
1162 void *dst = __raw_xsave_addr(xsave, i);
1163
1164 offset = xstate_offsets[i];
1165 size = xstate_sizes[i];
1166
1167 memcpy(dst, kbuf + offset, size);
1168 }
1169 }
1170
1171 if (xfeatures_mxcsr_quirk(hdr.xfeatures)) {
1172 offset = offsetof(struct fxregs_state, mxcsr);
1173 size = MXCSR_AND_FLAGS_SIZE;
1174 memcpy(&xsave->i387.mxcsr, kbuf + offset, size);
1175 }
1176
1177
1178
1179
1180
1181 xsave->header.xfeatures &= XFEATURE_MASK_SUPERVISOR;
1182
1183
1184
1185
1186 xsave->header.xfeatures |= hdr.xfeatures;
1187
1188 return 0;
1189 }
1190
1191
1192
1193
1194
1195
1196
1197 int copy_user_to_xstate(struct xregs_state *xsave, const void __user *ubuf)
1198 {
1199 unsigned int offset, size;
1200 int i;
1201 struct xstate_header hdr;
1202
1203 offset = offsetof(struct xregs_state, header);
1204 size = sizeof(hdr);
1205
1206 if (__copy_from_user(&hdr, ubuf + offset, size))
1207 return -EFAULT;
1208
1209 if (validate_xstate_header(&hdr))
1210 return -EINVAL;
1211
1212 for (i = 0; i < XFEATURE_MAX; i++) {
1213 u64 mask = ((u64)1 << i);
1214
1215 if (hdr.xfeatures & mask) {
1216 void *dst = __raw_xsave_addr(xsave, i);
1217
1218 offset = xstate_offsets[i];
1219 size = xstate_sizes[i];
1220
1221 if (__copy_from_user(dst, ubuf + offset, size))
1222 return -EFAULT;
1223 }
1224 }
1225
1226 if (xfeatures_mxcsr_quirk(hdr.xfeatures)) {
1227 offset = offsetof(struct fxregs_state, mxcsr);
1228 size = MXCSR_AND_FLAGS_SIZE;
1229 if (__copy_from_user(&xsave->i387.mxcsr, ubuf + offset, size))
1230 return -EFAULT;
1231 }
1232
1233
1234
1235
1236
1237 xsave->header.xfeatures &= XFEATURE_MASK_SUPERVISOR;
1238
1239
1240
1241
1242 xsave->header.xfeatures |= hdr.xfeatures;
1243
1244 return 0;
1245 }
1246
1247 #ifdef CONFIG_PROC_PID_ARCH_STATUS
1248
1249
1250
1251
1252 static void avx512_status(struct seq_file *m, struct task_struct *task)
1253 {
1254 unsigned long timestamp = READ_ONCE(task->thread.fpu.avx512_timestamp);
1255 long delta;
1256
1257 if (!timestamp) {
1258
1259
1260
1261 delta = -1;
1262 } else {
1263 delta = (long)(jiffies - timestamp);
1264
1265
1266
1267 if (delta < 0)
1268 delta = LONG_MAX;
1269 delta = jiffies_to_msecs(delta);
1270 }
1271
1272 seq_put_decimal_ll(m, "AVX512_elapsed_ms:\t", delta);
1273 seq_putc(m, '\n');
1274 }
1275
1276
1277
1278
1279 int proc_pid_arch_status(struct seq_file *m, struct pid_namespace *ns,
1280 struct pid *pid, struct task_struct *task)
1281 {
1282
1283
1284
1285 if (cpu_feature_enabled(X86_FEATURE_AVX512F))
1286 avx512_status(m, task);
1287
1288 return 0;
1289 }
1290 #endif