arch/x86/kernel/apic/io

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This source file includes following definitions.
mpc_ioapic_id
mpc_ioapic_addr
mp_ioapic_gsi_routing
mp_ioapic_pin_count
mp_pin_to_gsi
mp_is_legacy_irq
mp_init_irq_at_boot
mp_ioapic_irqdomain
disable_ioapic_support
parse_noapic
mp_save_irq
alloc_ioapic_saved_registers
free_ioapic_saved_registers
arch_early_ioapic_init
io_apic_base
io_apic_eoi
native_io_apic_read
io_apic_write
__ioapic_read_entry
ioapic_read_entry
__ioapic_write_entry
ioapic_write_entry
ioapic_mask_entry
__add_pin_to_irq_node
__remove_pin_from_irq
add_pin_to_irq_node
replace_pin_at_irq_node
io_apic_modify_irq
io_apic_sync
mask_ioapic_irq
__unmask_ioapic
unmask_ioapic_irq
__eoi_ioapic_pin
eoi_ioapic_pin
clear_IO_APIC_pin
clear_IO_APIC
ioapic_pirq_setup
save_ioapic_entries
mask_ioapic_entries
restore_ioapic_entries
find_irq_entry
find_isa_irq_pin
find_isa_irq_apic
EISA_ELCR
irq_polarity
eisa_irq_trigger
eisa_irq_trigger
irq_trigger
ioapic_set_alloc_attr
ioapic_copy_alloc_attr
ioapic_alloc_attr_node
mp_register_handler
mp_check_pin_attr
alloc_irq_from_domain
alloc_isa_irq_from_domain
mp_map_pin_to_irq
pin_2_irq
mp_map_gsi_to_irq
mp_unmap_irq
IO_APIC_get_PCI_irq_vector
setup_IO_APIC_irqs
ioapic_zap_locks
io_apic_print_entries
print_IO_APIC
print_IO_APICs
enable_IO_APIC
native_restore_boot_irq_mode
restore_boot_irq_mode
setup_ioapic_ids_from_mpc_nocheck
setup_ioapic_ids_from_mpc
notimercheck
delay_with_tsc
delay_without_tsc
timer_irq_works
startup_ioapic_irq
io_apic_level_ack_pending
ioapic_irqd_mask
ioapic_irqd_unmask
ioapic_irqd_mask
ioapic_irqd_unmask
ioapic_ack_level
ioapic_ir_ack_level
ioapic_configure_entry
ioapic_set_affinity
ioapic_irq_get_chip_state
init_IO_APIC_traps
mask_lapic_irq
unmask_lapic_irq
ack_lapic_irq
lapic_register_intr
unlock_ExtINT_logic
disable_timer_pin_setup
mp_alloc_timer_irq
check_timer
mp_irqdomain_create
ioapic_destroy_irqdomain
setup_IO_APIC
resume_ioapic_id
ioapic_resume
ioapic_init_ops
io_apic_get_redir_entries
arch_dynirq_lower_bound
io_apic_get_unique_id
io_apic_unique_id
io_apic_unique_id
io_apic_get_version
acpi_get_override_irq
ioapic_setup_resources
io_apic_init_mappings
ioapic_insert_resources
mp_find_ioapic
mp_find_ioapic_pin
bad_ioapic_register
find_free_ioapic_entry
mp_register_ioapic
mp_unregister_ioapic
mp_ioapic_registered
mp_irqdomain_get_attr
mp_setup_entry
mp_irqdomain_alloc
mp_irqdomain_free
mp_irqdomain_activate
mp_irqdomain_deactivate
mp_irqdomain_ioapic_idx
   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  *      Intel IO-APIC support for multi-Pentium hosts.
   4  *
   5  *      Copyright (C) 1997, 1998, 1999, 2000, 2009 Ingo Molnar, Hajnalka Szabo
   6  *
   7  *      Many thanks to Stig Venaas for trying out countless experimental
   8  *      patches and reporting/debugging problems patiently!
   9  *
  10  *      (c) 1999, Multiple IO-APIC support, developed by
  11  *      Ken-ichi Yaku <yaku@css1.kbnes.nec.co.jp> and
  12  *      Hidemi Kishimoto <kisimoto@css1.kbnes.nec.co.jp>,
  13  *      further tested and cleaned up by Zach Brown <zab@redhat.com>
  14  *      and Ingo Molnar <mingo@redhat.com>
  15  *
  16  *      Fixes
  17  *      Maciej W. Rozycki       :       Bits for genuine 82489DX APICs;
  18  *                                      thanks to Eric Gilmore
  19  *                                      and Rolf G. Tews
  20  *                                      for testing these extensively
  21  *      Paul Diefenbaugh        :       Added full ACPI support
  22  *
  23  * Historical information which is worth to be preserved:
  24  *
  25  * - SiS APIC rmw bug:
  26  *
  27  *      We used to have a workaround for a bug in SiS chips which
  28  *      required to rewrite the index register for a read-modify-write
  29  *      operation as the chip lost the index information which was
  30  *      setup for the read already. We cache the data now, so that
  31  *      workaround has been removed.
  32  */
  33 
  34 #include <linux/mm.h>
  35 #include <linux/interrupt.h>
  36 #include <linux/irq.h>
  37 #include <linux/init.h>
  38 #include <linux/delay.h>
  39 #include <linux/sched.h>
  40 #include <linux/pci.h>
  41 #include <linux/mc146818rtc.h>
  42 #include <linux/compiler.h>
  43 #include <linux/acpi.h>
  44 #include <linux/export.h>
  45 #include <linux/syscore_ops.h>
  46 #include <linux/freezer.h>
  47 #include <linux/kthread.h>
  48 #include <linux/jiffies.h>      /* time_after() */
  49 #include <linux/slab.h>
  50 #include <linux/memblock.h>
  51 
  52 #include <asm/irqdomain.h>
  53 #include <asm/io.h>
  54 #include <asm/smp.h>
  55 #include <asm/cpu.h>
  56 #include <asm/desc.h>
  57 #include <asm/proto.h>
  58 #include <asm/acpi.h>
  59 #include <asm/dma.h>
  60 #include <asm/timer.h>
  61 #include <asm/time.h>
  62 #include <asm/i8259.h>
  63 #include <asm/setup.h>
  64 #include <asm/irq_remapping.h>
  65 #include <asm/hw_irq.h>
  66 
  67 #include <asm/apic.h>
  68 
  69 #define for_each_ioapic(idx)            \
  70         for ((idx) = 0; (idx) < nr_ioapics; (idx)++)
  71 #define for_each_ioapic_reverse(idx)    \
  72         for ((idx) = nr_ioapics - 1; (idx) >= 0; (idx)--)
  73 #define for_each_pin(idx, pin)          \
  74         for ((pin) = 0; (pin) < ioapics[(idx)].nr_registers; (pin)++)
  75 #define for_each_ioapic_pin(idx, pin)   \
  76         for_each_ioapic((idx))          \
  77                 for_each_pin((idx), (pin))
  78 #define for_each_irq_pin(entry, head) \
  79         list_for_each_entry(entry, &head, list)
  80 
  81 static DEFINE_RAW_SPINLOCK(ioapic_lock);
  82 static DEFINE_MUTEX(ioapic_mutex);
  83 static unsigned int ioapic_dynirq_base;
  84 static int ioapic_initialized;
  85 
  86 struct irq_pin_list {
  87         struct list_head list;
  88         int apic, pin;
  89 };
  90 
  91 struct mp_chip_data {
  92         struct list_head irq_2_pin;
  93         struct IO_APIC_route_entry entry;
  94         int trigger;
  95         int polarity;
  96         u32 count;
  97         bool isa_irq;
  98 };
  99 
 100 struct mp_ioapic_gsi {
 101         u32 gsi_base;
 102         u32 gsi_end;
 103 };
 104 
 105 static struct ioapic {
 106         /*
 107          * # of IRQ routing registers
 108          */
 109         int nr_registers;
 110         /*
 111          * Saved state during suspend/resume, or while enabling intr-remap.
 112          */
 113         struct IO_APIC_route_entry *saved_registers;
 114         /* I/O APIC config */
 115         struct mpc_ioapic mp_config;
 116         /* IO APIC gsi routing info */
 117         struct mp_ioapic_gsi  gsi_config;
 118         struct ioapic_domain_cfg irqdomain_cfg;
 119         struct irq_domain *irqdomain;
 120         struct resource *iomem_res;
 121 } ioapics[MAX_IO_APICS];
 122 
 123 #define mpc_ioapic_ver(ioapic_idx)      ioapics[ioapic_idx].mp_config.apicver
 124 
 125 int mpc_ioapic_id(int ioapic_idx)
 126 {
 127         return ioapics[ioapic_idx].mp_config.apicid;
 128 }
 129 
 130 unsigned int mpc_ioapic_addr(int ioapic_idx)
 131 {
 132         return ioapics[ioapic_idx].mp_config.apicaddr;
 133 }
 134 
 135 static inline struct mp_ioapic_gsi *mp_ioapic_gsi_routing(int ioapic_idx)
 136 {
 137         return &ioapics[ioapic_idx].gsi_config;
 138 }
 139 
 140 static inline int mp_ioapic_pin_count(int ioapic)
 141 {
 142         struct mp_ioapic_gsi *gsi_cfg = mp_ioapic_gsi_routing(ioapic);
 143 
 144         return gsi_cfg->gsi_end - gsi_cfg->gsi_base + 1;
 145 }
 146 
 147 static inline u32 mp_pin_to_gsi(int ioapic, int pin)
 148 {
 149         return mp_ioapic_gsi_routing(ioapic)->gsi_base + pin;
 150 }
 151 
 152 static inline bool mp_is_legacy_irq(int irq)
 153 {
 154         return irq >= 0 && irq < nr_legacy_irqs();
 155 }
 156 
 157 /*
 158  * Initialize all legacy IRQs and all pins on the first IOAPIC
 159  * if we have legacy interrupt controller. Kernel boot option "pirq="
 160  * may rely on non-legacy pins on the first IOAPIC.
 161  */
 162 static inline int mp_init_irq_at_boot(int ioapic, int irq)
 163 {
 164         if (!nr_legacy_irqs())
 165                 return 0;
 166 
 167         return ioapic == 0 || mp_is_legacy_irq(irq);
 168 }
 169 
 170 static inline struct irq_domain *mp_ioapic_irqdomain(int ioapic)
 171 {
 172         return ioapics[ioapic].irqdomain;
 173 }
 174 
 175 int nr_ioapics;
 176 
 177 /* The one past the highest gsi number used */
 178 u32 gsi_top;
 179 
 180 /* MP IRQ source entries */
 181 struct mpc_intsrc mp_irqs[MAX_IRQ_SOURCES];
 182 
 183 /* # of MP IRQ source entries */
 184 int mp_irq_entries;
 185 
 186 #ifdef CONFIG_EISA
 187 int mp_bus_id_to_type[MAX_MP_BUSSES];
 188 #endif
 189 
 190 DECLARE_BITMAP(mp_bus_not_pci, MAX_MP_BUSSES);
 191 
 192 int skip_ioapic_setup;
 193 
 194 /**
 195  * disable_ioapic_support() - disables ioapic support at runtime
 196  */
 197 void disable_ioapic_support(void)
 198 {
 199 #ifdef CONFIG_PCI
 200         noioapicquirk = 1;
 201         noioapicreroute = -1;
 202 #endif
 203         skip_ioapic_setup = 1;
 204 }
 205 
 206 static int __init parse_noapic(char *str)
 207 {
 208         /* disable IO-APIC */
 209         disable_ioapic_support();
 210         return 0;
 211 }
 212 early_param("noapic", parse_noapic);
 213 
 214 /* Will be called in mpparse/acpi/sfi codes for saving IRQ info */
 215 void mp_save_irq(struct mpc_intsrc *m)
 216 {
 217         int i;
 218 
 219         apic_printk(APIC_VERBOSE, "Int: type %d, pol %d, trig %d, bus %02x,"
 220                 " IRQ %02x, APIC ID %x, APIC INT %02x\n",
 221                 m->irqtype, m->irqflag & 3, (m->irqflag >> 2) & 3, m->srcbus,
 222                 m->srcbusirq, m->dstapic, m->dstirq);
 223 
 224         for (i = 0; i < mp_irq_entries; i++) {
 225                 if (!memcmp(&mp_irqs[i], m, sizeof(*m)))
 226                         return;
 227         }
 228 
 229         memcpy(&mp_irqs[mp_irq_entries], m, sizeof(*m));
 230         if (++mp_irq_entries == MAX_IRQ_SOURCES)
 231                 panic("Max # of irq sources exceeded!!\n");
 232 }
 233 
 234 static void alloc_ioapic_saved_registers(int idx)
 235 {
 236         size_t size;
 237 
 238         if (ioapics[idx].saved_registers)
 239                 return;
 240 
 241         size = sizeof(struct IO_APIC_route_entry) * ioapics[idx].nr_registers;
 242         ioapics[idx].saved_registers = kzalloc(size, GFP_KERNEL);
 243         if (!ioapics[idx].saved_registers)
 244                 pr_err("IOAPIC %d: suspend/resume impossible!\n", idx);
 245 }
 246 
 247 static void free_ioapic_saved_registers(int idx)
 248 {
 249         kfree(ioapics[idx].saved_registers);
 250         ioapics[idx].saved_registers = NULL;
 251 }
 252 
 253 int __init arch_early_ioapic_init(void)
 254 {
 255         int i;
 256 
 257         if (!nr_legacy_irqs())
 258                 io_apic_irqs = ~0UL;
 259 
 260         for_each_ioapic(i)
 261                 alloc_ioapic_saved_registers(i);
 262 
 263         return 0;
 264 }
 265 
 266 struct io_apic {
 267         unsigned int index;
 268         unsigned int unused[3];
 269         unsigned int data;
 270         unsigned int unused2[11];
 271         unsigned int eoi;
 272 };
 273 
 274 static __attribute_const__ struct io_apic __iomem *io_apic_base(int idx)
 275 {
 276         return (void __iomem *) __fix_to_virt(FIX_IO_APIC_BASE_0 + idx)
 277                 + (mpc_ioapic_addr(idx) & ~PAGE_MASK);
 278 }
 279 
 280 static inline void io_apic_eoi(unsigned int apic, unsigned int vector)
 281 {
 282         struct io_apic __iomem *io_apic = io_apic_base(apic);
 283         writel(vector, &io_apic->eoi);
 284 }
 285 
 286 unsigned int native_io_apic_read(unsigned int apic, unsigned int reg)
 287 {
 288         struct io_apic __iomem *io_apic = io_apic_base(apic);
 289         writel(reg, &io_apic->index);
 290         return readl(&io_apic->data);
 291 }
 292 
 293 static void io_apic_write(unsigned int apic, unsigned int reg,
 294                           unsigned int value)
 295 {
 296         struct io_apic __iomem *io_apic = io_apic_base(apic);
 297 
 298         writel(reg, &io_apic->index);
 299         writel(value, &io_apic->data);
 300 }
 301 
 302 union entry_union {
 303         struct { u32 w1, w2; };
 304         struct IO_APIC_route_entry entry;
 305 };
 306 
 307 static struct IO_APIC_route_entry __ioapic_read_entry(int apic, int pin)
 308 {
 309         union entry_union eu;
 310 
 311         eu.w1 = io_apic_read(apic, 0x10 + 2 * pin);
 312         eu.w2 = io_apic_read(apic, 0x11 + 2 * pin);
 313 
 314         return eu.entry;
 315 }
 316 
 317 static struct IO_APIC_route_entry ioapic_read_entry(int apic, int pin)
 318 {
 319         union entry_union eu;
 320         unsigned long flags;
 321 
 322         raw_spin_lock_irqsave(&ioapic_lock, flags);
 323         eu.entry = __ioapic_read_entry(apic, pin);
 324         raw_spin_unlock_irqrestore(&ioapic_lock, flags);
 325 
 326         return eu.entry;
 327 }
 328 
 329 /*
 330  * When we write a new IO APIC routing entry, we need to write the high
 331  * word first! If the mask bit in the low word is clear, we will enable
 332  * the interrupt, and we need to make sure the entry is fully populated
 333  * before that happens.
 334  */
 335 static void __ioapic_write_entry(int apic, int pin, struct IO_APIC_route_entry e)
 336 {
 337         union entry_union eu = {{0, 0}};
 338 
 339         eu.entry = e;
 340         io_apic_write(apic, 0x11 + 2*pin, eu.w2);
 341         io_apic_write(apic, 0x10 + 2*pin, eu.w1);
 342 }
 343 
 344 static void ioapic_write_entry(int apic, int pin, struct IO_APIC_route_entry e)
 345 {
 346         unsigned long flags;
 347 
 348         raw_spin_lock_irqsave(&ioapic_lock, flags);
 349         __ioapic_write_entry(apic, pin, e);
 350         raw_spin_unlock_irqrestore(&ioapic_lock, flags);
 351 }
 352 
 353 /*
 354  * When we mask an IO APIC routing entry, we need to write the low
 355  * word first, in order to set the mask bit before we change the
 356  * high bits!
 357  */
 358 static void ioapic_mask_entry(int apic, int pin)
 359 {
 360         unsigned long flags;
 361         union entry_union eu = { .entry.mask = IOAPIC_MASKED };
 362 
 363         raw_spin_lock_irqsave(&ioapic_lock, flags);
 364         io_apic_write(apic, 0x10 + 2*pin, eu.w1);
 365         io_apic_write(apic, 0x11 + 2*pin, eu.w2);
 366         raw_spin_unlock_irqrestore(&ioapic_lock, flags);
 367 }
 368 
 369 /*
 370  * The common case is 1:1 IRQ<->pin mappings. Sometimes there are
 371  * shared ISA-space IRQs, so we have to support them. We are super
 372  * fast in the common case, and fast for shared ISA-space IRQs.
 373  */
 374 static int __add_pin_to_irq_node(struct mp_chip_data *data,
 375                                  int node, int apic, int pin)
 376 {
 377         struct irq_pin_list *entry;
 378 
 379         /* don't allow duplicates */
 380         for_each_irq_pin(entry, data->irq_2_pin)
 381                 if (entry->apic == apic && entry->pin == pin)
 382                         return 0;
 383 
 384         entry = kzalloc_node(sizeof(struct irq_pin_list), GFP_ATOMIC, node);
 385         if (!entry) {
 386                 pr_err("can not alloc irq_pin_list (%d,%d,%d)\n",
 387                        node, apic, pin);
 388                 return -ENOMEM;
 389         }
 390         entry->apic = apic;
 391         entry->pin = pin;
 392         list_add_tail(&entry->list, &data->irq_2_pin);
 393 
 394         return 0;
 395 }
 396 
 397 static void __remove_pin_from_irq(struct mp_chip_data *data, int apic, int pin)
 398 {
 399         struct irq_pin_list *tmp, *entry;
 400 
 401         list_for_each_entry_safe(entry, tmp, &data->irq_2_pin, list)
 402                 if (entry->apic == apic && entry->pin == pin) {
 403                         list_del(&entry->list);
 404                         kfree(entry);
 405                         return;
 406                 }
 407 }
 408 
 409 static void add_pin_to_irq_node(struct mp_chip_data *data,
 410                                 int node, int apic, int pin)
 411 {
 412         if (__add_pin_to_irq_node(data, node, apic, pin))
 413                 panic("IO-APIC: failed to add irq-pin. Can not proceed\n");
 414 }
 415 
 416 /*
 417  * Reroute an IRQ to a different pin.
 418  */
 419 static void __init replace_pin_at_irq_node(struct mp_chip_data *data, int node,
 420                                            int oldapic, int oldpin,
 421                                            int newapic, int newpin)
 422 {
 423         struct irq_pin_list *entry;
 424 
 425         for_each_irq_pin(entry, data->irq_2_pin) {
 426                 if (entry->apic == oldapic && entry->pin == oldpin) {
 427                         entry->apic = newapic;
 428                         entry->pin = newpin;
 429                         /* every one is different, right? */
 430                         return;
 431                 }
 432         }
 433 
 434         /* old apic/pin didn't exist, so just add new ones */
 435         add_pin_to_irq_node(data, node, newapic, newpin);
 436 }
 437 
 438 static void io_apic_modify_irq(struct mp_chip_data *data,
 439                                int mask_and, int mask_or,
 440                                void (*final)(struct irq_pin_list *entry))
 441 {
 442         union entry_union eu;
 443         struct irq_pin_list *entry;
 444 
 445         eu.entry = data->entry;
 446         eu.w1 &= mask_and;
 447         eu.w1 |= mask_or;
 448         data->entry = eu.entry;
 449 
 450         for_each_irq_pin(entry, data->irq_2_pin) {
 451                 io_apic_write(entry->apic, 0x10 + 2 * entry->pin, eu.w1);
 452                 if (final)
 453                         final(entry);
 454         }
 455 }
 456 
 457 static void io_apic_sync(struct irq_pin_list *entry)
 458 {
 459         /*
 460          * Synchronize the IO-APIC and the CPU by doing
 461          * a dummy read from the IO-APIC
 462          */
 463         struct io_apic __iomem *io_apic;
 464 
 465         io_apic = io_apic_base(entry->apic);
 466         readl(&io_apic->data);
 467 }
 468 
 469 static void mask_ioapic_irq(struct irq_data *irq_data)
 470 {
 471         struct mp_chip_data *data = irq_data->chip_data;
 472         unsigned long flags;
 473 
 474         raw_spin_lock_irqsave(&ioapic_lock, flags);
 475         io_apic_modify_irq(data, ~0, IO_APIC_REDIR_MASKED, &io_apic_sync);
 476         raw_spin_unlock_irqrestore(&ioapic_lock, flags);
 477 }
 478 
 479 static void __unmask_ioapic(struct mp_chip_data *data)
 480 {
 481         io_apic_modify_irq(data, ~IO_APIC_REDIR_MASKED, 0, NULL);
 482 }
 483 
 484 static void unmask_ioapic_irq(struct irq_data *irq_data)
 485 {
 486         struct mp_chip_data *data = irq_data->chip_data;
 487         unsigned long flags;
 488 
 489         raw_spin_lock_irqsave(&ioapic_lock, flags);
 490         __unmask_ioapic(data);
 491         raw_spin_unlock_irqrestore(&ioapic_lock, flags);
 492 }
 493 
 494 /*
 495  * IO-APIC versions below 0x20 don't support EOI register.
 496  * For the record, here is the information about various versions:
 497  *     0Xh     82489DX
 498  *     1Xh     I/OAPIC or I/O(x)APIC which are not PCI 2.2 Compliant
 499  *     2Xh     I/O(x)APIC which is PCI 2.2 Compliant
 500  *     30h-FFh Reserved
 501  *
 502  * Some of the Intel ICH Specs (ICH2 to ICH5) documents the io-apic
 503  * version as 0x2. This is an error with documentation and these ICH chips
 504  * use io-apic's of version 0x20.
 505  *
 506  * For IO-APIC's with EOI register, we use that to do an explicit EOI.
 507  * Otherwise, we simulate the EOI message manually by changing the trigger
 508  * mode to edge and then back to level, with RTE being masked during this.
 509  */
 510 static void __eoi_ioapic_pin(int apic, int pin, int vector)
 511 {
 512         if (mpc_ioapic_ver(apic) >= 0x20) {
 513                 io_apic_eoi(apic, vector);
 514         } else {
 515                 struct IO_APIC_route_entry entry, entry1;
 516 
 517                 entry = entry1 = __ioapic_read_entry(apic, pin);
 518 
 519                 /*
 520                  * Mask the entry and change the trigger mode to edge.
 521                  */
 522                 entry1.mask = IOAPIC_MASKED;
 523                 entry1.trigger = IOAPIC_EDGE;
 524 
 525                 __ioapic_write_entry(apic, pin, entry1);
 526 
 527                 /*
 528                  * Restore the previous level triggered entry.
 529                  */
 530                 __ioapic_write_entry(apic, pin, entry);
 531         }
 532 }
 533 
 534 static void eoi_ioapic_pin(int vector, struct mp_chip_data *data)
 535 {
 536         unsigned long flags;
 537         struct irq_pin_list *entry;
 538 
 539         raw_spin_lock_irqsave(&ioapic_lock, flags);
 540         for_each_irq_pin(entry, data->irq_2_pin)
 541                 __eoi_ioapic_pin(entry->apic, entry->pin, vector);
 542         raw_spin_unlock_irqrestore(&ioapic_lock, flags);
 543 }
 544 
 545 static void clear_IO_APIC_pin(unsigned int apic, unsigned int pin)
 546 {
 547         struct IO_APIC_route_entry entry;
 548 
 549         /* Check delivery_mode to be sure we're not clearing an SMI pin */
 550         entry = ioapic_read_entry(apic, pin);
 551         if (entry.delivery_mode == dest_SMI)
 552                 return;
 553 
 554         /*
 555          * Make sure the entry is masked and re-read the contents to check
 556          * if it is a level triggered pin and if the remote-IRR is set.
 557          */
 558         if (entry.mask == IOAPIC_UNMASKED) {
 559                 entry.mask = IOAPIC_MASKED;
 560                 ioapic_write_entry(apic, pin, entry);
 561                 entry = ioapic_read_entry(apic, pin);
 562         }
 563 
 564         if (entry.irr) {
 565                 unsigned long flags;
 566 
 567                 /*
 568                  * Make sure the trigger mode is set to level. Explicit EOI
 569                  * doesn't clear the remote-IRR if the trigger mode is not
 570                  * set to level.
 571                  */
 572                 if (entry.trigger == IOAPIC_EDGE) {
 573                         entry.trigger = IOAPIC_LEVEL;
 574                         ioapic_write_entry(apic, pin, entry);
 575                 }
 576                 raw_spin_lock_irqsave(&ioapic_lock, flags);
 577                 __eoi_ioapic_pin(apic, pin, entry.vector);
 578                 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
 579         }
 580 
 581         /*
 582          * Clear the rest of the bits in the IO-APIC RTE except for the mask
 583          * bit.
 584          */
 585         ioapic_mask_entry(apic, pin);
 586         entry = ioapic_read_entry(apic, pin);
 587         if (entry.irr)
 588                 pr_err("Unable to reset IRR for apic: %d, pin :%d\n",
 589                        mpc_ioapic_id(apic), pin);
 590 }
 591 
 592 void clear_IO_APIC (void)
 593 {
 594         int apic, pin;
 595 
 596         for_each_ioapic_pin(apic, pin)
 597                 clear_IO_APIC_pin(apic, pin);
 598 }
 599 
 600 #ifdef CONFIG_X86_32
 601 /*
 602  * support for broken MP BIOSs, enables hand-redirection of PIRQ0-7 to
 603  * specific CPU-side IRQs.
 604  */
 605 
 606 #define MAX_PIRQS 8
 607 static int pirq_entries[MAX_PIRQS] = {
 608         [0 ... MAX_PIRQS - 1] = -1
 609 };
 610 
 611 static int __init ioapic_pirq_setup(char *str)
 612 {
 613         int i, max;
 614         int ints[MAX_PIRQS+1];
 615 
 616         get_options(str, ARRAY_SIZE(ints), ints);
 617 
 618         apic_printk(APIC_VERBOSE, KERN_INFO
 619                         "PIRQ redirection, working around broken MP-BIOS.\n");
 620         max = MAX_PIRQS;
 621         if (ints[0] < MAX_PIRQS)
 622                 max = ints[0];
 623 
 624         for (i = 0; i < max; i++) {
 625                 apic_printk(APIC_VERBOSE, KERN_DEBUG
 626                                 "... PIRQ%d -> IRQ %d\n", i, ints[i+1]);
 627                 /*
 628                  * PIRQs are mapped upside down, usually.
 629                  */
 630                 pirq_entries[MAX_PIRQS-i-1] = ints[i+1];
 631         }
 632         return 1;
 633 }
 634 
 635 __setup("pirq=", ioapic_pirq_setup);
 636 #endif /* CONFIG_X86_32 */
 637 
 638 /*
 639  * Saves all the IO-APIC RTE's
 640  */
 641 int save_ioapic_entries(void)
 642 {
 643         int apic, pin;
 644         int err = 0;
 645 
 646         for_each_ioapic(apic) {
 647                 if (!ioapics[apic].saved_registers) {
 648                         err = -ENOMEM;
 649                         continue;
 650                 }
 651 
 652                 for_each_pin(apic, pin)
 653                         ioapics[apic].saved_registers[pin] =
 654                                 ioapic_read_entry(apic, pin);
 655         }
 656 
 657         return err;
 658 }
 659 
 660 /*
 661  * Mask all IO APIC entries.
 662  */
 663 void mask_ioapic_entries(void)
 664 {
 665         int apic, pin;
 666 
 667         for_each_ioapic(apic) {
 668                 if (!ioapics[apic].saved_registers)
 669                         continue;
 670 
 671                 for_each_pin(apic, pin) {
 672                         struct IO_APIC_route_entry entry;
 673 
 674                         entry = ioapics[apic].saved_registers[pin];
 675                         if (entry.mask == IOAPIC_UNMASKED) {
 676                                 entry.mask = IOAPIC_MASKED;
 677                                 ioapic_write_entry(apic, pin, entry);
 678                         }
 679                 }
 680         }
 681 }
 682 
 683 /*
 684  * Restore IO APIC entries which was saved in the ioapic structure.
 685  */
 686 int restore_ioapic_entries(void)
 687 {
 688         int apic, pin;
 689 
 690         for_each_ioapic(apic) {
 691                 if (!ioapics[apic].saved_registers)
 692                         continue;
 693 
 694                 for_each_pin(apic, pin)
 695                         ioapic_write_entry(apic, pin,
 696                                            ioapics[apic].saved_registers[pin]);
 697         }
 698         return 0;
 699 }
 700 
 701 /*
 702  * Find the IRQ entry number of a certain pin.
 703  */
 704 static int find_irq_entry(int ioapic_idx, int pin, int type)
 705 {
 706         int i;
 707 
 708         for (i = 0; i < mp_irq_entries; i++)
 709                 if (mp_irqs[i].irqtype == type &&
 710                     (mp_irqs[i].dstapic == mpc_ioapic_id(ioapic_idx) ||
 711                      mp_irqs[i].dstapic == MP_APIC_ALL) &&
 712                     mp_irqs[i].dstirq == pin)
 713                         return i;
 714 
 715         return -1;
 716 }
 717 
 718 /*
 719  * Find the pin to which IRQ[irq] (ISA) is connected
 720  */
 721 static int __init find_isa_irq_pin(int irq, int type)
 722 {
 723         int i;
 724 
 725         for (i = 0; i < mp_irq_entries; i++) {
 726                 int lbus = mp_irqs[i].srcbus;
 727 
 728                 if (test_bit(lbus, mp_bus_not_pci) &&
 729                     (mp_irqs[i].irqtype == type) &&
 730                     (mp_irqs[i].srcbusirq == irq))
 731 
 732                         return mp_irqs[i].dstirq;
 733         }
 734         return -1;
 735 }
 736 
 737 static int __init find_isa_irq_apic(int irq, int type)
 738 {
 739         int i;
 740 
 741         for (i = 0; i < mp_irq_entries; i++) {
 742                 int lbus = mp_irqs[i].srcbus;
 743 
 744                 if (test_bit(lbus, mp_bus_not_pci) &&
 745                     (mp_irqs[i].irqtype == type) &&
 746                     (mp_irqs[i].srcbusirq == irq))
 747                         break;
 748         }
 749 
 750         if (i < mp_irq_entries) {
 751                 int ioapic_idx;
 752 
 753                 for_each_ioapic(ioapic_idx)
 754                         if (mpc_ioapic_id(ioapic_idx) == mp_irqs[i].dstapic)
 755                                 return ioapic_idx;
 756         }
 757 
 758         return -1;
 759 }
 760 
 761 #ifdef CONFIG_EISA
 762 /*
 763  * EISA Edge/Level control register, ELCR
 764  */
 765 static int EISA_ELCR(unsigned int irq)
 766 {
 767         if (irq < nr_legacy_irqs()) {
 768                 unsigned int port = 0x4d0 + (irq >> 3);
 769                 return (inb(port) >> (irq & 7)) & 1;
 770         }
 771         apic_printk(APIC_VERBOSE, KERN_INFO
 772                         "Broken MPtable reports ISA irq %d\n", irq);
 773         return 0;
 774 }
 775 
 776 #endif
 777 
 778 /* ISA interrupts are always active high edge triggered,
 779  * when listed as conforming in the MP table. */
 780 
 781 #define default_ISA_trigger(idx)        (IOAPIC_EDGE)
 782 #define default_ISA_polarity(idx)       (IOAPIC_POL_HIGH)
 783 
 784 /* EISA interrupts are always polarity zero and can be edge or level
 785  * trigger depending on the ELCR value.  If an interrupt is listed as
 786  * EISA conforming in the MP table, that means its trigger type must
 787  * be read in from the ELCR */
 788 
 789 #define default_EISA_trigger(idx)       (EISA_ELCR(mp_irqs[idx].srcbusirq))
 790 #define default_EISA_polarity(idx)      default_ISA_polarity(idx)
 791 
 792 /* PCI interrupts are always active low level triggered,
 793  * when listed as conforming in the MP table. */
 794 
 795 #define default_PCI_trigger(idx)        (IOAPIC_LEVEL)
 796 #define default_PCI_polarity(idx)       (IOAPIC_POL_LOW)
 797 
 798 static int irq_polarity(int idx)
 799 {
 800         int bus = mp_irqs[idx].srcbus;
 801 
 802         /*
 803          * Determine IRQ line polarity (high active or low active):
 804          */
 805         switch (mp_irqs[idx].irqflag & MP_IRQPOL_MASK) {
 806         case MP_IRQPOL_DEFAULT:
 807                 /* conforms to spec, ie. bus-type dependent polarity */
 808                 if (test_bit(bus, mp_bus_not_pci))
 809                         return default_ISA_polarity(idx);
 810                 else
 811                         return default_PCI_polarity(idx);
 812         case MP_IRQPOL_ACTIVE_HIGH:
 813                 return IOAPIC_POL_HIGH;
 814         case MP_IRQPOL_RESERVED:
 815                 pr_warn("IOAPIC: Invalid polarity: 2, defaulting to low\n");
 816                 /* fall through */
 817         case MP_IRQPOL_ACTIVE_LOW:
 818         default: /* Pointless default required due to do gcc stupidity */
 819                 return IOAPIC_POL_LOW;
 820         }
 821 }
 822 
 823 #ifdef CONFIG_EISA
 824 static int eisa_irq_trigger(int idx, int bus, int trigger)
 825 {
 826         switch (mp_bus_id_to_type[bus]) {
 827         case MP_BUS_PCI:
 828         case MP_BUS_ISA:
 829                 return trigger;
 830         case MP_BUS_EISA:
 831                 return default_EISA_trigger(idx);
 832         }
 833         pr_warn("IOAPIC: Invalid srcbus: %d defaulting to level\n", bus);
 834         return IOAPIC_LEVEL;
 835 }
 836 #else
 837 static inline int eisa_irq_trigger(int idx, int bus, int trigger)
 838 {
 839         return trigger;
 840 }
 841 #endif
 842 
 843 static int irq_trigger(int idx)
 844 {
 845         int bus = mp_irqs[idx].srcbus;
 846         int trigger;
 847 
 848         /*
 849          * Determine IRQ trigger mode (edge or level sensitive):
 850          */
 851         switch (mp_irqs[idx].irqflag & MP_IRQTRIG_MASK) {
 852         case MP_IRQTRIG_DEFAULT:
 853                 /* conforms to spec, ie. bus-type dependent trigger mode */
 854                 if (test_bit(bus, mp_bus_not_pci))
 855                         trigger = default_ISA_trigger(idx);
 856                 else
 857                         trigger = default_PCI_trigger(idx);
 858                 /* Take EISA into account */
 859                 return eisa_irq_trigger(idx, bus, trigger);
 860         case MP_IRQTRIG_EDGE:
 861                 return IOAPIC_EDGE;
 862         case MP_IRQTRIG_RESERVED:
 863                 pr_warn("IOAPIC: Invalid trigger mode 2 defaulting to level\n");
 864                 /* fall through */
 865         case MP_IRQTRIG_LEVEL:
 866         default: /* Pointless default required due to do gcc stupidity */
 867                 return IOAPIC_LEVEL;
 868         }
 869 }
 870 
 871 void ioapic_set_alloc_attr(struct irq_alloc_info *info, int node,
 872                            int trigger, int polarity)
 873 {
 874         init_irq_alloc_info(info, NULL);
 875         info->type = X86_IRQ_ALLOC_TYPE_IOAPIC;
 876         info->ioapic_node = node;
 877         info->ioapic_trigger = trigger;
 878         info->ioapic_polarity = polarity;
 879         info->ioapic_valid = 1;
 880 }
 881 
 882 #ifndef CONFIG_ACPI
 883 int acpi_get_override_irq(u32 gsi, int *trigger, int *polarity);
 884 #endif
 885 
 886 static void ioapic_copy_alloc_attr(struct irq_alloc_info *dst,
 887                                    struct irq_alloc_info *src,
 888                                    u32 gsi, int ioapic_idx, int pin)
 889 {
 890         int trigger, polarity;
 891 
 892         copy_irq_alloc_info(dst, src);
 893         dst->type = X86_IRQ_ALLOC_TYPE_IOAPIC;
 894         dst->ioapic_id = mpc_ioapic_id(ioapic_idx);
 895         dst->ioapic_pin = pin;
 896         dst->ioapic_valid = 1;
 897         if (src && src->ioapic_valid) {
 898                 dst->ioapic_node = src->ioapic_node;
 899                 dst->ioapic_trigger = src->ioapic_trigger;
 900                 dst->ioapic_polarity = src->ioapic_polarity;
 901         } else {
 902                 dst->ioapic_node = NUMA_NO_NODE;
 903                 if (acpi_get_override_irq(gsi, &trigger, &polarity) >= 0) {
 904                         dst->ioapic_trigger = trigger;
 905                         dst->ioapic_polarity = polarity;
 906                 } else {
 907                         /*
 908                          * PCI interrupts are always active low level
 909                          * triggered.
 910                          */
 911                         dst->ioapic_trigger = IOAPIC_LEVEL;
 912                         dst->ioapic_polarity = IOAPIC_POL_LOW;
 913                 }
 914         }
 915 }
 916 
 917 static int ioapic_alloc_attr_node(struct irq_alloc_info *info)
 918 {
 919         return (info && info->ioapic_valid) ? info->ioapic_node : NUMA_NO_NODE;
 920 }
 921 
 922 static void mp_register_handler(unsigned int irq, unsigned long trigger)
 923 {
 924         irq_flow_handler_t hdl;
 925         bool fasteoi;
 926 
 927         if (trigger) {
 928                 irq_set_status_flags(irq, IRQ_LEVEL);
 929                 fasteoi = true;
 930         } else {
 931                 irq_clear_status_flags(irq, IRQ_LEVEL);
 932                 fasteoi = false;
 933         }
 934 
 935         hdl = fasteoi ? handle_fasteoi_irq : handle_edge_irq;
 936         __irq_set_handler(irq, hdl, 0, fasteoi ? "fasteoi" : "edge");
 937 }
 938 
 939 static bool mp_check_pin_attr(int irq, struct irq_alloc_info *info)
 940 {
 941         struct mp_chip_data *data = irq_get_chip_data(irq);
 942 
 943         /*
 944          * setup_IO_APIC_irqs() programs all legacy IRQs with default trigger
 945          * and polarity attirbutes. So allow the first user to reprogram the
 946          * pin with real trigger and polarity attributes.
 947          */
 948         if (irq < nr_legacy_irqs() && data->count == 1) {
 949                 if (info->ioapic_trigger != data->trigger)
 950                         mp_register_handler(irq, info->ioapic_trigger);
 951                 data->entry.trigger = data->trigger = info->ioapic_trigger;
 952                 data->entry.polarity = data->polarity = info->ioapic_polarity;
 953         }
 954 
 955         return data->trigger == info->ioapic_trigger &&
 956                data->polarity == info->ioapic_polarity;
 957 }
 958 
 959 static int alloc_irq_from_domain(struct irq_domain *domain, int ioapic, u32 gsi,
 960                                  struct irq_alloc_info *info)
 961 {
 962         bool legacy = false;
 963         int irq = -1;
 964         int type = ioapics[ioapic].irqdomain_cfg.type;
 965 
 966         switch (type) {
 967         case IOAPIC_DOMAIN_LEGACY:
 968                 /*
 969                  * Dynamically allocate IRQ number for non-ISA IRQs in the first
 970                  * 16 GSIs on some weird platforms.
 971                  */
 972                 if (!ioapic_initialized || gsi >= nr_legacy_irqs())
 973                         irq = gsi;
 974                 legacy = mp_is_legacy_irq(irq);
 975                 break;
 976         case IOAPIC_DOMAIN_STRICT:
 977                 irq = gsi;
 978                 break;
 979         case IOAPIC_DOMAIN_DYNAMIC:
 980                 break;
 981         default:
 982                 WARN(1, "ioapic: unknown irqdomain type %d\n", type);
 983                 return -1;
 984         }
 985 
 986         return __irq_domain_alloc_irqs(domain, irq, 1,
 987                                        ioapic_alloc_attr_node(info),
 988                                        info, legacy, NULL);
 989 }
 990 
 991 /*
 992  * Need special handling for ISA IRQs because there may be multiple IOAPIC pins
 993  * sharing the same ISA IRQ number and irqdomain only supports 1:1 mapping
 994  * between IOAPIC pin and IRQ number. A typical IOAPIC has 24 pins, pin 0-15 are
 995  * used for legacy IRQs and pin 16-23 are used for PCI IRQs (PIRQ A-H).
 996  * When ACPI is disabled, only legacy IRQ numbers (IRQ0-15) are available, and
 997  * some BIOSes may use MP Interrupt Source records to override IRQ numbers for
 998  * PIRQs instead of reprogramming the interrupt routing logic. Thus there may be
 999  * multiple pins sharing the same legacy IRQ number when ACPI is disabled.
1000  */
1001 static int alloc_isa_irq_from_domain(struct irq_domain *domain,
1002                                      int irq, int ioapic, int pin,
1003                                      struct irq_alloc_info *info)
1004 {
1005         struct mp_chip_data *data;
1006         struct irq_data *irq_data = irq_get_irq_data(irq);
1007         int node = ioapic_alloc_attr_node(info);
1008 
1009         /*
1010          * Legacy ISA IRQ has already been allocated, just add pin to
1011          * the pin list assoicated with this IRQ and program the IOAPIC
1012          * entry. The IOAPIC entry
1013          */
1014         if (irq_data && irq_data->parent_data) {
1015                 if (!mp_check_pin_attr(irq, info))
1016                         return -EBUSY;
1017                 if (__add_pin_to_irq_node(irq_data->chip_data, node, ioapic,
1018                                           info->ioapic_pin))
1019                         return -ENOMEM;
1020         } else {
1021                 info->flags |= X86_IRQ_ALLOC_LEGACY;
1022                 irq = __irq_domain_alloc_irqs(domain, irq, 1, node, info, true,
1023                                               NULL);
1024                 if (irq >= 0) {
1025                         irq_data = irq_domain_get_irq_data(domain, irq);
1026                         data = irq_data->chip_data;
1027                         data->isa_irq = true;
1028                 }
1029         }
1030 
1031         return irq;
1032 }
1033 
1034 static int mp_map_pin_to_irq(u32 gsi, int idx, int ioapic, int pin,
1035                              unsigned int flags, struct irq_alloc_info *info)
1036 {
1037         int irq;
1038         bool legacy = false;
1039         struct irq_alloc_info tmp;
1040         struct mp_chip_data *data;
1041         struct irq_domain *domain = mp_ioapic_irqdomain(ioapic);
1042 
1043         if (!domain)
1044                 return -ENOSYS;
1045 
1046         if (idx >= 0 && test_bit(mp_irqs[idx].srcbus, mp_bus_not_pci)) {
1047                 irq = mp_irqs[idx].srcbusirq;
1048                 legacy = mp_is_legacy_irq(irq);
1049         }
1050 
1051         mutex_lock(&ioapic_mutex);
1052         if (!(flags & IOAPIC_MAP_ALLOC)) {
1053                 if (!legacy) {
1054                         irq = irq_find_mapping(domain, pin);
1055                         if (irq == 0)
1056                                 irq = -ENOENT;
1057                 }
1058         } else {
1059                 ioapic_copy_alloc_attr(&tmp, info, gsi, ioapic, pin);
1060                 if (legacy)
1061                         irq = alloc_isa_irq_from_domain(domain, irq,
1062                                                         ioapic, pin, &tmp);
1063                 else if ((irq = irq_find_mapping(domain, pin)) == 0)
1064                         irq = alloc_irq_from_domain(domain, ioapic, gsi, &tmp);
1065                 else if (!mp_check_pin_attr(irq, &tmp))
1066                         irq = -EBUSY;
1067                 if (irq >= 0) {
1068                         data = irq_get_chip_data(irq);
1069                         data->count++;
1070                 }
1071         }
1072         mutex_unlock(&ioapic_mutex);
1073 
1074         return irq;
1075 }
1076 
1077 static int pin_2_irq(int idx, int ioapic, int pin, unsigned int flags)
1078 {
1079         u32 gsi = mp_pin_to_gsi(ioapic, pin);
1080 
1081         /*
1082          * Debugging check, we are in big trouble if this message pops up!
1083          */
1084         if (mp_irqs[idx].dstirq != pin)
1085                 pr_err("broken BIOS or MPTABLE parser, ayiee!!\n");
1086 
1087 #ifdef CONFIG_X86_32
1088         /*
1089          * PCI IRQ command line redirection. Yes, limits are hardcoded.
1090          */
1091         if ((pin >= 16) && (pin <= 23)) {
1092                 if (pirq_entries[pin-16] != -1) {
1093                         if (!pirq_entries[pin-16]) {
1094                                 apic_printk(APIC_VERBOSE, KERN_DEBUG
1095                                                 "disabling PIRQ%d\n", pin-16);
1096                         } else {
1097                                 int irq = pirq_entries[pin-16];
1098                                 apic_printk(APIC_VERBOSE, KERN_DEBUG
1099                                                 "using PIRQ%d -> IRQ %d\n",
1100                                                 pin-16, irq);
1101                                 return irq;
1102                         }
1103                 }
1104         }
1105 #endif
1106 
1107         return  mp_map_pin_to_irq(gsi, idx, ioapic, pin, flags, NULL);
1108 }
1109 
1110 int mp_map_gsi_to_irq(u32 gsi, unsigned int flags, struct irq_alloc_info *info)
1111 {
1112         int ioapic, pin, idx;
1113 
1114         ioapic = mp_find_ioapic(gsi);
1115         if (ioapic < 0)
1116                 return -ENODEV;
1117 
1118         pin = mp_find_ioapic_pin(ioapic, gsi);
1119         idx = find_irq_entry(ioapic, pin, mp_INT);
1120         if ((flags & IOAPIC_MAP_CHECK) && idx < 0)
1121                 return -ENODEV;
1122 
1123         return mp_map_pin_to_irq(gsi, idx, ioapic, pin, flags, info);
1124 }
1125 
1126 void mp_unmap_irq(int irq)
1127 {
1128         struct irq_data *irq_data = irq_get_irq_data(irq);
1129         struct mp_chip_data *data;
1130 
1131         if (!irq_data || !irq_data->domain)
1132                 return;
1133 
1134         data = irq_data->chip_data;
1135         if (!data || data->isa_irq)
1136                 return;
1137 
1138         mutex_lock(&ioapic_mutex);
1139         if (--data->count == 0)
1140                 irq_domain_free_irqs(irq, 1);
1141         mutex_unlock(&ioapic_mutex);
1142 }
1143 
1144 /*
1145  * Find a specific PCI IRQ entry.
1146  * Not an __init, possibly needed by modules
1147  */
1148 int IO_APIC_get_PCI_irq_vector(int bus, int slot, int pin)
1149 {
1150         int irq, i, best_ioapic = -1, best_idx = -1;
1151 
1152         apic_printk(APIC_DEBUG,
1153                     "querying PCI -> IRQ mapping bus:%d, slot:%d, pin:%d.\n",
1154                     bus, slot, pin);
1155         if (test_bit(bus, mp_bus_not_pci)) {
1156                 apic_printk(APIC_VERBOSE,
1157                             "PCI BIOS passed nonexistent PCI bus %d!\n", bus);
1158                 return -1;
1159         }
1160 
1161         for (i = 0; i < mp_irq_entries; i++) {
1162                 int lbus = mp_irqs[i].srcbus;
1163                 int ioapic_idx, found = 0;
1164 
1165                 if (bus != lbus || mp_irqs[i].irqtype != mp_INT ||
1166                     slot != ((mp_irqs[i].srcbusirq >> 2) & 0x1f))
1167                         continue;
1168 
1169                 for_each_ioapic(ioapic_idx)
1170                         if (mpc_ioapic_id(ioapic_idx) == mp_irqs[i].dstapic ||
1171                             mp_irqs[i].dstapic == MP_APIC_ALL) {
1172                                 found = 1;
1173                                 break;
1174                         }
1175                 if (!found)
1176                         continue;
1177 
1178                 /* Skip ISA IRQs */
1179                 irq = pin_2_irq(i, ioapic_idx, mp_irqs[i].dstirq, 0);
1180                 if (irq > 0 && !IO_APIC_IRQ(irq))
1181                         continue;
1182 
1183                 if (pin == (mp_irqs[i].srcbusirq & 3)) {
1184                         best_idx = i;
1185                         best_ioapic = ioapic_idx;
1186                         goto out;
1187                 }
1188 
1189                 /*
1190                  * Use the first all-but-pin matching entry as a
1191                  * best-guess fuzzy result for broken mptables.
1192                  */
1193                 if (best_idx < 0) {
1194                         best_idx = i;
1195                         best_ioapic = ioapic_idx;
1196                 }
1197         }
1198         if (best_idx < 0)
1199                 return -1;
1200 
1201 out:
1202         return pin_2_irq(best_idx, best_ioapic, mp_irqs[best_idx].dstirq,
1203                          IOAPIC_MAP_ALLOC);
1204 }
1205 EXPORT_SYMBOL(IO_APIC_get_PCI_irq_vector);
1206 
1207 static struct irq_chip ioapic_chip, ioapic_ir_chip;
1208 
1209 static void __init setup_IO_APIC_irqs(void)
1210 {
1211         unsigned int ioapic, pin;
1212         int idx;
1213 
1214         apic_printk(APIC_VERBOSE, KERN_DEBUG "init IO_APIC IRQs\n");
1215 
1216         for_each_ioapic_pin(ioapic, pin) {
1217                 idx = find_irq_entry(ioapic, pin, mp_INT);
1218                 if (idx < 0)
1219                         apic_printk(APIC_VERBOSE,
1220                                     KERN_DEBUG " apic %d pin %d not connected\n",
1221                                     mpc_ioapic_id(ioapic), pin);
1222                 else
1223                         pin_2_irq(idx, ioapic, pin,
1224                                   ioapic ? 0 : IOAPIC_MAP_ALLOC);
1225         }
1226 }
1227 
1228 void ioapic_zap_locks(void)
1229 {
1230         raw_spin_lock_init(&ioapic_lock);
1231 }
1232 
1233 static void io_apic_print_entries(unsigned int apic, unsigned int nr_entries)
1234 {
1235         int i;
1236         char buf[256];
1237         struct IO_APIC_route_entry entry;
1238         struct IR_IO_APIC_route_entry *ir_entry = (void *)&entry;
1239 
1240         printk(KERN_DEBUG "IOAPIC %d:\n", apic);
1241         for (i = 0; i <= nr_entries; i++) {
1242                 entry = ioapic_read_entry(apic, i);
1243                 snprintf(buf, sizeof(buf),
1244                          " pin%02x, %s, %s, %s, V(%02X), IRR(%1d), S(%1d)",
1245                          i,
1246                          entry.mask == IOAPIC_MASKED ? "disabled" : "enabled ",
1247                          entry.trigger == IOAPIC_LEVEL ? "level" : "edge ",
1248                          entry.polarity == IOAPIC_POL_LOW ? "low " : "high",
1249                          entry.vector, entry.irr, entry.delivery_status);
1250                 if (ir_entry->format)
1251                         printk(KERN_DEBUG "%s, remapped, I(%04X),  Z(%X)\n",
1252                                buf, (ir_entry->index2 << 15) | ir_entry->index,
1253                                ir_entry->zero);
1254                 else
1255                         printk(KERN_DEBUG "%s, %s, D(%02X), M(%1d)\n",
1256                                buf,
1257                                entry.dest_mode == IOAPIC_DEST_MODE_LOGICAL ?
1258                                "logical " : "physical",
1259                                entry.dest, entry.delivery_mode);
1260         }
1261 }
1262 
1263 static void __init print_IO_APIC(int ioapic_idx)
1264 {
1265         union IO_APIC_reg_00 reg_00;
1266         union IO_APIC_reg_01 reg_01;
1267         union IO_APIC_reg_02 reg_02;
1268         union IO_APIC_reg_03 reg_03;
1269         unsigned long flags;
1270 
1271         raw_spin_lock_irqsave(&ioapic_lock, flags);
1272         reg_00.raw = io_apic_read(ioapic_idx, 0);
1273         reg_01.raw = io_apic_read(ioapic_idx, 1);
1274         if (reg_01.bits.version >= 0x10)
1275                 reg_02.raw = io_apic_read(ioapic_idx, 2);
1276         if (reg_01.bits.version >= 0x20)
1277                 reg_03.raw = io_apic_read(ioapic_idx, 3);
1278         raw_spin_unlock_irqrestore(&ioapic_lock, flags);
1279 
1280         printk(KERN_DEBUG "IO APIC #%d......\n", mpc_ioapic_id(ioapic_idx));
1281         printk(KERN_DEBUG ".... register #00: %08X\n", reg_00.raw);
1282         printk(KERN_DEBUG ".......    : physical APIC id: %02X\n", reg_00.bits.ID);
1283         printk(KERN_DEBUG ".......    : Delivery Type: %X\n", reg_00.bits.delivery_type);
1284         printk(KERN_DEBUG ".......    : LTS          : %X\n", reg_00.bits.LTS);
1285 
1286         printk(KERN_DEBUG ".... register #01: %08X\n", *(int *)&reg_01);
1287         printk(KERN_DEBUG ".......     : max redirection entries: %02X\n",
1288                 reg_01.bits.entries);
1289 
1290         printk(KERN_DEBUG ".......     : PRQ implemented: %X\n", reg_01.bits.PRQ);
1291         printk(KERN_DEBUG ".......     : IO APIC version: %02X\n",
1292                 reg_01.bits.version);
1293 
1294         /*
1295          * Some Intel chipsets with IO APIC VERSION of 0x1? don't have reg_02,
1296          * but the value of reg_02 is read as the previous read register
1297          * value, so ignore it if reg_02 == reg_01.
1298          */
1299         if (reg_01.bits.version >= 0x10 && reg_02.raw != reg_01.raw) {
1300                 printk(KERN_DEBUG ".... register #02: %08X\n", reg_02.raw);
1301                 printk(KERN_DEBUG ".......     : arbitration: %02X\n", reg_02.bits.arbitration);
1302         }
1303 
1304         /*
1305          * Some Intel chipsets with IO APIC VERSION of 0x2? don't have reg_02
1306          * or reg_03, but the value of reg_0[23] is read as the previous read
1307          * register value, so ignore it if reg_03 == reg_0[12].
1308          */
1309         if (reg_01.bits.version >= 0x20 && reg_03.raw != reg_02.raw &&
1310             reg_03.raw != reg_01.raw) {
1311                 printk(KERN_DEBUG ".... register #03: %08X\n", reg_03.raw);
1312                 printk(KERN_DEBUG ".......     : Boot DT    : %X\n", reg_03.bits.boot_DT);
1313         }
1314 
1315         printk(KERN_DEBUG ".... IRQ redirection table:\n");
1316         io_apic_print_entries(ioapic_idx, reg_01.bits.entries);
1317 }
1318 
1319 void __init print_IO_APICs(void)
1320 {
1321         int ioapic_idx;
1322         unsigned int irq;
1323 
1324         printk(KERN_DEBUG "number of MP IRQ sources: %d.\n", mp_irq_entries);
1325         for_each_ioapic(ioapic_idx)
1326                 printk(KERN_DEBUG "number of IO-APIC #%d registers: %d.\n",
1327                        mpc_ioapic_id(ioapic_idx),
1328                        ioapics[ioapic_idx].nr_registers);
1329 
1330         /*
1331          * We are a bit conservative about what we expect.  We have to
1332          * know about every hardware change ASAP.
1333          */
1334         printk(KERN_INFO "testing the IO APIC.......................\n");
1335 
1336         for_each_ioapic(ioapic_idx)
1337                 print_IO_APIC(ioapic_idx);
1338 
1339         printk(KERN_DEBUG "IRQ to pin mappings:\n");
1340         for_each_active_irq(irq) {
1341                 struct irq_pin_list *entry;
1342                 struct irq_chip *chip;
1343                 struct mp_chip_data *data;
1344 
1345                 chip = irq_get_chip(irq);
1346                 if (chip != &ioapic_chip && chip != &ioapic_ir_chip)
1347                         continue;
1348                 data = irq_get_chip_data(irq);
1349                 if (!data)
1350                         continue;
1351                 if (list_empty(&data->irq_2_pin))
1352                         continue;
1353 
1354                 printk(KERN_DEBUG "IRQ%d ", irq);
1355                 for_each_irq_pin(entry, data->irq_2_pin)
1356                         pr_cont("-> %d:%d", entry->apic, entry->pin);
1357                 pr_cont("\n");
1358         }
1359 
1360         printk(KERN_INFO ".................................... done.\n");
1361 }
1362 
1363 /* Where if anywhere is the i8259 connect in external int mode */
1364 static struct { int pin, apic; } ioapic_i8259 = { -1, -1 };
1365 
1366 void __init enable_IO_APIC(void)
1367 {
1368         int i8259_apic, i8259_pin;
1369         int apic, pin;
1370 
1371         if (skip_ioapic_setup)
1372                 nr_ioapics = 0;
1373 
1374         if (!nr_legacy_irqs() || !nr_ioapics)
1375                 return;
1376 
1377         for_each_ioapic_pin(apic, pin) {
1378                 /* See if any of the pins is in ExtINT mode */
1379                 struct IO_APIC_route_entry entry = ioapic_read_entry(apic, pin);
1380 
1381                 /* If the interrupt line is enabled and in ExtInt mode
1382                  * I have found the pin where the i8259 is connected.
1383                  */
1384                 if ((entry.mask == 0) && (entry.delivery_mode == dest_ExtINT)) {
1385                         ioapic_i8259.apic = apic;
1386                         ioapic_i8259.pin  = pin;
1387                         goto found_i8259;
1388                 }
1389         }
1390  found_i8259:
1391         /* Look to see what if the MP table has reported the ExtINT */
1392         /* If we could not find the appropriate pin by looking at the ioapic
1393          * the i8259 probably is not connected the ioapic but give the
1394          * mptable a chance anyway.
1395          */
1396         i8259_pin  = find_isa_irq_pin(0, mp_ExtINT);
1397         i8259_apic = find_isa_irq_apic(0, mp_ExtINT);
1398         /* Trust the MP table if nothing is setup in the hardware */
1399         if ((ioapic_i8259.pin == -1) && (i8259_pin >= 0)) {
1400                 printk(KERN_WARNING "ExtINT not setup in hardware but reported by MP table\n");
1401                 ioapic_i8259.pin  = i8259_pin;
1402                 ioapic_i8259.apic = i8259_apic;
1403         }
1404         /* Complain if the MP table and the hardware disagree */
1405         if (((ioapic_i8259.apic != i8259_apic) || (ioapic_i8259.pin != i8259_pin)) &&
1406                 (i8259_pin >= 0) && (ioapic_i8259.pin >= 0))
1407         {
1408                 printk(KERN_WARNING "ExtINT in hardware and MP table differ\n");
1409         }
1410 
1411         /*
1412          * Do not trust the IO-APIC being empty at bootup
1413          */
1414         clear_IO_APIC();
1415 }
1416 
1417 void native_restore_boot_irq_mode(void)
1418 {
1419         /*
1420          * If the i8259 is routed through an IOAPIC
1421          * Put that IOAPIC in virtual wire mode
1422          * so legacy interrupts can be delivered.
1423          */
1424         if (ioapic_i8259.pin != -1) {
1425                 struct IO_APIC_route_entry entry;
1426 
1427                 memset(&entry, 0, sizeof(entry));
1428                 entry.mask              = IOAPIC_UNMASKED;
1429                 entry.trigger           = IOAPIC_EDGE;
1430                 entry.polarity          = IOAPIC_POL_HIGH;
1431                 entry.dest_mode         = IOAPIC_DEST_MODE_PHYSICAL;
1432                 entry.delivery_mode     = dest_ExtINT;
1433                 entry.dest              = read_apic_id();
1434 
1435                 /*
1436                  * Add it to the IO-APIC irq-routing table:
1437                  */
1438                 ioapic_write_entry(ioapic_i8259.apic, ioapic_i8259.pin, entry);
1439         }
1440 
1441         if (boot_cpu_has(X86_FEATURE_APIC) || apic_from_smp_config())
1442                 disconnect_bsp_APIC(ioapic_i8259.pin != -1);
1443 }
1444 
1445 void restore_boot_irq_mode(void)
1446 {
1447         if (!nr_legacy_irqs())
1448                 return;
1449 
1450         x86_apic_ops.restore();
1451 }
1452 
1453 #ifdef CONFIG_X86_32
1454 /*
1455  * function to set the IO-APIC physical IDs based on the
1456  * values stored in the MPC table.
1457  *
1458  * by Matt Domsch <Matt_Domsch@dell.com>  Tue Dec 21 12:25:05 CST 1999
1459  */
1460 void __init setup_ioapic_ids_from_mpc_nocheck(void)
1461 {
1462         union IO_APIC_reg_00 reg_00;
1463         physid_mask_t phys_id_present_map;
1464         int ioapic_idx;
1465         int i;
1466         unsigned char old_id;
1467         unsigned long flags;
1468 
1469         /*
1470          * This is broken; anything with a real cpu count has to
1471          * circumvent this idiocy regardless.
1472          */
1473         apic->ioapic_phys_id_map(&phys_cpu_present_map, &phys_id_present_map);
1474 
1475         /*
1476          * Set the IOAPIC ID to the value stored in the MPC table.
1477          */
1478         for_each_ioapic(ioapic_idx) {
1479                 /* Read the register 0 value */
1480                 raw_spin_lock_irqsave(&ioapic_lock, flags);
1481                 reg_00.raw = io_apic_read(ioapic_idx, 0);
1482                 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
1483 
1484                 old_id = mpc_ioapic_id(ioapic_idx);
1485 
1486                 if (mpc_ioapic_id(ioapic_idx) >= get_physical_broadcast()) {
1487                         printk(KERN_ERR "BIOS bug, IO-APIC#%d ID is %d in the MPC table!...\n",
1488                                 ioapic_idx, mpc_ioapic_id(ioapic_idx));
1489                         printk(KERN_ERR "... fixing up to %d. (tell your hw vendor)\n",
1490                                 reg_00.bits.ID);
1491                         ioapics[ioapic_idx].mp_config.apicid = reg_00.bits.ID;
1492                 }
1493 
1494                 /*
1495                  * Sanity check, is the ID really free? Every APIC in a
1496                  * system must have a unique ID or we get lots of nice
1497                  * 'stuck on smp_invalidate_needed IPI wait' messages.
1498                  */
1499                 if (apic->check_apicid_used(&phys_id_present_map,
1500                                             mpc_ioapic_id(ioapic_idx))) {
1501                         printk(KERN_ERR "BIOS bug, IO-APIC#%d ID %d is already used!...\n",
1502                                 ioapic_idx, mpc_ioapic_id(ioapic_idx));
1503                         for (i = 0; i < get_physical_broadcast(); i++)
1504                                 if (!physid_isset(i, phys_id_present_map))
1505                                         break;
1506                         if (i >= get_physical_broadcast())
1507                                 panic("Max APIC ID exceeded!\n");
1508                         printk(KERN_ERR "... fixing up to %d. (tell your hw vendor)\n",
1509                                 i);
1510                         physid_set(i, phys_id_present_map);
1511                         ioapics[ioapic_idx].mp_config.apicid = i;
1512                 } else {
1513                         physid_mask_t tmp;
1514                         apic->apicid_to_cpu_present(mpc_ioapic_id(ioapic_idx),
1515                                                     &tmp);
1516                         apic_printk(APIC_VERBOSE, "Setting %d in the "
1517                                         "phys_id_present_map\n",
1518                                         mpc_ioapic_id(ioapic_idx));
1519                         physids_or(phys_id_present_map, phys_id_present_map, tmp);
1520                 }
1521 
1522                 /*
1523                  * We need to adjust the IRQ routing table
1524                  * if the ID changed.
1525                  */
1526                 if (old_id != mpc_ioapic_id(ioapic_idx))
1527                         for (i = 0; i < mp_irq_entries; i++)
1528                                 if (mp_irqs[i].dstapic == old_id)
1529                                         mp_irqs[i].dstapic
1530                                                 = mpc_ioapic_id(ioapic_idx);
1531 
1532                 /*
1533                  * Update the ID register according to the right value
1534                  * from the MPC table if they are different.
1535                  */
1536                 if (mpc_ioapic_id(ioapic_idx) == reg_00.bits.ID)
1537                         continue;
1538 
1539                 apic_printk(APIC_VERBOSE, KERN_INFO
1540                         "...changing IO-APIC physical APIC ID to %d ...",
1541                         mpc_ioapic_id(ioapic_idx));
1542 
1543                 reg_00.bits.ID = mpc_ioapic_id(ioapic_idx);
1544                 raw_spin_lock_irqsave(&ioapic_lock, flags);
1545                 io_apic_write(ioapic_idx, 0, reg_00.raw);
1546                 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
1547 
1548                 /*
1549                  * Sanity check
1550                  */
1551                 raw_spin_lock_irqsave(&ioapic_lock, flags);
1552                 reg_00.raw = io_apic_read(ioapic_idx, 0);
1553                 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
1554                 if (reg_00.bits.ID != mpc_ioapic_id(ioapic_idx))
1555                         pr_cont("could not set ID!\n");
1556                 else
1557                         apic_printk(APIC_VERBOSE, " ok.\n");
1558         }
1559 }
1560 
1561 void __init setup_ioapic_ids_from_mpc(void)
1562 {
1563 
1564         if (acpi_ioapic)
1565                 return;
1566         /*
1567          * Don't check I/O APIC IDs for xAPIC systems.  They have
1568          * no meaning without the serial APIC bus.
1569          */
1570         if (!(boot_cpu_data.x86_vendor == X86_VENDOR_INTEL)
1571                 || APIC_XAPIC(boot_cpu_apic_version))
1572                 return;
1573         setup_ioapic_ids_from_mpc_nocheck();
1574 }
1575 #endif
1576 
1577 int no_timer_check __initdata;
1578 
1579 static int __init notimercheck(char *s)
1580 {
1581         no_timer_check = 1;
1582         return 1;
1583 }
1584 __setup("no_timer_check", notimercheck);
1585 
1586 static void __init delay_with_tsc(void)
1587 {
1588         unsigned long long start, now;
1589         unsigned long end = jiffies + 4;
1590 
1591         start = rdtsc();
1592 
1593         /*
1594          * We don't know the TSC frequency yet, but waiting for
1595          * 40000000000/HZ TSC cycles is safe:
1596          * 4 GHz == 10 jiffies
1597          * 1 GHz == 40 jiffies
1598          */
1599         do {
1600                 rep_nop();
1601                 now = rdtsc();
1602         } while ((now - start) < 40000000000ULL / HZ &&
1603                 time_before_eq(jiffies, end));
1604 }
1605 
1606 static void __init delay_without_tsc(void)
1607 {
1608         unsigned long end = jiffies + 4;
1609         int band = 1;
1610 
1611         /*
1612          * We don't know any frequency yet, but waiting for
1613          * 40940000000/HZ cycles is safe:
1614          * 4 GHz == 10 jiffies
1615          * 1 GHz == 40 jiffies
1616          * 1 << 1 + 1 << 2 +...+ 1 << 11 = 4094
1617          */
1618         do {
1619                 __delay(((1U << band++) * 10000000UL) / HZ);
1620         } while (band < 12 && time_before_eq(jiffies, end));
1621 }
1622 
1623 /*
1624  * There is a nasty bug in some older SMP boards, their mptable lies
1625  * about the timer IRQ. We do the following to work around the situation:
1626  *
1627  *      - timer IRQ defaults to IO-APIC IRQ
1628  *      - if this function detects that timer IRQs are defunct, then we fall
1629  *        back to ISA timer IRQs
1630  */
1631 static int __init timer_irq_works(void)
1632 {
1633         unsigned long t1 = jiffies;
1634         unsigned long flags;
1635 
1636         if (no_timer_check)
1637                 return 1;
1638 
1639         local_save_flags(flags);
1640         local_irq_enable();
1641 
1642         if (boot_cpu_has(X86_FEATURE_TSC))
1643                 delay_with_tsc();
1644         else
1645                 delay_without_tsc();
1646 
1647         local_irq_restore(flags);
1648 
1649         /*
1650          * Expect a few ticks at least, to be sure some possible
1651          * glue logic does not lock up after one or two first
1652          * ticks in a non-ExtINT mode.  Also the local APIC
1653          * might have cached one ExtINT interrupt.  Finally, at
1654          * least one tick may be lost due to delays.
1655          */
1656 
1657         /* jiffies wrap? */
1658         if (time_after(jiffies, t1 + 4))
1659                 return 1;
1660         return 0;
1661 }
1662 
1663 /*
1664  * In the SMP+IOAPIC case it might happen that there are an unspecified
1665  * number of pending IRQ events unhandled. These cases are very rare,
1666  * so we 'resend' these IRQs via IPIs, to the same CPU. It's much
1667  * better to do it this way as thus we do not have to be aware of
1668  * 'pending' interrupts in the IRQ path, except at this point.
1669  */
1670 /*
1671  * Edge triggered needs to resend any interrupt
1672  * that was delayed but this is now handled in the device
1673  * independent code.
1674  */
1675 
1676 /*
1677  * Starting up a edge-triggered IO-APIC interrupt is
1678  * nasty - we need to make sure that we get the edge.
1679  * If it is already asserted for some reason, we need
1680  * return 1 to indicate that is was pending.
1681  *
1682  * This is not complete - we should be able to fake
1683  * an edge even if it isn't on the 8259A...
1684  */
1685 static unsigned int startup_ioapic_irq(struct irq_data *data)
1686 {
1687         int was_pending = 0, irq = data->irq;
1688         unsigned long flags;
1689 
1690         raw_spin_lock_irqsave(&ioapic_lock, flags);
1691         if (irq < nr_legacy_irqs()) {
1692                 legacy_pic->mask(irq);
1693                 if (legacy_pic->irq_pending(irq))
1694                         was_pending = 1;
1695         }
1696         __unmask_ioapic(data->chip_data);
1697         raw_spin_unlock_irqrestore(&ioapic_lock, flags);
1698 
1699         return was_pending;
1700 }
1701 
1702 atomic_t irq_mis_count;
1703 
1704 #ifdef CONFIG_GENERIC_PENDING_IRQ
1705 static bool io_apic_level_ack_pending(struct mp_chip_data *data)
1706 {
1707         struct irq_pin_list *entry;
1708         unsigned long flags;
1709 
1710         raw_spin_lock_irqsave(&ioapic_lock, flags);
1711         for_each_irq_pin(entry, data->irq_2_pin) {
1712                 unsigned int reg;
1713                 int pin;
1714 
1715                 pin = entry->pin;
1716                 reg = io_apic_read(entry->apic, 0x10 + pin*2);
1717                 /* Is the remote IRR bit set? */
1718                 if (reg & IO_APIC_REDIR_REMOTE_IRR) {
1719                         raw_spin_unlock_irqrestore(&ioapic_lock, flags);
1720                         return true;
1721                 }
1722         }
1723         raw_spin_unlock_irqrestore(&ioapic_lock, flags);
1724 
1725         return false;
1726 }
1727 
1728 static inline bool ioapic_irqd_mask(struct irq_data *data)
1729 {
1730         /* If we are moving the IRQ we need to mask it */
1731         if (unlikely(irqd_is_setaffinity_pending(data))) {
1732                 if (!irqd_irq_masked(data))
1733                         mask_ioapic_irq(data);
1734                 return true;
1735         }
1736         return false;
1737 }
1738 
1739 static inline void ioapic_irqd_unmask(struct irq_data *data, bool masked)
1740 {
1741         if (unlikely(masked)) {
1742                 /* Only migrate the irq if the ack has been received.
1743                  *
1744                  * On rare occasions the broadcast level triggered ack gets
1745                  * delayed going to ioapics, and if we reprogram the
1746                  * vector while Remote IRR is still set the irq will never
1747                  * fire again.
1748                  *
1749                  * To prevent this scenario we read the Remote IRR bit
1750                  * of the ioapic.  This has two effects.
1751                  * - On any sane system the read of the ioapic will
1752                  *   flush writes (and acks) going to the ioapic from
1753                  *   this cpu.
1754                  * - We get to see if the ACK has actually been delivered.
1755                  *
1756                  * Based on failed experiments of reprogramming the
1757                  * ioapic entry from outside of irq context starting
1758                  * with masking the ioapic entry and then polling until
1759                  * Remote IRR was clear before reprogramming the
1760                  * ioapic I don't trust the Remote IRR bit to be
1761                  * completey accurate.
1762                  *
1763                  * However there appears to be no other way to plug
1764                  * this race, so if the Remote IRR bit is not
1765                  * accurate and is causing problems then it is a hardware bug
1766                  * and you can go talk to the chipset vendor about it.
1767                  */
1768                 if (!io_apic_level_ack_pending(data->chip_data))
1769                         irq_move_masked_irq(data);
1770                 /* If the IRQ is masked in the core, leave it: */
1771                 if (!irqd_irq_masked(data))
1772                         unmask_ioapic_irq(data);
1773         }
1774 }
1775 #else
1776 static inline bool ioapic_irqd_mask(struct irq_data *data)
1777 {
1778         return false;
1779 }
1780 static inline void ioapic_irqd_unmask(struct irq_data *data, bool masked)
1781 {
1782 }
1783 #endif
1784 
1785 static void ioapic_ack_level(struct irq_data *irq_data)
1786 {
1787         struct irq_cfg *cfg = irqd_cfg(irq_data);
1788         unsigned long v;
1789         bool masked;
1790         int i;
1791 
1792         irq_complete_move(cfg);
1793         masked = ioapic_irqd_mask(irq_data);
1794 
1795         /*
1796          * It appears there is an erratum which affects at least version 0x11
1797          * of I/O APIC (that's the 82093AA and cores integrated into various
1798          * chipsets).  Under certain conditions a level-triggered interrupt is
1799          * erroneously delivered as edge-triggered one but the respective IRR
1800          * bit gets set nevertheless.  As a result the I/O unit expects an EOI
1801          * message but it will never arrive and further interrupts are blocked
1802          * from the source.  The exact reason is so far unknown, but the
1803          * phenomenon was observed when two consecutive interrupt requests
1804          * from a given source get delivered to the same CPU and the source is
1805          * temporarily disabled in between.
1806          *
1807          * A workaround is to simulate an EOI message manually.  We achieve it
1808          * by setting the trigger mode to edge and then to level when the edge
1809          * trigger mode gets detected in the TMR of a local APIC for a
1810          * level-triggered interrupt.  We mask the source for the time of the
1811          * operation to prevent an edge-triggered interrupt escaping meanwhile.
1812          * The idea is from Manfred Spraul.  --macro
1813          *
1814          * Also in the case when cpu goes offline, fixup_irqs() will forward
1815          * any unhandled interrupt on the offlined cpu to the new cpu
1816          * destination that is handling the corresponding interrupt. This
1817          * interrupt forwarding is done via IPI's. Hence, in this case also
1818          * level-triggered io-apic interrupt will be seen as an edge
1819          * interrupt in the IRR. And we can't rely on the cpu's EOI
1820          * to be broadcasted to the IO-APIC's which will clear the remoteIRR
1821          * corresponding to the level-triggered interrupt. Hence on IO-APIC's
1822          * supporting EOI register, we do an explicit EOI to clear the
1823          * remote IRR and on IO-APIC's which don't have an EOI register,
1824          * we use the above logic (mask+edge followed by unmask+level) from
1825          * Manfred Spraul to clear the remote IRR.
1826          */
1827         i = cfg->vector;
1828         v = apic_read(APIC_TMR + ((i & ~0x1f) >> 1));
1829 
1830         /*
1831          * We must acknowledge the irq before we move it or the acknowledge will
1832          * not propagate properly.
1833          */
1834         ack_APIC_irq();
1835 
1836         /*
1837          * Tail end of clearing remote IRR bit (either by delivering the EOI
1838          * message via io-apic EOI register write or simulating it using
1839          * mask+edge followed by unnask+level logic) manually when the
1840          * level triggered interrupt is seen as the edge triggered interrupt
1841          * at the cpu.
1842          */
1843         if (!(v & (1 << (i & 0x1f)))) {
1844                 atomic_inc(&irq_mis_count);
1845                 eoi_ioapic_pin(cfg->vector, irq_data->chip_data);
1846         }
1847 
1848         ioapic_irqd_unmask(irq_data, masked);
1849 }
1850 
1851 static void ioapic_ir_ack_level(struct irq_data *irq_data)
1852 {
1853         struct mp_chip_data *data = irq_data->chip_data;
1854 
1855         /*
1856          * Intr-remapping uses pin number as the virtual vector
1857          * in the RTE. Actual vector is programmed in
1858          * intr-remapping table entry. Hence for the io-apic
1859          * EOI we use the pin number.
1860          */
1861         apic_ack_irq(irq_data);
1862         eoi_ioapic_pin(data->entry.vector, data);
1863 }
1864 
1865 static void ioapic_configure_entry(struct irq_data *irqd)
1866 {
1867         struct mp_chip_data *mpd = irqd->chip_data;
1868         struct irq_cfg *cfg = irqd_cfg(irqd);
1869         struct irq_pin_list *entry;
1870 
1871         /*
1872          * Only update when the parent is the vector domain, don't touch it
1873          * if the parent is the remapping domain. Check the installed
1874          * ioapic chip to verify that.
1875          */
1876         if (irqd->chip == &ioapic_chip) {
1877                 mpd->entry.dest = cfg->dest_apicid;
1878                 mpd->entry.vector = cfg->vector;
1879         }
1880         for_each_irq_pin(entry, mpd->irq_2_pin)
1881                 __ioapic_write_entry(entry->apic, entry->pin, mpd->entry);
1882 }
1883 
1884 static int ioapic_set_affinity(struct irq_data *irq_data,
1885                                const struct cpumask *mask, bool force)
1886 {
1887         struct irq_data *parent = irq_data->parent_data;
1888         unsigned long flags;
1889         int ret;
1890 
1891         ret = parent->chip->irq_set_affinity(parent, mask, force);
1892         raw_spin_lock_irqsave(&ioapic_lock, flags);
1893         if (ret >= 0 && ret != IRQ_SET_MASK_OK_DONE)
1894                 ioapic_configure_entry(irq_data);
1895         raw_spin_unlock_irqrestore(&ioapic_lock, flags);
1896 
1897         return ret;
1898 }
1899 
1900 /*
1901  * Interrupt shutdown masks the ioapic pin, but the interrupt might already
1902  * be in flight, but not yet serviced by the target CPU. That means
1903  * __synchronize_hardirq() would return and claim that everything is calmed
1904  * down. So free_irq() would proceed and deactivate the interrupt and free
1905  * resources.
1906  *
1907  * Once the target CPU comes around to service it it will find a cleared
1908  * vector and complain. While the spurious interrupt is harmless, the full
1909  * release of resources might prevent the interrupt from being acknowledged
1910  * which keeps the hardware in a weird state.
1911  *
1912  * Verify that the corresponding Remote-IRR bits are clear.
1913  */
1914 static int ioapic_irq_get_chip_state(struct irq_data *irqd,
1915                                    enum irqchip_irq_state which,
1916                                    bool *state)
1917 {
1918         struct mp_chip_data *mcd = irqd->chip_data;
1919         struct IO_APIC_route_entry rentry;
1920         struct irq_pin_list *p;
1921 
1922         if (which != IRQCHIP_STATE_ACTIVE)
1923                 return -EINVAL;
1924 
1925         *state = false;
1926         raw_spin_lock(&ioapic_lock);
1927         for_each_irq_pin(p, mcd->irq_2_pin) {
1928                 rentry = __ioapic_read_entry(p->apic, p->pin);
1929                 /*
1930                  * The remote IRR is only valid in level trigger mode. It's
1931                  * meaning is undefined for edge triggered interrupts and
1932                  * irrelevant because the IO-APIC treats them as fire and
1933                  * forget.
1934                  */
1935                 if (rentry.irr && rentry.trigger) {
1936                         *state = true;
1937                         break;
1938                 }
1939         }
1940         raw_spin_unlock(&ioapic_lock);
1941         return 0;
1942 }
1943 
1944 static struct irq_chip ioapic_chip __read_mostly = {
1945         .name                   = "IO-APIC",
1946         .irq_startup            = startup_ioapic_irq,
1947         .irq_mask               = mask_ioapic_irq,
1948         .irq_unmask             = unmask_ioapic_irq,
1949         .irq_ack                = irq_chip_ack_parent,
1950         .irq_eoi                = ioapic_ack_level,
1951         .irq_set_affinity       = ioapic_set_affinity,
1952         .irq_retrigger          = irq_chip_retrigger_hierarchy,
1953         .irq_get_irqchip_state  = ioapic_irq_get_chip_state,
1954         .flags                  = IRQCHIP_SKIP_SET_WAKE,
1955 };
1956 
1957 static struct irq_chip ioapic_ir_chip __read_mostly = {
1958         .name                   = "IR-IO-APIC",
1959         .irq_startup            = startup_ioapic_irq,
1960         .irq_mask               = mask_ioapic_irq,
1961         .irq_unmask             = unmask_ioapic_irq,
1962         .irq_ack                = irq_chip_ack_parent,
1963         .irq_eoi                = ioapic_ir_ack_level,
1964         .irq_set_affinity       = ioapic_set_affinity,
1965         .irq_retrigger          = irq_chip_retrigger_hierarchy,
1966         .irq_get_irqchip_state  = ioapic_irq_get_chip_state,
1967         .flags                  = IRQCHIP_SKIP_SET_WAKE,
1968 };
1969 
1970 static inline void init_IO_APIC_traps(void)
1971 {
1972         struct irq_cfg *cfg;
1973         unsigned int irq;
1974 
1975         for_each_active_irq(irq) {
1976                 cfg = irq_cfg(irq);
1977                 if (IO_APIC_IRQ(irq) && cfg && !cfg->vector) {
1978                         /*
1979                          * Hmm.. We don't have an entry for this,
1980                          * so default to an old-fashioned 8259
1981                          * interrupt if we can..
1982                          */
1983                         if (irq < nr_legacy_irqs())
1984                                 legacy_pic->make_irq(irq);
1985                         else
1986                                 /* Strange. Oh, well.. */
1987                                 irq_set_chip(irq, &no_irq_chip);
1988                 }
1989         }
1990 }
1991 
1992 /*
1993  * The local APIC irq-chip implementation:
1994  */
1995 
1996 static void mask_lapic_irq(struct irq_data *data)
1997 {
1998         unsigned long v;
1999 
2000         v = apic_read(APIC_LVT0);
2001         apic_write(APIC_LVT0, v | APIC_LVT_MASKED);
2002 }
2003 
2004 static void unmask_lapic_irq(struct irq_data *data)
2005 {
2006         unsigned long v;
2007 
2008         v = apic_read(APIC_LVT0);
2009         apic_write(APIC_LVT0, v & ~APIC_LVT_MASKED);
2010 }
2011 
2012 static void ack_lapic_irq(struct irq_data *data)
2013 {
2014         ack_APIC_irq();
2015 }
2016 
2017 static struct irq_chip lapic_chip __read_mostly = {
2018         .name           = "local-APIC",
2019         .irq_mask       = mask_lapic_irq,
2020         .irq_unmask     = unmask_lapic_irq,
2021         .irq_ack        = ack_lapic_irq,
2022 };
2023 
2024 static void lapic_register_intr(int irq)
2025 {
2026         irq_clear_status_flags(irq, IRQ_LEVEL);
2027         irq_set_chip_and_handler_name(irq, &lapic_chip, handle_edge_irq,
2028                                       "edge");
2029 }
2030 
2031 /*
2032  * This looks a bit hackish but it's about the only one way of sending
2033  * a few INTA cycles to 8259As and any associated glue logic.  ICR does
2034  * not support the ExtINT mode, unfortunately.  We need to send these
2035  * cycles as some i82489DX-based boards have glue logic that keeps the
2036  * 8259A interrupt line asserted until INTA.  --macro
2037  */
2038 static inline void __init unlock_ExtINT_logic(void)
2039 {
2040         int apic, pin, i;
2041         struct IO_APIC_route_entry entry0, entry1;
2042         unsigned char save_control, save_freq_select;
2043 
2044         pin  = find_isa_irq_pin(8, mp_INT);
2045         if (pin == -1) {
2046                 WARN_ON_ONCE(1);
2047                 return;
2048         }
2049         apic = find_isa_irq_apic(8, mp_INT);
2050         if (apic == -1) {
2051                 WARN_ON_ONCE(1);
2052                 return;
2053         }
2054 
2055         entry0 = ioapic_read_entry(apic, pin);
2056         clear_IO_APIC_pin(apic, pin);
2057 
2058         memset(&entry1, 0, sizeof(entry1));
2059 
2060         entry1.dest_mode = IOAPIC_DEST_MODE_PHYSICAL;
2061         entry1.mask = IOAPIC_UNMASKED;
2062         entry1.dest = hard_smp_processor_id();
2063         entry1.delivery_mode = dest_ExtINT;
2064         entry1.polarity = entry0.polarity;
2065         entry1.trigger = IOAPIC_EDGE;
2066         entry1.vector = 0;
2067 
2068         ioapic_write_entry(apic, pin, entry1);
2069 
2070         save_control = CMOS_READ(RTC_CONTROL);
2071         save_freq_select = CMOS_READ(RTC_FREQ_SELECT);
2072         CMOS_WRITE((save_freq_select & ~RTC_RATE_SELECT) | 0x6,
2073                    RTC_FREQ_SELECT);
2074         CMOS_WRITE(save_control | RTC_PIE, RTC_CONTROL);
2075 
2076         i = 100;
2077         while (i-- > 0) {
2078                 mdelay(10);
2079                 if ((CMOS_READ(RTC_INTR_FLAGS) & RTC_PF) == RTC_PF)
2080                         i -= 10;
2081         }
2082 
2083         CMOS_WRITE(save_control, RTC_CONTROL);
2084         CMOS_WRITE(save_freq_select, RTC_FREQ_SELECT);
2085         clear_IO_APIC_pin(apic, pin);
2086 
2087         ioapic_write_entry(apic, pin, entry0);
2088 }
2089 
2090 static int disable_timer_pin_1 __initdata;
2091 /* Actually the next is obsolete, but keep it for paranoid reasons -AK */
2092 static int __init disable_timer_pin_setup(char *arg)
2093 {
2094         disable_timer_pin_1 = 1;
2095         return 0;
2096 }
2097 early_param("disable_timer_pin_1", disable_timer_pin_setup);
2098 
2099 static int mp_alloc_timer_irq(int ioapic, int pin)
2100 {
2101         int irq = -1;
2102         struct irq_domain *domain = mp_ioapic_irqdomain(ioapic);
2103 
2104         if (domain) {
2105                 struct irq_alloc_info info;
2106 
2107                 ioapic_set_alloc_attr(&info, NUMA_NO_NODE, 0, 0);
2108                 info.ioapic_id = mpc_ioapic_id(ioapic);
2109                 info.ioapic_pin = pin;
2110                 mutex_lock(&ioapic_mutex);
2111                 irq = alloc_isa_irq_from_domain(domain, 0, ioapic, pin, &info);
2112                 mutex_unlock(&ioapic_mutex);
2113         }
2114 
2115         return irq;
2116 }
2117 
2118 /*
2119  * This code may look a bit paranoid, but it's supposed to cooperate with
2120  * a wide range of boards and BIOS bugs.  Fortunately only the timer IRQ
2121  * is so screwy.  Thanks to Brian Perkins for testing/hacking this beast
2122  * fanatically on his truly buggy board.
2123  *
2124  * FIXME: really need to revamp this for all platforms.
2125  */
2126 static inline void __init check_timer(void)
2127 {
2128         struct irq_data *irq_data = irq_get_irq_data(0);
2129         struct mp_chip_data *data = irq_data->chip_data;
2130         struct irq_cfg *cfg = irqd_cfg(irq_data);
2131         int node = cpu_to_node(0);
2132         int apic1, pin1, apic2, pin2;
2133         unsigned long flags;
2134         int no_pin1 = 0;
2135 
2136         if (!global_clock_event)
2137                 return;
2138 
2139         local_irq_save(flags);
2140 
2141         /*
2142          * get/set the timer IRQ vector:
2143          */
2144         legacy_pic->mask(0);
2145 
2146         /*
2147          * As IRQ0 is to be enabled in the 8259A, the virtual
2148          * wire has to be disabled in the local APIC.  Also
2149          * timer interrupts need to be acknowledged manually in
2150          * the 8259A for the i82489DX when using the NMI
2151          * watchdog as that APIC treats NMIs as level-triggered.
2152          * The AEOI mode will finish them in the 8259A
2153          * automatically.
2154          */
2155         apic_write(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_EXTINT);
2156         legacy_pic->init(1);
2157 
2158         pin1  = find_isa_irq_pin(0, mp_INT);
2159         apic1 = find_isa_irq_apic(0, mp_INT);
2160         pin2  = ioapic_i8259.pin;
2161         apic2 = ioapic_i8259.apic;
2162 
2163         apic_printk(APIC_QUIET, KERN_INFO "..TIMER: vector=0x%02X "
2164                     "apic1=%d pin1=%d apic2=%d pin2=%d\n",
2165                     cfg->vector, apic1, pin1, apic2, pin2);
2166 
2167         /*
2168          * Some BIOS writers are clueless and report the ExtINTA
2169          * I/O APIC input from the cascaded 8259A as the timer
2170          * interrupt input.  So just in case, if only one pin
2171          * was found above, try it both directly and through the
2172          * 8259A.
2173          */
2174         if (pin1 == -1) {
2175                 panic_if_irq_remap("BIOS bug: timer not connected to IO-APIC");
2176                 pin1 = pin2;
2177                 apic1 = apic2;
2178                 no_pin1 = 1;
2179         } else if (pin2 == -1) {
2180                 pin2 = pin1;
2181                 apic2 = apic1;
2182         }
2183 
2184         if (pin1 != -1) {
2185                 /* Ok, does IRQ0 through the IOAPIC work? */
2186                 if (no_pin1) {
2187                         mp_alloc_timer_irq(apic1, pin1);
2188                 } else {
2189                         /*
2190                          * for edge trigger, it's already unmasked,
2191                          * so only need to unmask if it is level-trigger
2192                          * do we really have level trigger timer?
2193                          */
2194                         int idx;
2195                         idx = find_irq_entry(apic1, pin1, mp_INT);
2196                         if (idx != -1 && irq_trigger(idx))
2197                                 unmask_ioapic_irq(irq_get_irq_data(0));
2198                 }
2199                 irq_domain_deactivate_irq(irq_data);
2200                 irq_domain_activate_irq(irq_data, false);
2201                 if (timer_irq_works()) {
2202                         if (disable_timer_pin_1 > 0)
2203                                 clear_IO_APIC_pin(0, pin1);
2204                         goto out;
2205                 }
2206                 panic_if_irq_remap("timer doesn't work through Interrupt-remapped IO-APIC");
2207                 local_irq_disable();
2208                 clear_IO_APIC_pin(apic1, pin1);
2209                 if (!no_pin1)
2210                         apic_printk(APIC_QUIET, KERN_ERR "..MP-BIOS bug: "
2211                                     "8254 timer not connected to IO-APIC\n");
2212 
2213                 apic_printk(APIC_QUIET, KERN_INFO "...trying to set up timer "
2214                             "(IRQ0) through the 8259A ...\n");
2215                 apic_printk(APIC_QUIET, KERN_INFO
2216                             "..... (found apic %d pin %d) ...\n", apic2, pin2);
2217                 /*
2218                  * legacy devices should be connected to IO APIC #0
2219                  */
2220                 replace_pin_at_irq_node(data, node, apic1, pin1, apic2, pin2);
2221                 irq_domain_deactivate_irq(irq_data);
2222                 irq_domain_activate_irq(irq_data, false);
2223                 legacy_pic->unmask(0);
2224                 if (timer_irq_works()) {
2225                         apic_printk(APIC_QUIET, KERN_INFO "....... works.\n");
2226                         goto out;
2227                 }
2228                 /*
2229                  * Cleanup, just in case ...
2230                  */
2231                 local_irq_disable();
2232                 legacy_pic->mask(0);
2233                 clear_IO_APIC_pin(apic2, pin2);
2234                 apic_printk(APIC_QUIET, KERN_INFO "....... failed.\n");
2235         }
2236 
2237         apic_printk(APIC_QUIET, KERN_INFO
2238                     "...trying to set up timer as Virtual Wire IRQ...\n");
2239 
2240         lapic_register_intr(0);
2241         apic_write(APIC_LVT0, APIC_DM_FIXED | cfg->vector);     /* Fixed mode */
2242         legacy_pic->unmask(0);
2243 
2244         if (timer_irq_works()) {
2245                 apic_printk(APIC_QUIET, KERN_INFO "..... works.\n");
2246                 goto out;
2247         }
2248         local_irq_disable();
2249         legacy_pic->mask(0);
2250         apic_write(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_FIXED | cfg->vector);
2251         apic_printk(APIC_QUIET, KERN_INFO "..... failed.\n");
2252 
2253         apic_printk(APIC_QUIET, KERN_INFO
2254                     "...trying to set up timer as ExtINT IRQ...\n");
2255 
2256         legacy_pic->init(0);
2257         legacy_pic->make_irq(0);
2258         apic_write(APIC_LVT0, APIC_DM_EXTINT);
2259 
2260         unlock_ExtINT_logic();
2261 
2262         if (timer_irq_works()) {
2263                 apic_printk(APIC_QUIET, KERN_INFO "..... works.\n");
2264                 goto out;
2265         }
2266         local_irq_disable();
2267         apic_printk(APIC_QUIET, KERN_INFO "..... failed :(.\n");
2268         if (apic_is_x2apic_enabled())
2269                 apic_printk(APIC_QUIET, KERN_INFO
2270                             "Perhaps problem with the pre-enabled x2apic mode\n"
2271                             "Try booting with x2apic and interrupt-remapping disabled in the bios.\n");
2272         panic("IO-APIC + timer doesn't work!  Boot with apic=debug and send a "
2273                 "report.  Then try booting with the 'noapic' option.\n");
2274 out:
2275         local_irq_restore(flags);
2276 }
2277 
2278 /*
2279  * Traditionally ISA IRQ2 is the cascade IRQ, and is not available
2280  * to devices.  However there may be an I/O APIC pin available for
2281  * this interrupt regardless.  The pin may be left unconnected, but
2282  * typically it will be reused as an ExtINT cascade interrupt for
2283  * the master 8259A.  In the MPS case such a pin will normally be
2284  * reported as an ExtINT interrupt in the MP table.  With ACPI
2285  * there is no provision for ExtINT interrupts, and in the absence
2286  * of an override it would be treated as an ordinary ISA I/O APIC
2287  * interrupt, that is edge-triggered and unmasked by default.  We
2288  * used to do this, but it caused problems on some systems because
2289  * of the NMI watchdog and sometimes IRQ0 of the 8254 timer using
2290  * the same ExtINT cascade interrupt to drive the local APIC of the
2291  * bootstrap processor.  Therefore we refrain from routing IRQ2 to
2292  * the I/O APIC in all cases now.  No actual device should request
2293  * it anyway.  --macro
2294  */
2295 #define PIC_IRQS        (1UL << PIC_CASCADE_IR)
2296 
2297 static int mp_irqdomain_create(int ioapic)
2298 {
2299         struct irq_alloc_info info;
2300         struct irq_domain *parent;
2301         int hwirqs = mp_ioapic_pin_count(ioapic);
2302         struct ioapic *ip = &ioapics[ioapic];
2303         struct ioapic_domain_cfg *cfg = &ip->irqdomain_cfg;
2304         struct mp_ioapic_gsi *gsi_cfg = mp_ioapic_gsi_routing(ioapic);
2305         struct fwnode_handle *fn;
2306         char *name = "IO-APIC";
2307 
2308         if (cfg->type == IOAPIC_DOMAIN_INVALID)
2309                 return 0;
2310 
2311         init_irq_alloc_info(&info, NULL);
2312         info.type = X86_IRQ_ALLOC_TYPE_IOAPIC;
2313         info.ioapic_id = mpc_ioapic_id(ioapic);
2314         parent = irq_remapping_get_ir_irq_domain(&info);
2315         if (!parent)
2316                 parent = x86_vector_domain;
2317         else
2318                 name = "IO-APIC-IR";
2319 
2320         /* Handle device tree enumerated APICs proper */
2321         if (cfg->dev) {
2322                 fn = of_node_to_fwnode(cfg->dev);
2323         } else {
2324                 fn = irq_domain_alloc_named_id_fwnode(name, ioapic);
2325                 if (!fn)
2326                         return -ENOMEM;
2327         }
2328 
2329         ip->irqdomain = irq_domain_create_linear(fn, hwirqs, cfg->ops,
2330                                                  (void *)(long)ioapic);
2331 
2332         /* Release fw handle if it was allocated above */
2333         if (!cfg->dev)
2334                 irq_domain_free_fwnode(fn);
2335 
2336         if (!ip->irqdomain)
2337                 return -ENOMEM;
2338 
2339         ip->irqdomain->parent = parent;
2340 
2341         if (cfg->type == IOAPIC_DOMAIN_LEGACY ||
2342             cfg->type == IOAPIC_DOMAIN_STRICT)
2343                 ioapic_dynirq_base = max(ioapic_dynirq_base,
2344                                          gsi_cfg->gsi_end + 1);
2345 
2346         return 0;
2347 }
2348 
2349 static void ioapic_destroy_irqdomain(int idx)
2350 {
2351         if (ioapics[idx].irqdomain) {
2352                 irq_domain_remove(ioapics[idx].irqdomain);
2353                 ioapics[idx].irqdomain = NULL;
2354         }
2355 }
2356 
2357 void __init setup_IO_APIC(void)
2358 {
2359         int ioapic;
2360 
2361         if (skip_ioapic_setup || !nr_ioapics)
2362                 return;
2363 
2364         io_apic_irqs = nr_legacy_irqs() ? ~PIC_IRQS : ~0UL;
2365 
2366         apic_printk(APIC_VERBOSE, "ENABLING IO-APIC IRQs\n");
2367         for_each_ioapic(ioapic)
2368                 BUG_ON(mp_irqdomain_create(ioapic));
2369 
2370         /*
2371          * Set up IO-APIC IRQ routing.
2372          */
2373         x86_init.mpparse.setup_ioapic_ids();
2374 
2375         sync_Arb_IDs();
2376         setup_IO_APIC_irqs();
2377         init_IO_APIC_traps();
2378         if (nr_legacy_irqs())
2379                 check_timer();
2380 
2381         ioapic_initialized = 1;
2382 }
2383 
2384 static void resume_ioapic_id(int ioapic_idx)
2385 {
2386         unsigned long flags;
2387         union IO_APIC_reg_00 reg_00;
2388 
2389         raw_spin_lock_irqsave(&ioapic_lock, flags);
2390         reg_00.raw = io_apic_read(ioapic_idx, 0);
2391         if (reg_00.bits.ID != mpc_ioapic_id(ioapic_idx)) {
2392                 reg_00.bits.ID = mpc_ioapic_id(ioapic_idx);
2393                 io_apic_write(ioapic_idx, 0, reg_00.raw);
2394         }
2395         raw_spin_unlock_irqrestore(&ioapic_lock, flags);
2396 }
2397 
2398 static void ioapic_resume(void)
2399 {
2400         int ioapic_idx;
2401 
2402         for_each_ioapic_reverse(ioapic_idx)
2403                 resume_ioapic_id(ioapic_idx);
2404 
2405         restore_ioapic_entries();
2406 }
2407 
2408 static struct syscore_ops ioapic_syscore_ops = {
2409         .suspend = save_ioapic_entries,
2410         .resume = ioapic_resume,
2411 };
2412 
2413 static int __init ioapic_init_ops(void)
2414 {
2415         register_syscore_ops(&ioapic_syscore_ops);
2416 
2417         return 0;
2418 }
2419 
2420 device_initcall(ioapic_init_ops);
2421 
2422 static int io_apic_get_redir_entries(int ioapic)
2423 {
2424         union IO_APIC_reg_01    reg_01;
2425         unsigned long flags;
2426 
2427         raw_spin_lock_irqsave(&ioapic_lock, flags);
2428         reg_01.raw = io_apic_read(ioapic, 1);
2429         raw_spin_unlock_irqrestore(&ioapic_lock, flags);
2430 
2431         /* The register returns the maximum index redir index
2432          * supported, which is one less than the total number of redir
2433          * entries.
2434          */
2435         return reg_01.bits.entries + 1;
2436 }
2437 
2438 unsigned int arch_dynirq_lower_bound(unsigned int from)
2439 {
2440         /*
2441          * dmar_alloc_hwirq() may be called before setup_IO_APIC(), so use
2442          * gsi_top if ioapic_dynirq_base hasn't been initialized yet.
2443          */
2444         if (!ioapic_initialized)
2445                 return gsi_top;
2446         /*
2447          * For DT enabled machines ioapic_dynirq_base is irrelevant and not
2448          * updated. So simply return @from if ioapic_dynirq_base == 0.
2449          */
2450         return ioapic_dynirq_base ? : from;
2451 }
2452 
2453 #ifdef CONFIG_X86_32
2454 static int io_apic_get_unique_id(int ioapic, int apic_id)
2455 {
2456         union IO_APIC_reg_00 reg_00;
2457         static physid_mask_t apic_id_map = PHYSID_MASK_NONE;
2458         physid_mask_t tmp;
2459         unsigned long flags;
2460         int i = 0;
2461 
2462         /*
2463          * The P4 platform supports up to 256 APIC IDs on two separate APIC
2464          * buses (one for LAPICs, one for IOAPICs), where predecessors only
2465          * supports up to 16 on one shared APIC bus.
2466          *
2467          * TBD: Expand LAPIC/IOAPIC support on P4-class systems to take full
2468          *      advantage of new APIC bus architecture.
2469          */
2470 
2471         if (physids_empty(apic_id_map))
2472                 apic->ioapic_phys_id_map(&phys_cpu_present_map, &apic_id_map);
2473 
2474         raw_spin_lock_irqsave(&ioapic_lock, flags);
2475         reg_00.raw = io_apic_read(ioapic, 0);
2476         raw_spin_unlock_irqrestore(&ioapic_lock, flags);
2477 
2478         if (apic_id >= get_physical_broadcast()) {
2479                 printk(KERN_WARNING "IOAPIC[%d]: Invalid apic_id %d, trying "
2480                         "%d\n", ioapic, apic_id, reg_00.bits.ID);
2481                 apic_id = reg_00.bits.ID;
2482         }
2483 
2484         /*
2485          * Every APIC in a system must have a unique ID or we get lots of nice
2486          * 'stuck on smp_invalidate_needed IPI wait' messages.
2487          */
2488         if (apic->check_apicid_used(&apic_id_map, apic_id)) {
2489 
2490                 for (i = 0; i < get_physical_broadcast(); i++) {
2491                         if (!apic->check_apicid_used(&apic_id_map, i))
2492                                 break;
2493                 }
2494 
2495                 if (i == get_physical_broadcast())
2496                         panic("Max apic_id exceeded!\n");
2497 
2498                 printk(KERN_WARNING "IOAPIC[%d]: apic_id %d already used, "
2499                         "trying %d\n", ioapic, apic_id, i);
2500 
2501                 apic_id = i;
2502         }
2503 
2504         apic->apicid_to_cpu_present(apic_id, &tmp);
2505         physids_or(apic_id_map, apic_id_map, tmp);
2506 
2507         if (reg_00.bits.ID != apic_id) {
2508                 reg_00.bits.ID = apic_id;
2509 
2510                 raw_spin_lock_irqsave(&ioapic_lock, flags);
2511                 io_apic_write(ioapic, 0, reg_00.raw);
2512                 reg_00.raw = io_apic_read(ioapic, 0);
2513                 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
2514 
2515                 /* Sanity check */
2516                 if (reg_00.bits.ID != apic_id) {
2517                         pr_err("IOAPIC[%d]: Unable to change apic_id!\n",
2518                                ioapic);
2519                         return -1;
2520                 }
2521         }
2522 
2523         apic_printk(APIC_VERBOSE, KERN_INFO
2524                         "IOAPIC[%d]: Assigned apic_id %d\n", ioapic, apic_id);
2525 
2526         return apic_id;
2527 }
2528 
2529 static u8 io_apic_unique_id(int idx, u8 id)
2530 {
2531         if ((boot_cpu_data.x86_vendor == X86_VENDOR_INTEL) &&
2532             !APIC_XAPIC(boot_cpu_apic_version))
2533                 return io_apic_get_unique_id(idx, id);
2534         else
2535                 return id;
2536 }
2537 #else
2538 static u8 io_apic_unique_id(int idx, u8 id)
2539 {
2540         union IO_APIC_reg_00 reg_00;
2541         DECLARE_BITMAP(used, 256);
2542         unsigned long flags;
2543         u8 new_id;
2544         int i;
2545 
2546         bitmap_zero(used, 256);
2547         for_each_ioapic(i)
2548                 __set_bit(mpc_ioapic_id(i), used);
2549 
2550         /* Hand out the requested id if available */
2551         if (!test_bit(id, used))
2552                 return id;
2553 
2554         /*
2555          * Read the current id from the ioapic and keep it if
2556          * available.
2557          */
2558         raw_spin_lock_irqsave(&ioapic_lock, flags);
2559         reg_00.raw = io_apic_read(idx, 0);
2560         raw_spin_unlock_irqrestore(&ioapic_lock, flags);
2561         new_id = reg_00.bits.ID;
2562         if (!test_bit(new_id, used)) {
2563                 apic_printk(APIC_VERBOSE, KERN_INFO
2564                         "IOAPIC[%d]: Using reg apic_id %d instead of %d\n",
2565                          idx, new_id, id);
2566                 return new_id;
2567         }
2568 
2569         /*
2570          * Get the next free id and write it to the ioapic.
2571          */
2572         new_id = find_first_zero_bit(used, 256);
2573         reg_00.bits.ID = new_id;
2574         raw_spin_lock_irqsave(&ioapic_lock, flags);
2575         io_apic_write(idx, 0, reg_00.raw);
2576         reg_00.raw = io_apic_read(idx, 0);
2577         raw_spin_unlock_irqrestore(&ioapic_lock, flags);
2578         /* Sanity check */
2579         BUG_ON(reg_00.bits.ID != new_id);
2580 
2581         return new_id;
2582 }
2583 #endif
2584 
2585 static int io_apic_get_version(int ioapic)
2586 {
2587         union IO_APIC_reg_01    reg_01;
2588         unsigned long flags;
2589 
2590         raw_spin_lock_irqsave(&ioapic_lock, flags);
2591         reg_01.raw = io_apic_read(ioapic, 1);
2592         raw_spin_unlock_irqrestore(&ioapic_lock, flags);
2593 
2594         return reg_01.bits.version;
2595 }
2596 
2597 int acpi_get_override_irq(u32 gsi, int *trigger, int *polarity)
2598 {
2599         int ioapic, pin, idx;
2600 
2601         if (skip_ioapic_setup)
2602                 return -1;
2603 
2604         ioapic = mp_find_ioapic(gsi);
2605         if (ioapic < 0)
2606                 return -1;
2607 
2608         pin = mp_find_ioapic_pin(ioapic, gsi);
2609         if (pin < 0)
2610                 return -1;
2611 
2612         idx = find_irq_entry(ioapic, pin, mp_INT);
2613         if (idx < 0)
2614                 return -1;
2615 
2616         *trigger = irq_trigger(idx);
2617         *polarity = irq_polarity(idx);
2618         return 0;
2619 }
2620 
2621 /*
2622  * This function updates target affinity of IOAPIC interrupts to include
2623  * the CPUs which came online during SMP bringup.
2624  */
2625 #define IOAPIC_RESOURCE_NAME_SIZE 11
2626 
2627 static struct resource *ioapic_resources;
2628 
2629 static struct resource * __init ioapic_setup_resources(void)
2630 {
2631         unsigned long n;
2632         struct resource *res;
2633         char *mem;
2634         int i;
2635 
2636         if (nr_ioapics == 0)
2637                 return NULL;
2638 
2639         n = IOAPIC_RESOURCE_NAME_SIZE + sizeof(struct resource);
2640         n *= nr_ioapics;
2641 
2642         mem = memblock_alloc(n, SMP_CACHE_BYTES);
2643         if (!mem)
2644                 panic("%s: Failed to allocate %lu bytes\n", __func__, n);
2645         res = (void *)mem;
2646 
2647         mem += sizeof(struct resource) * nr_ioapics;
2648 
2649         for_each_ioapic(i) {
2650                 res[i].name = mem;
2651                 res[i].flags = IORESOURCE_MEM | IORESOURCE_BUSY;
2652                 snprintf(mem, IOAPIC_RESOURCE_NAME_SIZE, "IOAPIC %u", i);
2653                 mem += IOAPIC_RESOURCE_NAME_SIZE;
2654                 ioapics[i].iomem_res = &res[i];
2655         }
2656 
2657         ioapic_resources = res;
2658 
2659         return res;
2660 }
2661 
2662 void __init io_apic_init_mappings(void)
2663 {
2664         unsigned long ioapic_phys, idx = FIX_IO_APIC_BASE_0;
2665         struct resource *ioapic_res;
2666         int i;
2667 
2668         ioapic_res = ioapic_setup_resources();
2669         for_each_ioapic(i) {
2670                 if (smp_found_config) {
2671                         ioapic_phys = mpc_ioapic_addr(i);
2672 #ifdef CONFIG_X86_32
2673                         if (!ioapic_phys) {
2674                                 printk(KERN_ERR
2675                                        "WARNING: bogus zero IO-APIC "
2676                                        "address found in MPTABLE, "
2677                                        "disabling IO/APIC support!\n");
2678                                 smp_found_config = 0;
2679                                 skip_ioapic_setup = 1;
2680                                 goto fake_ioapic_page;
2681                         }
2682 #endif
2683                 } else {
2684 #ifdef CONFIG_X86_32
2685 fake_ioapic_page:
2686 #endif
2687                         ioapic_phys = (unsigned long)memblock_alloc(PAGE_SIZE,
2688                                                                     PAGE_SIZE);
2689                         if (!ioapic_phys)
2690                                 panic("%s: Failed to allocate %lu bytes align=0x%lx\n",
2691                                       __func__, PAGE_SIZE, PAGE_SIZE);
2692                         ioapic_phys = __pa(ioapic_phys);
2693                 }
2694                 set_fixmap_nocache(idx, ioapic_phys);
2695                 apic_printk(APIC_VERBOSE, "mapped IOAPIC to %08lx (%08lx)\n",
2696                         __fix_to_virt(idx) + (ioapic_phys & ~PAGE_MASK),
2697                         ioapic_phys);
2698                 idx++;
2699 
2700                 ioapic_res->start = ioapic_phys;
2701                 ioapic_res->end = ioapic_phys + IO_APIC_SLOT_SIZE - 1;
2702                 ioapic_res++;
2703         }
2704 }
2705 
2706 void __init ioapic_insert_resources(void)
2707 {
2708         int i;
2709         struct resource *r = ioapic_resources;
2710 
2711         if (!r) {
2712                 if (nr_ioapics > 0)
2713                         printk(KERN_ERR
2714                                 "IO APIC resources couldn't be allocated.\n");
2715                 return;
2716         }
2717 
2718         for_each_ioapic(i) {
2719                 insert_resource(&iomem_resource, r);
2720                 r++;
2721         }
2722 }
2723 
2724 int mp_find_ioapic(u32 gsi)
2725 {
2726         int i;
2727 
2728         if (nr_ioapics == 0)
2729                 return -1;
2730 
2731         /* Find the IOAPIC that manages this GSI. */
2732         for_each_ioapic(i) {
2733                 struct mp_ioapic_gsi *gsi_cfg = mp_ioapic_gsi_routing(i);
2734                 if (gsi >= gsi_cfg->gsi_base && gsi <= gsi_cfg->gsi_end)
2735                         return i;
2736         }
2737 
2738         printk(KERN_ERR "ERROR: Unable to locate IOAPIC for GSI %d\n", gsi);
2739         return -1;
2740 }
2741 
2742 int mp_find_ioapic_pin(int ioapic, u32 gsi)
2743 {
2744         struct mp_ioapic_gsi *gsi_cfg;
2745 
2746         if (WARN_ON(ioapic < 0))
2747                 return -1;
2748 
2749         gsi_cfg = mp_ioapic_gsi_routing(ioapic);
2750         if (WARN_ON(gsi > gsi_cfg->gsi_end))
2751                 return -1;
2752 
2753         return gsi - gsi_cfg->gsi_base;
2754 }
2755 
2756 static int bad_ioapic_register(int idx)
2757 {
2758         union IO_APIC_reg_00 reg_00;
2759         union IO_APIC_reg_01 reg_01;
2760         union IO_APIC_reg_02 reg_02;
2761 
2762         reg_00.raw = io_apic_read(idx, 0);
2763         reg_01.raw = io_apic_read(idx, 1);
2764         reg_02.raw = io_apic_read(idx, 2);
2765 
2766         if (reg_00.raw == -1 && reg_01.raw == -1 && reg_02.raw == -1) {
2767                 pr_warn("I/O APIC 0x%x registers return all ones, skipping!\n",
2768                         mpc_ioapic_addr(idx));
2769                 return 1;
2770         }
2771 
2772         return 0;
2773 }
2774 
2775 static int find_free_ioapic_entry(void)
2776 {
2777         int idx;
2778 
2779         for (idx = 0; idx < MAX_IO_APICS; idx++)
2780                 if (ioapics[idx].nr_registers == 0)
2781                         return idx;
2782 
2783         return MAX_IO_APICS;
2784 }
2785 
2786 /**
2787  * mp_register_ioapic - Register an IOAPIC device
2788  * @id:         hardware IOAPIC ID
2789  * @address:    physical address of IOAPIC register area
2790  * @gsi_base:   base of GSI associated with the IOAPIC
2791  * @cfg:        configuration information for the IOAPIC
2792  */
2793 int mp_register_ioapic(int id, u32 address, u32 gsi_base,
2794                        struct ioapic_domain_cfg *cfg)
2795 {
2796         bool hotplug = !!ioapic_initialized;
2797         struct mp_ioapic_gsi *gsi_cfg;
2798         int idx, ioapic, entries;
2799         u32 gsi_end;
2800 
2801         if (!address) {
2802                 pr_warn("Bogus (zero) I/O APIC address found, skipping!\n");
2803                 return -EINVAL;
2804         }
2805         for_each_ioapic(ioapic)
2806                 if (ioapics[ioapic].mp_config.apicaddr == address) {
2807                         pr_warn("address 0x%x conflicts with IOAPIC%d\n",
2808                                 address, ioapic);
2809                         return -EEXIST;
2810                 }
2811 
2812         idx = find_free_ioapic_entry();
2813         if (idx >= MAX_IO_APICS) {
2814                 pr_warn("Max # of I/O APICs (%d) exceeded (found %d), skipping\n",
2815                         MAX_IO_APICS, idx);
2816                 return -ENOSPC;
2817         }
2818 
2819         ioapics[idx].mp_config.type = MP_IOAPIC;
2820         ioapics[idx].mp_config.flags = MPC_APIC_USABLE;
2821         ioapics[idx].mp_config.apicaddr = address;
2822 
2823         set_fixmap_nocache(FIX_IO_APIC_BASE_0 + idx, address);
2824         if (bad_ioapic_register(idx)) {
2825                 clear_fixmap(FIX_IO_APIC_BASE_0 + idx);
2826                 return -ENODEV;
2827         }
2828 
2829         ioapics[idx].mp_config.apicid = io_apic_unique_id(idx, id);
2830         ioapics[idx].mp_config.apicver = io_apic_get_version(idx);
2831 
2832         /*
2833          * Build basic GSI lookup table to facilitate gsi->io_apic lookups
2834          * and to prevent reprogramming of IOAPIC pins (PCI GSIs).
2835          */
2836         entries = io_apic_get_redir_entries(idx);
2837         gsi_end = gsi_base + entries - 1;
2838         for_each_ioapic(ioapic) {
2839                 gsi_cfg = mp_ioapic_gsi_routing(ioapic);
2840                 if ((gsi_base >= gsi_cfg->gsi_base &&
2841                      gsi_base <= gsi_cfg->gsi_end) ||
2842                     (gsi_end >= gsi_cfg->gsi_base &&
2843                      gsi_end <= gsi_cfg->gsi_end)) {
2844                         pr_warn("GSI range [%u-%u] for new IOAPIC conflicts with GSI[%u-%u]\n",
2845                                 gsi_base, gsi_end,
2846                                 gsi_cfg->gsi_base, gsi_cfg->gsi_end);
2847                         clear_fixmap(FIX_IO_APIC_BASE_0 + idx);
2848                         return -ENOSPC;
2849                 }
2850         }
2851         gsi_cfg = mp_ioapic_gsi_routing(idx);
2852         gsi_cfg->gsi_base = gsi_base;
2853         gsi_cfg->gsi_end = gsi_end;
2854 
2855         ioapics[idx].irqdomain = NULL;
2856         ioapics[idx].irqdomain_cfg = *cfg;
2857 
2858         /*
2859          * If mp_register_ioapic() is called during early boot stage when
2860          * walking ACPI/SFI/DT tables, it's too early to create irqdomain,
2861          * we are still using bootmem allocator. So delay it to setup_IO_APIC().
2862          */
2863         if (hotplug) {
2864                 if (mp_irqdomain_create(idx)) {
2865                         clear_fixmap(FIX_IO_APIC_BASE_0 + idx);
2866                         return -ENOMEM;
2867                 }
2868                 alloc_ioapic_saved_registers(idx);
2869         }
2870 
2871         if (gsi_cfg->gsi_end >= gsi_top)
2872                 gsi_top = gsi_cfg->gsi_end + 1;
2873         if (nr_ioapics <= idx)
2874                 nr_ioapics = idx + 1;
2875 
2876         /* Set nr_registers to mark entry present */
2877         ioapics[idx].nr_registers = entries;
2878 
2879         pr_info("IOAPIC[%d]: apic_id %d, version %d, address 0x%x, GSI %d-%d\n",
2880                 idx, mpc_ioapic_id(idx),
2881                 mpc_ioapic_ver(idx), mpc_ioapic_addr(idx),
2882                 gsi_cfg->gsi_base, gsi_cfg->gsi_end);
2883 
2884         return 0;
2885 }
2886 
2887 int mp_unregister_ioapic(u32 gsi_base)
2888 {
2889         int ioapic, pin;
2890         int found = 0;
2891 
2892         for_each_ioapic(ioapic)
2893                 if (ioapics[ioapic].gsi_config.gsi_base == gsi_base) {
2894                         found = 1;
2895                         break;
2896                 }
2897         if (!found) {
2898                 pr_warn("can't find IOAPIC for GSI %d\n", gsi_base);
2899                 return -ENODEV;
2900         }
2901 
2902         for_each_pin(ioapic, pin) {
2903                 u32 gsi = mp_pin_to_gsi(ioapic, pin);
2904                 int irq = mp_map_gsi_to_irq(gsi, 0, NULL);
2905                 struct mp_chip_data *data;
2906 
2907                 if (irq >= 0) {
2908                         data = irq_get_chip_data(irq);
2909                         if (data && data->count) {
2910                                 pr_warn("pin%d on IOAPIC%d is still in use.\n",
2911                                         pin, ioapic);
2912                                 return -EBUSY;
2913                         }
2914                 }
2915         }
2916 
2917         /* Mark entry not present */
2918         ioapics[ioapic].nr_registers  = 0;
2919         ioapic_destroy_irqdomain(ioapic);
2920         free_ioapic_saved_registers(ioapic);
2921         if (ioapics[ioapic].iomem_res)
2922                 release_resource(ioapics[ioapic].iomem_res);
2923         clear_fixmap(FIX_IO_APIC_BASE_0 + ioapic);
2924         memset(&ioapics[ioapic], 0, sizeof(ioapics[ioapic]));
2925 
2926         return 0;
2927 }
2928 
2929 int mp_ioapic_registered(u32 gsi_base)
2930 {
2931         int ioapic;
2932 
2933         for_each_ioapic(ioapic)
2934                 if (ioapics[ioapic].gsi_config.gsi_base == gsi_base)
2935                         return 1;
2936 
2937         return 0;
2938 }
2939 
2940 static void mp_irqdomain_get_attr(u32 gsi, struct mp_chip_data *data,
2941                                   struct irq_alloc_info *info)
2942 {
2943         if (info && info->ioapic_valid) {
2944                 data->trigger = info->ioapic_trigger;
2945                 data->polarity = info->ioapic_polarity;
2946         } else if (acpi_get_override_irq(gsi, &data->trigger,
2947                                          &data->polarity) < 0) {
2948                 /* PCI interrupts are always active low level triggered. */
2949                 data->trigger = IOAPIC_LEVEL;
2950                 data->polarity = IOAPIC_POL_LOW;
2951         }
2952 }
2953 
2954 static void mp_setup_entry(struct irq_cfg *cfg, struct mp_chip_data *data,
2955                            struct IO_APIC_route_entry *entry)
2956 {
2957         memset(entry, 0, sizeof(*entry));
2958         entry->delivery_mode = apic->irq_delivery_mode;
2959         entry->dest_mode     = apic->irq_dest_mode;
2960         entry->dest          = cfg->dest_apicid;
2961         entry->vector        = cfg->vector;
2962         entry->trigger       = data->trigger;
2963         entry->polarity      = data->polarity;
2964         /*
2965          * Mask level triggered irqs. Edge triggered irqs are masked
2966          * by the irq core code in case they fire.
2967          */
2968         if (data->trigger == IOAPIC_LEVEL)
2969                 entry->mask = IOAPIC_MASKED;
2970         else
2971                 entry->mask = IOAPIC_UNMASKED;
2972 }
2973 
2974 int mp_irqdomain_alloc(struct irq_domain *domain, unsigned int virq,
2975                        unsigned int nr_irqs, void *arg)
2976 {
2977         int ret, ioapic, pin;
2978         struct irq_cfg *cfg;
2979         struct irq_data *irq_data;
2980         struct mp_chip_data *data;
2981         struct irq_alloc_info *info = arg;
2982         unsigned long flags;
2983 
2984         if (!info || nr_irqs > 1)
2985                 return -EINVAL;
2986         irq_data = irq_domain_get_irq_data(domain, virq);
2987         if (!irq_data)
2988                 return -EINVAL;
2989 
2990         ioapic = mp_irqdomain_ioapic_idx(domain);
2991         pin = info->ioapic_pin;
2992         if (irq_find_mapping(domain, (irq_hw_number_t)pin) > 0)
2993                 return -EEXIST;
2994 
2995         data = kzalloc(sizeof(*data), GFP_KERNEL);
2996         if (!data)
2997                 return -ENOMEM;
2998 
2999         info->ioapic_entry = &data->entry;
3000         ret = irq_domain_alloc_irqs_parent(domain, virq, nr_irqs, info);
3001         if (ret < 0) {
3002                 kfree(data);
3003                 return ret;
3004         }
3005 
3006         INIT_LIST_HEAD(&data->irq_2_pin);
3007         irq_data->hwirq = info->ioapic_pin;
3008         irq_data->chip = (domain->parent == x86_vector_domain) ?
3009                           &ioapic_chip : &ioapic_ir_chip;
3010         irq_data->chip_data = data;
3011         mp_irqdomain_get_attr(mp_pin_to_gsi(ioapic, pin), data, info);
3012 
3013         cfg = irqd_cfg(irq_data);
3014         add_pin_to_irq_node(data, ioapic_alloc_attr_node(info), ioapic, pin);
3015 
3016         local_irq_save(flags);
3017         if (info->ioapic_entry)
3018                 mp_setup_entry(cfg, data, info->ioapic_entry);
3019         mp_register_handler(virq, data->trigger);
3020         if (virq < nr_legacy_irqs())
3021                 legacy_pic->mask(virq);
3022         local_irq_restore(flags);
3023 
3024         apic_printk(APIC_VERBOSE, KERN_DEBUG
3025                     "IOAPIC[%d]: Set routing entry (%d-%d -> 0x%x -> IRQ %d Mode:%i Active:%i Dest:%d)\n",
3026                     ioapic, mpc_ioapic_id(ioapic), pin, cfg->vector,
3027                     virq, data->trigger, data->polarity, cfg->dest_apicid);
3028 
3029         return 0;
3030 }
3031 
3032 void mp_irqdomain_free(struct irq_domain *domain, unsigned int virq,
3033                        unsigned int nr_irqs)
3034 {
3035         struct irq_data *irq_data;
3036         struct mp_chip_data *data;
3037 
3038         BUG_ON(nr_irqs != 1);
3039         irq_data = irq_domain_get_irq_data(domain, virq);
3040         if (irq_data && irq_data->chip_data) {
3041                 data = irq_data->chip_data;
3042                 __remove_pin_from_irq(data, mp_irqdomain_ioapic_idx(domain),
3043                                       (int)irq_data->hwirq);
3044                 WARN_ON(!list_empty(&data->irq_2_pin));
3045                 kfree(irq_data->chip_data);
3046         }
3047         irq_domain_free_irqs_top(domain, virq, nr_irqs);
3048 }
3049 
3050 int mp_irqdomain_activate(struct irq_domain *domain,
3051                           struct irq_data *irq_data, bool reserve)
3052 {
3053         unsigned long flags;
3054 
3055         raw_spin_lock_irqsave(&ioapic_lock, flags);
3056         ioapic_configure_entry(irq_data);
3057         raw_spin_unlock_irqrestore(&ioapic_lock, flags);
3058         return 0;
3059 }
3060 
3061 void mp_irqdomain_deactivate(struct irq_domain *domain,
3062                              struct irq_data *irq_data)
3063 {
3064         /* It won't be called for IRQ with multiple IOAPIC pins associated */
3065         ioapic_mask_entry(mp_irqdomain_ioapic_idx(domain),
3066                           (int)irq_data->hwirq);
3067 }
3068 
3069 int mp_irqdomain_ioapic_idx(struct irq_domain *domain)
3070 {
3071         return (int)(long)domain->host_data;
3072 }
3073 
3074 const struct irq_domain_ops mp_ioapic_irqdomain_ops = {
3075         .alloc          = mp_irqdomain_alloc,
3076         .free           = mp_irqdomain_free,
3077         .activate       = mp_irqdomain_activate,
3078         .deactivate     = mp_irqdomain_deactivate,
3079 };
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root/arch/x86/kernel/apic/io_apic.c

DEFINITIONS
