arch/x86/kernel/smpboot.c

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This source file includes following definitions.
arch_update_cpu_topology
smpboot_setup_warm_reset_vector
smpboot_restore_warm_reset_vector
smp_callin
start_secondary
topology_is_primary_thread
topology_smt_supported
topology_phys_to_logical_pkg
topology_phys_to_logical_die
topology_update_package_map
topology_update_die_map
smp_store_boot_cpu_info
smp_store_cpu_info
topology_same_node
topology_sane
match_smt
match_llc
match_pkg
match_die
x86_sched_itmt_flags
x86_core_flags
x86_smt_flags
set_cpu_sibling_map
cpu_coregroup_mask
impress_friends
__inquire_remote_apic
cpu_init_udelay
smp_quirk_init_udelay
wakeup_secondary_cpu_via_nmi
wakeup_secondary_cpu_via_init
announce_cpu
wakeup_cpu0_nmi
wakeup_cpu_via_init_nmi
common_cpu_up
do_boot_cpu
native_cpu_up
arch_disable_smp_support
disable_smp
smp_sanity_check
smp_cpu_index_default
smp_get_logical_apicid
native_smp_prepare_cpus
arch_enable_nonboot_cpus_begin
arch_enable_nonboot_cpus_end
native_smp_prepare_boot_cpu
calculate_max_logical_packages
native_smp_cpus_done
_setup_possible_cpus
prefill_possible_map
recompute_smt_state
remove_siblinginfo
remove_cpu_from_maps
cpu_disable_common
native_cpu_disable
common_cpu_die
native_cpu_die
play_dead_common
wakeup_cpu0
mwait_play_dead
hlt_play_dead
native_play_dead
native_cpu_disable
native_cpu_die
native_play_dead
   1 // SPDX-License-Identifier: GPL-2.0-or-later
   2  /*
   3  *      x86 SMP booting functions
   4  *
   5  *      (c) 1995 Alan Cox, Building #3 <alan@lxorguk.ukuu.org.uk>
   6  *      (c) 1998, 1999, 2000, 2009 Ingo Molnar <mingo@redhat.com>
   7  *      Copyright 2001 Andi Kleen, SuSE Labs.
   8  *
   9  *      Much of the core SMP work is based on previous work by Thomas Radke, to
  10  *      whom a great many thanks are extended.
  11  *
  12  *      Thanks to Intel for making available several different Pentium,
  13  *      Pentium Pro and Pentium-II/Xeon MP machines.
  14  *      Original development of Linux SMP code supported by Caldera.
  15  *
  16  *      Fixes
  17  *              Felix Koop      :       NR_CPUS used properly
  18  *              Jose Renau      :       Handle single CPU case.
  19  *              Alan Cox        :       By repeated request 8) - Total BogoMIPS report.
  20  *              Greg Wright     :       Fix for kernel stacks panic.
  21  *              Erich Boleyn    :       MP v1.4 and additional changes.
  22  *      Matthias Sattler        :       Changes for 2.1 kernel map.
  23  *      Michel Lespinasse       :       Changes for 2.1 kernel map.
  24  *      Michael Chastain        :       Change trampoline.S to gnu as.
  25  *              Alan Cox        :       Dumb bug: 'B' step PPro's are fine
  26  *              Ingo Molnar     :       Added APIC timers, based on code
  27  *                                      from Jose Renau
  28  *              Ingo Molnar     :       various cleanups and rewrites
  29  *              Tigran Aivazian :       fixed "0.00 in /proc/uptime on SMP" bug.
  30  *      Maciej W. Rozycki       :       Bits for genuine 82489DX APICs
  31  *      Andi Kleen              :       Changed for SMP boot into long mode.
  32  *              Martin J. Bligh :       Added support for multi-quad systems
  33  *              Dave Jones      :       Report invalid combinations of Athlon CPUs.
  34  *              Rusty Russell   :       Hacked into shape for new "hotplug" boot process.
  35  *      Andi Kleen              :       Converted to new state machine.
  36  *      Ashok Raj               :       CPU hotplug support
  37  *      Glauber Costa           :       i386 and x86_64 integration
  38  */
  39 
  40 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
  41 
  42 #include <linux/init.h>
  43 #include <linux/smp.h>
  44 #include <linux/export.h>
  45 #include <linux/sched.h>
  46 #include <linux/sched/topology.h>
  47 #include <linux/sched/hotplug.h>
  48 #include <linux/sched/task_stack.h>
  49 #include <linux/percpu.h>
  50 #include <linux/memblock.h>
  51 #include <linux/err.h>
  52 #include <linux/nmi.h>
  53 #include <linux/tboot.h>
  54 #include <linux/stackprotector.h>
  55 #include <linux/gfp.h>
  56 #include <linux/cpuidle.h>
  57 #include <linux/numa.h>
  58 
  59 #include <asm/acpi.h>
  60 #include <asm/desc.h>
  61 #include <asm/nmi.h>
  62 #include <asm/irq.h>
  63 #include <asm/realmode.h>
  64 #include <asm/cpu.h>
  65 #include <asm/numa.h>
  66 #include <asm/pgtable.h>
  67 #include <asm/tlbflush.h>
  68 #include <asm/mtrr.h>
  69 #include <asm/mwait.h>
  70 #include <asm/apic.h>
  71 #include <asm/io_apic.h>
  72 #include <asm/fpu/internal.h>
  73 #include <asm/setup.h>
  74 #include <asm/uv/uv.h>
  75 #include <linux/mc146818rtc.h>
  76 #include <asm/i8259.h>
  77 #include <asm/misc.h>
  78 #include <asm/qspinlock.h>
  79 #include <asm/intel-family.h>
  80 #include <asm/cpu_device_id.h>
  81 #include <asm/spec-ctrl.h>
  82 #include <asm/hw_irq.h>
  83 
  84 /* representing HT siblings of each logical CPU */
  85 DEFINE_PER_CPU_READ_MOSTLY(cpumask_var_t, cpu_sibling_map);
  86 EXPORT_PER_CPU_SYMBOL(cpu_sibling_map);
  87 
  88 /* representing HT and core siblings of each logical CPU */
  89 DEFINE_PER_CPU_READ_MOSTLY(cpumask_var_t, cpu_core_map);
  90 EXPORT_PER_CPU_SYMBOL(cpu_core_map);
  91 
  92 /* representing HT, core, and die siblings of each logical CPU */
  93 DEFINE_PER_CPU_READ_MOSTLY(cpumask_var_t, cpu_die_map);
  94 EXPORT_PER_CPU_SYMBOL(cpu_die_map);
  95 
  96 DEFINE_PER_CPU_READ_MOSTLY(cpumask_var_t, cpu_llc_shared_map);
  97 
  98 /* Per CPU bogomips and other parameters */
  99 DEFINE_PER_CPU_READ_MOSTLY(struct cpuinfo_x86, cpu_info);
 100 EXPORT_PER_CPU_SYMBOL(cpu_info);
 101 
 102 /* Logical package management. We might want to allocate that dynamically */
 103 unsigned int __max_logical_packages __read_mostly;
 104 EXPORT_SYMBOL(__max_logical_packages);
 105 static unsigned int logical_packages __read_mostly;
 106 static unsigned int logical_die __read_mostly;
 107 
 108 /* Maximum number of SMT threads on any online core */
 109 int __read_mostly __max_smt_threads = 1;
 110 
 111 /* Flag to indicate if a complete sched domain rebuild is required */
 112 bool x86_topology_update;
 113 
 114 int arch_update_cpu_topology(void)
 115 {
 116         int retval = x86_topology_update;
 117 
 118         x86_topology_update = false;
 119         return retval;
 120 }
 121 
 122 static inline void smpboot_setup_warm_reset_vector(unsigned long start_eip)
 123 {
 124         unsigned long flags;
 125 
 126         spin_lock_irqsave(&rtc_lock, flags);
 127         CMOS_WRITE(0xa, 0xf);
 128         spin_unlock_irqrestore(&rtc_lock, flags);
 129         *((volatile unsigned short *)phys_to_virt(TRAMPOLINE_PHYS_HIGH)) =
 130                                                         start_eip >> 4;
 131         *((volatile unsigned short *)phys_to_virt(TRAMPOLINE_PHYS_LOW)) =
 132                                                         start_eip & 0xf;
 133 }
 134 
 135 static inline void smpboot_restore_warm_reset_vector(void)
 136 {
 137         unsigned long flags;
 138 
 139         /*
 140          * Paranoid:  Set warm reset code and vector here back
 141          * to default values.
 142          */
 143         spin_lock_irqsave(&rtc_lock, flags);
 144         CMOS_WRITE(0, 0xf);
 145         spin_unlock_irqrestore(&rtc_lock, flags);
 146 
 147         *((volatile u32 *)phys_to_virt(TRAMPOLINE_PHYS_LOW)) = 0;
 148 }
 149 
 150 /*
 151  * Report back to the Boot Processor during boot time or to the caller processor
 152  * during CPU online.
 153  */
 154 static void smp_callin(void)
 155 {
 156         int cpuid;
 157 
 158         /*
 159          * If waken up by an INIT in an 82489DX configuration
 160          * cpu_callout_mask guarantees we don't get here before
 161          * an INIT_deassert IPI reaches our local APIC, so it is
 162          * now safe to touch our local APIC.
 163          */
 164         cpuid = smp_processor_id();
 165 
 166         /*
 167          * the boot CPU has finished the init stage and is spinning
 168          * on callin_map until we finish. We are free to set up this
 169          * CPU, first the APIC. (this is probably redundant on most
 170          * boards)
 171          */
 172         apic_ap_setup();
 173 
 174         /*
 175          * Save our processor parameters. Note: this information
 176          * is needed for clock calibration.
 177          */
 178         smp_store_cpu_info(cpuid);
 179 
 180         /*
 181          * The topology information must be up to date before
 182          * calibrate_delay() and notify_cpu_starting().
 183          */
 184         set_cpu_sibling_map(raw_smp_processor_id());
 185 
 186         /*
 187          * Get our bogomips.
 188          * Update loops_per_jiffy in cpu_data. Previous call to
 189          * smp_store_cpu_info() stored a value that is close but not as
 190          * accurate as the value just calculated.
 191          */
 192         calibrate_delay();
 193         cpu_data(cpuid).loops_per_jiffy = loops_per_jiffy;
 194         pr_debug("Stack at about %p\n", &cpuid);
 195 
 196         wmb();
 197 
 198         notify_cpu_starting(cpuid);
 199 
 200         /*
 201          * Allow the master to continue.
 202          */
 203         cpumask_set_cpu(cpuid, cpu_callin_mask);
 204 }
 205 
 206 static int cpu0_logical_apicid;
 207 static int enable_start_cpu0;
 208 /*
 209  * Activate a secondary processor.
 210  */
 211 static void notrace start_secondary(void *unused)
 212 {
 213         /*
 214          * Don't put *anything* except direct CPU state initialization
 215          * before cpu_init(), SMP booting is too fragile that we want to
 216          * limit the things done here to the most necessary things.
 217          */
 218         cr4_init();
 219 
 220 #ifdef CONFIG_X86_32
 221         /* switch away from the initial page table */
 222         load_cr3(swapper_pg_dir);
 223         __flush_tlb_all();
 224 #endif
 225         load_current_idt();
 226         cpu_init();
 227         x86_cpuinit.early_percpu_clock_init();
 228         preempt_disable();
 229         smp_callin();
 230 
 231         enable_start_cpu0 = 0;
 232 
 233         /* otherwise gcc will move up smp_processor_id before the cpu_init */
 234         barrier();
 235         /*
 236          * Check TSC synchronization with the boot CPU:
 237          */
 238         check_tsc_sync_target();
 239 
 240         speculative_store_bypass_ht_init();
 241 
 242         /*
 243          * Lock vector_lock, set CPU online and bring the vector
 244          * allocator online. Online must be set with vector_lock held
 245          * to prevent a concurrent irq setup/teardown from seeing a
 246          * half valid vector space.
 247          */
 248         lock_vector_lock();
 249         set_cpu_online(smp_processor_id(), true);
 250         lapic_online();
 251         unlock_vector_lock();
 252         cpu_set_state_online(smp_processor_id());
 253         x86_platform.nmi_init();
 254 
 255         /* enable local interrupts */
 256         local_irq_enable();
 257 
 258         /* to prevent fake stack check failure in clock setup */
 259         boot_init_stack_canary();
 260 
 261         x86_cpuinit.setup_percpu_clockev();
 262 
 263         wmb();
 264         cpu_startup_entry(CPUHP_AP_ONLINE_IDLE);
 265 
 266         /*
 267          * Prevent tail call to cpu_startup_entry() because the stack protector
 268          * guard has been changed a couple of function calls up, in
 269          * boot_init_stack_canary() and must not be checked before tail calling
 270          * another function.
 271          */
 272         prevent_tail_call_optimization();
 273 }
 274 
 275 /**
 276  * topology_is_primary_thread - Check whether CPU is the primary SMT thread
 277  * @cpu:        CPU to check
 278  */
 279 bool topology_is_primary_thread(unsigned int cpu)
 280 {
 281         return apic_id_is_primary_thread(per_cpu(x86_cpu_to_apicid, cpu));
 282 }
 283 
 284 /**
 285  * topology_smt_supported - Check whether SMT is supported by the CPUs
 286  */
 287 bool topology_smt_supported(void)
 288 {
 289         return smp_num_siblings > 1;
 290 }
 291 
 292 /**
 293  * topology_phys_to_logical_pkg - Map a physical package id to a logical
 294  *
 295  * Returns logical package id or -1 if not found
 296  */
 297 int topology_phys_to_logical_pkg(unsigned int phys_pkg)
 298 {
 299         int cpu;
 300 
 301         for_each_possible_cpu(cpu) {
 302                 struct cpuinfo_x86 *c = &cpu_data(cpu);
 303 
 304                 if (c->initialized && c->phys_proc_id == phys_pkg)
 305                         return c->logical_proc_id;
 306         }
 307         return -1;
 308 }
 309 EXPORT_SYMBOL(topology_phys_to_logical_pkg);
 310 /**
 311  * topology_phys_to_logical_die - Map a physical die id to logical
 312  *
 313  * Returns logical die id or -1 if not found
 314  */
 315 int topology_phys_to_logical_die(unsigned int die_id, unsigned int cur_cpu)
 316 {
 317         int cpu;
 318         int proc_id = cpu_data(cur_cpu).phys_proc_id;
 319 
 320         for_each_possible_cpu(cpu) {
 321                 struct cpuinfo_x86 *c = &cpu_data(cpu);
 322 
 323                 if (c->initialized && c->cpu_die_id == die_id &&
 324                     c->phys_proc_id == proc_id)
 325                         return c->logical_die_id;
 326         }
 327         return -1;
 328 }
 329 EXPORT_SYMBOL(topology_phys_to_logical_die);
 330 
 331 /**
 332  * topology_update_package_map - Update the physical to logical package map
 333  * @pkg:        The physical package id as retrieved via CPUID
 334  * @cpu:        The cpu for which this is updated
 335  */
 336 int topology_update_package_map(unsigned int pkg, unsigned int cpu)
 337 {
 338         int new;
 339 
 340         /* Already available somewhere? */
 341         new = topology_phys_to_logical_pkg(pkg);
 342         if (new >= 0)
 343                 goto found;
 344 
 345         new = logical_packages++;
 346         if (new != pkg) {
 347                 pr_info("CPU %u Converting physical %u to logical package %u\n",
 348                         cpu, pkg, new);
 349         }
 350 found:
 351         cpu_data(cpu).logical_proc_id = new;
 352         return 0;
 353 }
 354 /**
 355  * topology_update_die_map - Update the physical to logical die map
 356  * @die:        The die id as retrieved via CPUID
 357  * @cpu:        The cpu for which this is updated
 358  */
 359 int topology_update_die_map(unsigned int die, unsigned int cpu)
 360 {
 361         int new;
 362 
 363         /* Already available somewhere? */
 364         new = topology_phys_to_logical_die(die, cpu);
 365         if (new >= 0)
 366                 goto found;
 367 
 368         new = logical_die++;
 369         if (new != die) {
 370                 pr_info("CPU %u Converting physical %u to logical die %u\n",
 371                         cpu, die, new);
 372         }
 373 found:
 374         cpu_data(cpu).logical_die_id = new;
 375         return 0;
 376 }
 377 
 378 void __init smp_store_boot_cpu_info(void)
 379 {
 380         int id = 0; /* CPU 0 */
 381         struct cpuinfo_x86 *c = &cpu_data(id);
 382 
 383         *c = boot_cpu_data;
 384         c->cpu_index = id;
 385         topology_update_package_map(c->phys_proc_id, id);
 386         topology_update_die_map(c->cpu_die_id, id);
 387         c->initialized = true;
 388 }
 389 
 390 /*
 391  * The bootstrap kernel entry code has set these up. Save them for
 392  * a given CPU
 393  */
 394 void smp_store_cpu_info(int id)
 395 {
 396         struct cpuinfo_x86 *c = &cpu_data(id);
 397 
 398         /* Copy boot_cpu_data only on the first bringup */
 399         if (!c->initialized)
 400                 *c = boot_cpu_data;
 401         c->cpu_index = id;
 402         /*
 403          * During boot time, CPU0 has this setup already. Save the info when
 404          * bringing up AP or offlined CPU0.
 405          */
 406         identify_secondary_cpu(c);
 407         c->initialized = true;
 408 }
 409 
 410 static bool
 411 topology_same_node(struct cpuinfo_x86 *c, struct cpuinfo_x86 *o)
 412 {
 413         int cpu1 = c->cpu_index, cpu2 = o->cpu_index;
 414 
 415         return (cpu_to_node(cpu1) == cpu_to_node(cpu2));
 416 }
 417 
 418 static bool
 419 topology_sane(struct cpuinfo_x86 *c, struct cpuinfo_x86 *o, const char *name)
 420 {
 421         int cpu1 = c->cpu_index, cpu2 = o->cpu_index;
 422 
 423         return !WARN_ONCE(!topology_same_node(c, o),
 424                 "sched: CPU #%d's %s-sibling CPU #%d is not on the same node! "
 425                 "[node: %d != %d]. Ignoring dependency.\n",
 426                 cpu1, name, cpu2, cpu_to_node(cpu1), cpu_to_node(cpu2));
 427 }
 428 
 429 #define link_mask(mfunc, c1, c2)                                        \
 430 do {                                                                    \
 431         cpumask_set_cpu((c1), mfunc(c2));                               \
 432         cpumask_set_cpu((c2), mfunc(c1));                               \
 433 } while (0)
 434 
 435 static bool match_smt(struct cpuinfo_x86 *c, struct cpuinfo_x86 *o)
 436 {
 437         if (boot_cpu_has(X86_FEATURE_TOPOEXT)) {
 438                 int cpu1 = c->cpu_index, cpu2 = o->cpu_index;
 439 
 440                 if (c->phys_proc_id == o->phys_proc_id &&
 441                     c->cpu_die_id == o->cpu_die_id &&
 442                     per_cpu(cpu_llc_id, cpu1) == per_cpu(cpu_llc_id, cpu2)) {
 443                         if (c->cpu_core_id == o->cpu_core_id)
 444                                 return topology_sane(c, o, "smt");
 445 
 446                         if ((c->cu_id != 0xff) &&
 447                             (o->cu_id != 0xff) &&
 448                             (c->cu_id == o->cu_id))
 449                                 return topology_sane(c, o, "smt");
 450                 }
 451 
 452         } else if (c->phys_proc_id == o->phys_proc_id &&
 453                    c->cpu_die_id == o->cpu_die_id &&
 454                    c->cpu_core_id == o->cpu_core_id) {
 455                 return topology_sane(c, o, "smt");
 456         }
 457 
 458         return false;
 459 }
 460 
 461 /*
 462  * Define snc_cpu[] for SNC (Sub-NUMA Cluster) CPUs.
 463  *
 464  * These are Intel CPUs that enumerate an LLC that is shared by
 465  * multiple NUMA nodes. The LLC on these systems is shared for
 466  * off-package data access but private to the NUMA node (half
 467  * of the package) for on-package access.
 468  *
 469  * CPUID (the source of the information about the LLC) can only
 470  * enumerate the cache as being shared *or* unshared, but not
 471  * this particular configuration. The CPU in this case enumerates
 472  * the cache to be shared across the entire package (spanning both
 473  * NUMA nodes).
 474  */
 475 
 476 static const struct x86_cpu_id snc_cpu[] = {
 477         { X86_VENDOR_INTEL, 6, INTEL_FAM6_SKYLAKE_X },
 478         {}
 479 };
 480 
 481 static bool match_llc(struct cpuinfo_x86 *c, struct cpuinfo_x86 *o)
 482 {
 483         int cpu1 = c->cpu_index, cpu2 = o->cpu_index;
 484 
 485         /* Do not match if we do not have a valid APICID for cpu: */
 486         if (per_cpu(cpu_llc_id, cpu1) == BAD_APICID)
 487                 return false;
 488 
 489         /* Do not match if LLC id does not match: */
 490         if (per_cpu(cpu_llc_id, cpu1) != per_cpu(cpu_llc_id, cpu2))
 491                 return false;
 492 
 493         /*
 494          * Allow the SNC topology without warning. Return of false
 495          * means 'c' does not share the LLC of 'o'. This will be
 496          * reflected to userspace.
 497          */
 498         if (!topology_same_node(c, o) && x86_match_cpu(snc_cpu))
 499                 return false;
 500 
 501         return topology_sane(c, o, "llc");
 502 }
 503 
 504 /*
 505  * Unlike the other levels, we do not enforce keeping a
 506  * multicore group inside a NUMA node.  If this happens, we will
 507  * discard the MC level of the topology later.
 508  */
 509 static bool match_pkg(struct cpuinfo_x86 *c, struct cpuinfo_x86 *o)
 510 {
 511         if (c->phys_proc_id == o->phys_proc_id)
 512                 return true;
 513         return false;
 514 }
 515 
 516 static bool match_die(struct cpuinfo_x86 *c, struct cpuinfo_x86 *o)
 517 {
 518         if ((c->phys_proc_id == o->phys_proc_id) &&
 519                 (c->cpu_die_id == o->cpu_die_id))
 520                 return true;
 521         return false;
 522 }
 523 
 524 
 525 #if defined(CONFIG_SCHED_SMT) || defined(CONFIG_SCHED_MC)
 526 static inline int x86_sched_itmt_flags(void)
 527 {
 528         return sysctl_sched_itmt_enabled ? SD_ASYM_PACKING : 0;
 529 }
 530 
 531 #ifdef CONFIG_SCHED_MC
 532 static int x86_core_flags(void)
 533 {
 534         return cpu_core_flags() | x86_sched_itmt_flags();
 535 }
 536 #endif
 537 #ifdef CONFIG_SCHED_SMT
 538 static int x86_smt_flags(void)
 539 {
 540         return cpu_smt_flags() | x86_sched_itmt_flags();
 541 }
 542 #endif
 543 #endif
 544 
 545 static struct sched_domain_topology_level x86_numa_in_package_topology[] = {
 546 #ifdef CONFIG_SCHED_SMT
 547         { cpu_smt_mask, x86_smt_flags, SD_INIT_NAME(SMT) },
 548 #endif
 549 #ifdef CONFIG_SCHED_MC
 550         { cpu_coregroup_mask, x86_core_flags, SD_INIT_NAME(MC) },
 551 #endif
 552         { NULL, },
 553 };
 554 
 555 static struct sched_domain_topology_level x86_topology[] = {
 556 #ifdef CONFIG_SCHED_SMT
 557         { cpu_smt_mask, x86_smt_flags, SD_INIT_NAME(SMT) },
 558 #endif
 559 #ifdef CONFIG_SCHED_MC
 560         { cpu_coregroup_mask, x86_core_flags, SD_INIT_NAME(MC) },
 561 #endif
 562         { cpu_cpu_mask, SD_INIT_NAME(DIE) },
 563         { NULL, },
 564 };
 565 
 566 /*
 567  * Set if a package/die has multiple NUMA nodes inside.
 568  * AMD Magny-Cours, Intel Cluster-on-Die, and Intel
 569  * Sub-NUMA Clustering have this.
 570  */
 571 static bool x86_has_numa_in_package;
 572 
 573 void set_cpu_sibling_map(int cpu)
 574 {
 575         bool has_smt = smp_num_siblings > 1;
 576         bool has_mp = has_smt || boot_cpu_data.x86_max_cores > 1;
 577         struct cpuinfo_x86 *c = &cpu_data(cpu);
 578         struct cpuinfo_x86 *o;
 579         int i, threads;
 580 
 581         cpumask_set_cpu(cpu, cpu_sibling_setup_mask);
 582 
 583         if (!has_mp) {
 584                 cpumask_set_cpu(cpu, topology_sibling_cpumask(cpu));
 585                 cpumask_set_cpu(cpu, cpu_llc_shared_mask(cpu));
 586                 cpumask_set_cpu(cpu, topology_core_cpumask(cpu));
 587                 cpumask_set_cpu(cpu, topology_die_cpumask(cpu));
 588                 c->booted_cores = 1;
 589                 return;
 590         }
 591 
 592         for_each_cpu(i, cpu_sibling_setup_mask) {
 593                 o = &cpu_data(i);
 594 
 595                 if ((i == cpu) || (has_smt && match_smt(c, o)))
 596                         link_mask(topology_sibling_cpumask, cpu, i);
 597 
 598                 if ((i == cpu) || (has_mp && match_llc(c, o)))
 599                         link_mask(cpu_llc_shared_mask, cpu, i);
 600 
 601         }
 602 
 603         /*
 604          * This needs a separate iteration over the cpus because we rely on all
 605          * topology_sibling_cpumask links to be set-up.
 606          */
 607         for_each_cpu(i, cpu_sibling_setup_mask) {
 608                 o = &cpu_data(i);
 609 
 610                 if ((i == cpu) || (has_mp && match_pkg(c, o))) {
 611                         link_mask(topology_core_cpumask, cpu, i);
 612 
 613                         /*
 614                          *  Does this new cpu bringup a new core?
 615                          */
 616                         if (cpumask_weight(
 617                             topology_sibling_cpumask(cpu)) == 1) {
 618                                 /*
 619                                  * for each core in package, increment
 620                                  * the booted_cores for this new cpu
 621                                  */
 622                                 if (cpumask_first(
 623                                     topology_sibling_cpumask(i)) == i)
 624                                         c->booted_cores++;
 625                                 /*
 626                                  * increment the core count for all
 627                                  * the other cpus in this package
 628                                  */
 629                                 if (i != cpu)
 630                                         cpu_data(i).booted_cores++;
 631                         } else if (i != cpu && !c->booted_cores)
 632                                 c->booted_cores = cpu_data(i).booted_cores;
 633                 }
 634                 if (match_pkg(c, o) && !topology_same_node(c, o))
 635                         x86_has_numa_in_package = true;
 636 
 637                 if ((i == cpu) || (has_mp && match_die(c, o)))
 638                         link_mask(topology_die_cpumask, cpu, i);
 639         }
 640 
 641         threads = cpumask_weight(topology_sibling_cpumask(cpu));
 642         if (threads > __max_smt_threads)
 643                 __max_smt_threads = threads;
 644 }
 645 
 646 /* maps the cpu to the sched domain representing multi-core */
 647 const struct cpumask *cpu_coregroup_mask(int cpu)
 648 {
 649         return cpu_llc_shared_mask(cpu);
 650 }
 651 
 652 static void impress_friends(void)
 653 {
 654         int cpu;
 655         unsigned long bogosum = 0;
 656         /*
 657          * Allow the user to impress friends.
 658          */
 659         pr_debug("Before bogomips\n");
 660         for_each_possible_cpu(cpu)
 661                 if (cpumask_test_cpu(cpu, cpu_callout_mask))
 662                         bogosum += cpu_data(cpu).loops_per_jiffy;
 663         pr_info("Total of %d processors activated (%lu.%02lu BogoMIPS)\n",
 664                 num_online_cpus(),
 665                 bogosum/(500000/HZ),
 666                 (bogosum/(5000/HZ))%100);
 667 
 668         pr_debug("Before bogocount - setting activated=1\n");
 669 }
 670 
 671 void __inquire_remote_apic(int apicid)
 672 {
 673         unsigned i, regs[] = { APIC_ID >> 4, APIC_LVR >> 4, APIC_SPIV >> 4 };
 674         const char * const names[] = { "ID", "VERSION", "SPIV" };
 675         int timeout;
 676         u32 status;
 677 
 678         pr_info("Inquiring remote APIC 0x%x...\n", apicid);
 679 
 680         for (i = 0; i < ARRAY_SIZE(regs); i++) {
 681                 pr_info("... APIC 0x%x %s: ", apicid, names[i]);
 682 
 683                 /*
 684                  * Wait for idle.
 685                  */
 686                 status = safe_apic_wait_icr_idle();
 687                 if (status)
 688                         pr_cont("a previous APIC delivery may have failed\n");
 689 
 690                 apic_icr_write(APIC_DM_REMRD | regs[i], apicid);
 691 
 692                 timeout = 0;
 693                 do {
 694                         udelay(100);
 695                         status = apic_read(APIC_ICR) & APIC_ICR_RR_MASK;
 696                 } while (status == APIC_ICR_RR_INPROG && timeout++ < 1000);
 697 
 698                 switch (status) {
 699                 case APIC_ICR_RR_VALID:
 700                         status = apic_read(APIC_RRR);
 701                         pr_cont("%08x\n", status);
 702                         break;
 703                 default:
 704                         pr_cont("failed\n");
 705                 }
 706         }
 707 }
 708 
 709 /*
 710  * The Multiprocessor Specification 1.4 (1997) example code suggests
 711  * that there should be a 10ms delay between the BSP asserting INIT
 712  * and de-asserting INIT, when starting a remote processor.
 713  * But that slows boot and resume on modern processors, which include
 714  * many cores and don't require that delay.
 715  *
 716  * Cmdline "init_cpu_udelay=" is available to over-ride this delay.
 717  * Modern processor families are quirked to remove the delay entirely.
 718  */
 719 #define UDELAY_10MS_DEFAULT 10000
 720 
 721 static unsigned int init_udelay = UINT_MAX;
 722 
 723 static int __init cpu_init_udelay(char *str)
 724 {
 725         get_option(&str, &init_udelay);
 726 
 727         return 0;
 728 }
 729 early_param("cpu_init_udelay", cpu_init_udelay);
 730 
 731 static void __init smp_quirk_init_udelay(void)
 732 {
 733         /* if cmdline changed it from default, leave it alone */
 734         if (init_udelay != UINT_MAX)
 735                 return;
 736 
 737         /* if modern processor, use no delay */
 738         if (((boot_cpu_data.x86_vendor == X86_VENDOR_INTEL) && (boot_cpu_data.x86 == 6)) ||
 739             ((boot_cpu_data.x86_vendor == X86_VENDOR_HYGON) && (boot_cpu_data.x86 >= 0x18)) ||
 740             ((boot_cpu_data.x86_vendor == X86_VENDOR_AMD) && (boot_cpu_data.x86 >= 0xF))) {
 741                 init_udelay = 0;
 742                 return;
 743         }
 744         /* else, use legacy delay */
 745         init_udelay = UDELAY_10MS_DEFAULT;
 746 }
 747 
 748 /*
 749  * Poke the other CPU in the eye via NMI to wake it up. Remember that the normal
 750  * INIT, INIT, STARTUP sequence will reset the chip hard for us, and this
 751  * won't ... remember to clear down the APIC, etc later.
 752  */
 753 int
 754 wakeup_secondary_cpu_via_nmi(int apicid, unsigned long start_eip)
 755 {
 756         unsigned long send_status, accept_status = 0;
 757         int maxlvt;
 758 
 759         /* Target chip */
 760         /* Boot on the stack */
 761         /* Kick the second */
 762         apic_icr_write(APIC_DM_NMI | apic->dest_logical, apicid);
 763 
 764         pr_debug("Waiting for send to finish...\n");
 765         send_status = safe_apic_wait_icr_idle();
 766 
 767         /*
 768          * Give the other CPU some time to accept the IPI.
 769          */
 770         udelay(200);
 771         if (APIC_INTEGRATED(boot_cpu_apic_version)) {
 772                 maxlvt = lapic_get_maxlvt();
 773                 if (maxlvt > 3)                 /* Due to the Pentium erratum 3AP.  */
 774                         apic_write(APIC_ESR, 0);
 775                 accept_status = (apic_read(APIC_ESR) & 0xEF);
 776         }
 777         pr_debug("NMI sent\n");
 778 
 779         if (send_status)
 780                 pr_err("APIC never delivered???\n");
 781         if (accept_status)
 782                 pr_err("APIC delivery error (%lx)\n", accept_status);
 783 
 784         return (send_status | accept_status);
 785 }
 786 
 787 static int
 788 wakeup_secondary_cpu_via_init(int phys_apicid, unsigned long start_eip)
 789 {
 790         unsigned long send_status = 0, accept_status = 0;
 791         int maxlvt, num_starts, j;
 792 
 793         maxlvt = lapic_get_maxlvt();
 794 
 795         /*
 796          * Be paranoid about clearing APIC errors.
 797          */
 798         if (APIC_INTEGRATED(boot_cpu_apic_version)) {
 799                 if (maxlvt > 3)         /* Due to the Pentium erratum 3AP.  */
 800                         apic_write(APIC_ESR, 0);
 801                 apic_read(APIC_ESR);
 802         }
 803 
 804         pr_debug("Asserting INIT\n");
 805 
 806         /*
 807          * Turn INIT on target chip
 808          */
 809         /*
 810          * Send IPI
 811          */
 812         apic_icr_write(APIC_INT_LEVELTRIG | APIC_INT_ASSERT | APIC_DM_INIT,
 813                        phys_apicid);
 814 
 815         pr_debug("Waiting for send to finish...\n");
 816         send_status = safe_apic_wait_icr_idle();
 817 
 818         udelay(init_udelay);
 819 
 820         pr_debug("Deasserting INIT\n");
 821 
 822         /* Target chip */
 823         /* Send IPI */
 824         apic_icr_write(APIC_INT_LEVELTRIG | APIC_DM_INIT, phys_apicid);
 825 
 826         pr_debug("Waiting for send to finish...\n");
 827         send_status = safe_apic_wait_icr_idle();
 828 
 829         mb();
 830 
 831         /*
 832          * Should we send STARTUP IPIs ?
 833          *
 834          * Determine this based on the APIC version.
 835          * If we don't have an integrated APIC, don't send the STARTUP IPIs.
 836          */
 837         if (APIC_INTEGRATED(boot_cpu_apic_version))
 838                 num_starts = 2;
 839         else
 840                 num_starts = 0;
 841 
 842         /*
 843          * Run STARTUP IPI loop.
 844          */
 845         pr_debug("#startup loops: %d\n", num_starts);
 846 
 847         for (j = 1; j <= num_starts; j++) {
 848                 pr_debug("Sending STARTUP #%d\n", j);
 849                 if (maxlvt > 3)         /* Due to the Pentium erratum 3AP.  */
 850                         apic_write(APIC_ESR, 0);
 851                 apic_read(APIC_ESR);
 852                 pr_debug("After apic_write\n");
 853 
 854                 /*
 855                  * STARTUP IPI
 856                  */
 857 
 858                 /* Target chip */
 859                 /* Boot on the stack */
 860                 /* Kick the second */
 861                 apic_icr_write(APIC_DM_STARTUP | (start_eip >> 12),
 862                                phys_apicid);
 863 
 864                 /*
 865                  * Give the other CPU some time to accept the IPI.
 866                  */
 867                 if (init_udelay == 0)
 868                         udelay(10);
 869                 else
 870                         udelay(300);
 871 
 872                 pr_debug("Startup point 1\n");
 873 
 874                 pr_debug("Waiting for send to finish...\n");
 875                 send_status = safe_apic_wait_icr_idle();
 876 
 877                 /*
 878                  * Give the other CPU some time to accept the IPI.
 879                  */
 880                 if (init_udelay == 0)
 881                         udelay(10);
 882                 else
 883                         udelay(200);
 884 
 885                 if (maxlvt > 3)         /* Due to the Pentium erratum 3AP.  */
 886                         apic_write(APIC_ESR, 0);
 887                 accept_status = (apic_read(APIC_ESR) & 0xEF);
 888                 if (send_status || accept_status)
 889                         break;
 890         }
 891         pr_debug("After Startup\n");
 892 
 893         if (send_status)
 894                 pr_err("APIC never delivered???\n");
 895         if (accept_status)
 896                 pr_err("APIC delivery error (%lx)\n", accept_status);
 897 
 898         return (send_status | accept_status);
 899 }
 900 
 901 /* reduce the number of lines printed when booting a large cpu count system */
 902 static void announce_cpu(int cpu, int apicid)
 903 {
 904         static int current_node = NUMA_NO_NODE;
 905         int node = early_cpu_to_node(cpu);
 906         static int width, node_width;
 907 
 908         if (!width)
 909                 width = num_digits(num_possible_cpus()) + 1; /* + '#' sign */
 910 
 911         if (!node_width)
 912                 node_width = num_digits(num_possible_nodes()) + 1; /* + '#' */
 913 
 914         if (cpu == 1)
 915                 printk(KERN_INFO "x86: Booting SMP configuration:\n");
 916 
 917         if (system_state < SYSTEM_RUNNING) {
 918                 if (node != current_node) {
 919                         if (current_node > (-1))
 920                                 pr_cont("\n");
 921                         current_node = node;
 922 
 923                         printk(KERN_INFO ".... node %*s#%d, CPUs:  ",
 924                                node_width - num_digits(node), " ", node);
 925                 }
 926 
 927                 /* Add padding for the BSP */
 928                 if (cpu == 1)
 929                         pr_cont("%*s", width + 1, " ");
 930 
 931                 pr_cont("%*s#%d", width - num_digits(cpu), " ", cpu);
 932 
 933         } else
 934                 pr_info("Booting Node %d Processor %d APIC 0x%x\n",
 935                         node, cpu, apicid);
 936 }
 937 
 938 static int wakeup_cpu0_nmi(unsigned int cmd, struct pt_regs *regs)
 939 {
 940         int cpu;
 941 
 942         cpu = smp_processor_id();
 943         if (cpu == 0 && !cpu_online(cpu) && enable_start_cpu0)
 944                 return NMI_HANDLED;
 945 
 946         return NMI_DONE;
 947 }
 948 
 949 /*
 950  * Wake up AP by INIT, INIT, STARTUP sequence.
 951  *
 952  * Instead of waiting for STARTUP after INITs, BSP will execute the BIOS
 953  * boot-strap code which is not a desired behavior for waking up BSP. To
 954  * void the boot-strap code, wake up CPU0 by NMI instead.
 955  *
 956  * This works to wake up soft offlined CPU0 only. If CPU0 is hard offlined
 957  * (i.e. physically hot removed and then hot added), NMI won't wake it up.
 958  * We'll change this code in the future to wake up hard offlined CPU0 if
 959  * real platform and request are available.
 960  */
 961 static int
 962 wakeup_cpu_via_init_nmi(int cpu, unsigned long start_ip, int apicid,
 963                int *cpu0_nmi_registered)
 964 {
 965         int id;
 966         int boot_error;
 967 
 968         preempt_disable();
 969 
 970         /*
 971          * Wake up AP by INIT, INIT, STARTUP sequence.
 972          */
 973         if (cpu) {
 974                 boot_error = wakeup_secondary_cpu_via_init(apicid, start_ip);
 975                 goto out;
 976         }
 977 
 978         /*
 979          * Wake up BSP by nmi.
 980          *
 981          * Register a NMI handler to help wake up CPU0.
 982          */
 983         boot_error = register_nmi_handler(NMI_LOCAL,
 984                                           wakeup_cpu0_nmi, 0, "wake_cpu0");
 985 
 986         if (!boot_error) {
 987                 enable_start_cpu0 = 1;
 988                 *cpu0_nmi_registered = 1;
 989                 if (apic->dest_logical == APIC_DEST_LOGICAL)
 990                         id = cpu0_logical_apicid;
 991                 else
 992                         id = apicid;
 993                 boot_error = wakeup_secondary_cpu_via_nmi(id, start_ip);
 994         }
 995 
 996 out:
 997         preempt_enable();
 998 
 999         return boot_error;
1000 }
1001 
1002 int common_cpu_up(unsigned int cpu, struct task_struct *idle)
1003 {
1004         int ret;
1005 
1006         /* Just in case we booted with a single CPU. */
1007         alternatives_enable_smp();
1008 
1009         per_cpu(current_task, cpu) = idle;
1010 
1011         /* Initialize the interrupt stack(s) */
1012         ret = irq_init_percpu_irqstack(cpu);
1013         if (ret)
1014                 return ret;
1015 
1016 #ifdef CONFIG_X86_32
1017         /* Stack for startup_32 can be just as for start_secondary onwards */
1018         per_cpu(cpu_current_top_of_stack, cpu) = task_top_of_stack(idle);
1019 #else
1020         initial_gs = per_cpu_offset(cpu);
1021 #endif
1022         return 0;
1023 }
1024 
1025 /*
1026  * NOTE - on most systems this is a PHYSICAL apic ID, but on multiquad
1027  * (ie clustered apic addressing mode), this is a LOGICAL apic ID.
1028  * Returns zero if CPU booted OK, else error code from
1029  * ->wakeup_secondary_cpu.
1030  */
1031 static int do_boot_cpu(int apicid, int cpu, struct task_struct *idle,
1032                        int *cpu0_nmi_registered)
1033 {
1034         /* start_ip had better be page-aligned! */
1035         unsigned long start_ip = real_mode_header->trampoline_start;
1036 
1037         unsigned long boot_error = 0;
1038         unsigned long timeout;
1039 
1040         idle->thread.sp = (unsigned long)task_pt_regs(idle);
1041         early_gdt_descr.address = (unsigned long)get_cpu_gdt_rw(cpu);
1042         initial_code = (unsigned long)start_secondary;
1043         initial_stack  = idle->thread.sp;
1044 
1045         /* Enable the espfix hack for this CPU */
1046         init_espfix_ap(cpu);
1047 
1048         /* So we see what's up */
1049         announce_cpu(cpu, apicid);
1050 
1051         /*
1052          * This grunge runs the startup process for
1053          * the targeted processor.
1054          */
1055 
1056         if (x86_platform.legacy.warm_reset) {
1057 
1058                 pr_debug("Setting warm reset code and vector.\n");
1059 
1060                 smpboot_setup_warm_reset_vector(start_ip);
1061                 /*
1062                  * Be paranoid about clearing APIC errors.
1063                 */
1064                 if (APIC_INTEGRATED(boot_cpu_apic_version)) {
1065                         apic_write(APIC_ESR, 0);
1066                         apic_read(APIC_ESR);
1067                 }
1068         }
1069 
1070         /*
1071          * AP might wait on cpu_callout_mask in cpu_init() with
1072          * cpu_initialized_mask set if previous attempt to online
1073          * it timed-out. Clear cpu_initialized_mask so that after
1074          * INIT/SIPI it could start with a clean state.
1075          */
1076         cpumask_clear_cpu(cpu, cpu_initialized_mask);
1077         smp_mb();
1078 
1079         /*
1080          * Wake up a CPU in difference cases:
1081          * - Use the method in the APIC driver if it's defined
1082          * Otherwise,
1083          * - Use an INIT boot APIC message for APs or NMI for BSP.
1084          */
1085         if (apic->wakeup_secondary_cpu)
1086                 boot_error = apic->wakeup_secondary_cpu(apicid, start_ip);
1087         else
1088                 boot_error = wakeup_cpu_via_init_nmi(cpu, start_ip, apicid,
1089                                                      cpu0_nmi_registered);
1090 
1091         if (!boot_error) {
1092                 /*
1093                  * Wait 10s total for first sign of life from AP
1094                  */
1095                 boot_error = -1;
1096                 timeout = jiffies + 10*HZ;
1097                 while (time_before(jiffies, timeout)) {
1098                         if (cpumask_test_cpu(cpu, cpu_initialized_mask)) {
1099                                 /*
1100                                  * Tell AP to proceed with initialization
1101                                  */
1102                                 cpumask_set_cpu(cpu, cpu_callout_mask);
1103                                 boot_error = 0;
1104                                 break;
1105                         }
1106                         schedule();
1107                 }
1108         }
1109 
1110         if (!boot_error) {
1111                 /*
1112                  * Wait till AP completes initial initialization
1113                  */
1114                 while (!cpumask_test_cpu(cpu, cpu_callin_mask)) {
1115                         /*
1116                          * Allow other tasks to run while we wait for the
1117                          * AP to come online. This also gives a chance
1118                          * for the MTRR work(triggered by the AP coming online)
1119                          * to be completed in the stop machine context.
1120                          */
1121                         schedule();
1122                 }
1123         }
1124 
1125         if (x86_platform.legacy.warm_reset) {
1126                 /*
1127                  * Cleanup possible dangling ends...
1128                  */
1129                 smpboot_restore_warm_reset_vector();
1130         }
1131 
1132         return boot_error;
1133 }
1134 
1135 int native_cpu_up(unsigned int cpu, struct task_struct *tidle)
1136 {
1137         int apicid = apic->cpu_present_to_apicid(cpu);
1138         int cpu0_nmi_registered = 0;
1139         unsigned long flags;
1140         int err, ret = 0;
1141 
1142         lockdep_assert_irqs_enabled();
1143 
1144         pr_debug("++++++++++++++++++++=_---CPU UP  %u\n", cpu);
1145 
1146         if (apicid == BAD_APICID ||
1147             !physid_isset(apicid, phys_cpu_present_map) ||
1148             !apic->apic_id_valid(apicid)) {
1149                 pr_err("%s: bad cpu %d\n", __func__, cpu);
1150                 return -EINVAL;
1151         }
1152 
1153         /*
1154          * Already booted CPU?
1155          */
1156         if (cpumask_test_cpu(cpu, cpu_callin_mask)) {
1157                 pr_debug("do_boot_cpu %d Already started\n", cpu);
1158                 return -ENOSYS;
1159         }
1160 
1161         /*
1162          * Save current MTRR state in case it was changed since early boot
1163          * (e.g. by the ACPI SMI) to initialize new CPUs with MTRRs in sync:
1164          */
1165         mtrr_save_state();
1166 
1167         /* x86 CPUs take themselves offline, so delayed offline is OK. */
1168         err = cpu_check_up_prepare(cpu);
1169         if (err && err != -EBUSY)
1170                 return err;
1171 
1172         /* the FPU context is blank, nobody can own it */
1173         per_cpu(fpu_fpregs_owner_ctx, cpu) = NULL;
1174 
1175         err = common_cpu_up(cpu, tidle);
1176         if (err)
1177                 return err;
1178 
1179         err = do_boot_cpu(apicid, cpu, tidle, &cpu0_nmi_registered);
1180         if (err) {
1181                 pr_err("do_boot_cpu failed(%d) to wakeup CPU#%u\n", err, cpu);
1182                 ret = -EIO;
1183                 goto unreg_nmi;
1184         }
1185 
1186         /*
1187          * Check TSC synchronization with the AP (keep irqs disabled
1188          * while doing so):
1189          */
1190         local_irq_save(flags);
1191         check_tsc_sync_source(cpu);
1192         local_irq_restore(flags);
1193 
1194         while (!cpu_online(cpu)) {
1195                 cpu_relax();
1196                 touch_nmi_watchdog();
1197         }
1198 
1199 unreg_nmi:
1200         /*
1201          * Clean up the nmi handler. Do this after the callin and callout sync
1202          * to avoid impact of possible long unregister time.
1203          */
1204         if (cpu0_nmi_registered)
1205                 unregister_nmi_handler(NMI_LOCAL, "wake_cpu0");
1206 
1207         return ret;
1208 }
1209 
1210 /**
1211  * arch_disable_smp_support() - disables SMP support for x86 at runtime
1212  */
1213 void arch_disable_smp_support(void)
1214 {
1215         disable_ioapic_support();
1216 }
1217 
1218 /*
1219  * Fall back to non SMP mode after errors.
1220  *
1221  * RED-PEN audit/test this more. I bet there is more state messed up here.
1222  */
1223 static __init void disable_smp(void)
1224 {
1225         pr_info("SMP disabled\n");
1226 
1227         disable_ioapic_support();
1228 
1229         init_cpu_present(cpumask_of(0));
1230         init_cpu_possible(cpumask_of(0));
1231 
1232         if (smp_found_config)
1233                 physid_set_mask_of_physid(boot_cpu_physical_apicid, &phys_cpu_present_map);
1234         else
1235                 physid_set_mask_of_physid(0, &phys_cpu_present_map);
1236         cpumask_set_cpu(0, topology_sibling_cpumask(0));
1237         cpumask_set_cpu(0, topology_core_cpumask(0));
1238         cpumask_set_cpu(0, topology_die_cpumask(0));
1239 }
1240 
1241 /*
1242  * Various sanity checks.
1243  */
1244 static void __init smp_sanity_check(void)
1245 {
1246         preempt_disable();
1247 
1248 #if !defined(CONFIG_X86_BIGSMP) && defined(CONFIG_X86_32)
1249         if (def_to_bigsmp && nr_cpu_ids > 8) {
1250                 unsigned int cpu;
1251                 unsigned nr;
1252 
1253                 pr_warn("More than 8 CPUs detected - skipping them\n"
1254                         "Use CONFIG_X86_BIGSMP\n");
1255 
1256                 nr = 0;
1257                 for_each_present_cpu(cpu) {
1258                         if (nr >= 8)
1259                                 set_cpu_present(cpu, false);
1260                         nr++;
1261                 }
1262 
1263                 nr = 0;
1264                 for_each_possible_cpu(cpu) {
1265                         if (nr >= 8)
1266                                 set_cpu_possible(cpu, false);
1267                         nr++;
1268                 }
1269 
1270                 nr_cpu_ids = 8;
1271         }
1272 #endif
1273 
1274         if (!physid_isset(hard_smp_processor_id(), phys_cpu_present_map)) {
1275                 pr_warn("weird, boot CPU (#%d) not listed by the BIOS\n",
1276                         hard_smp_processor_id());
1277 
1278                 physid_set(hard_smp_processor_id(), phys_cpu_present_map);
1279         }
1280 
1281         /*
1282          * Should not be necessary because the MP table should list the boot
1283          * CPU too, but we do it for the sake of robustness anyway.
1284          */
1285         if (!apic->check_phys_apicid_present(boot_cpu_physical_apicid)) {
1286                 pr_notice("weird, boot CPU (#%d) not listed by the BIOS\n",
1287                           boot_cpu_physical_apicid);
1288                 physid_set(hard_smp_processor_id(), phys_cpu_present_map);
1289         }
1290         preempt_enable();
1291 }
1292 
1293 static void __init smp_cpu_index_default(void)
1294 {
1295         int i;
1296         struct cpuinfo_x86 *c;
1297 
1298         for_each_possible_cpu(i) {
1299                 c = &cpu_data(i);
1300                 /* mark all to hotplug */
1301                 c->cpu_index = nr_cpu_ids;
1302         }
1303 }
1304 
1305 static void __init smp_get_logical_apicid(void)
1306 {
1307         if (x2apic_mode)
1308                 cpu0_logical_apicid = apic_read(APIC_LDR);
1309         else
1310                 cpu0_logical_apicid = GET_APIC_LOGICAL_ID(apic_read(APIC_LDR));
1311 }
1312 
1313 /*
1314  * Prepare for SMP bootup.
1315  * @max_cpus: configured maximum number of CPUs, It is a legacy parameter
1316  *            for common interface support.
1317  */
1318 void __init native_smp_prepare_cpus(unsigned int max_cpus)
1319 {
1320         unsigned int i;
1321 
1322         smp_cpu_index_default();
1323 
1324         /*
1325          * Setup boot CPU information
1326          */
1327         smp_store_boot_cpu_info(); /* Final full version of the data */
1328         cpumask_copy(cpu_callin_mask, cpumask_of(0));
1329         mb();
1330 
1331         for_each_possible_cpu(i) {
1332                 zalloc_cpumask_var(&per_cpu(cpu_sibling_map, i), GFP_KERNEL);
1333                 zalloc_cpumask_var(&per_cpu(cpu_core_map, i), GFP_KERNEL);
1334                 zalloc_cpumask_var(&per_cpu(cpu_die_map, i), GFP_KERNEL);
1335                 zalloc_cpumask_var(&per_cpu(cpu_llc_shared_map, i), GFP_KERNEL);
1336         }
1337 
1338         /*
1339          * Set 'default' x86 topology, this matches default_topology() in that
1340          * it has NUMA nodes as a topology level. See also
1341          * native_smp_cpus_done().
1342          *
1343          * Must be done before set_cpus_sibling_map() is ran.
1344          */
1345         set_sched_topology(x86_topology);
1346 
1347         set_cpu_sibling_map(0);
1348 
1349         smp_sanity_check();
1350 
1351         switch (apic_intr_mode) {
1352         case APIC_PIC:
1353         case APIC_VIRTUAL_WIRE_NO_CONFIG:
1354                 disable_smp();
1355                 return;
1356         case APIC_SYMMETRIC_IO_NO_ROUTING:
1357                 disable_smp();
1358                 /* Setup local timer */
1359                 x86_init.timers.setup_percpu_clockev();
1360                 return;
1361         case APIC_VIRTUAL_WIRE:
1362         case APIC_SYMMETRIC_IO:
1363                 break;
1364         }
1365 
1366         /* Setup local timer */
1367         x86_init.timers.setup_percpu_clockev();
1368 
1369         smp_get_logical_apicid();
1370 
1371         pr_info("CPU0: ");
1372         print_cpu_info(&cpu_data(0));
1373 
1374         uv_system_init();
1375 
1376         set_mtrr_aps_delayed_init();
1377 
1378         smp_quirk_init_udelay();
1379 
1380         speculative_store_bypass_ht_init();
1381 }
1382 
1383 void arch_enable_nonboot_cpus_begin(void)
1384 {
1385         set_mtrr_aps_delayed_init();
1386 }
1387 
1388 void arch_enable_nonboot_cpus_end(void)
1389 {
1390         mtrr_aps_init();
1391 }
1392 
1393 /*
1394  * Early setup to make printk work.
1395  */
1396 void __init native_smp_prepare_boot_cpu(void)
1397 {
1398         int me = smp_processor_id();
1399         switch_to_new_gdt(me);
1400         /* already set me in cpu_online_mask in boot_cpu_init() */
1401         cpumask_set_cpu(me, cpu_callout_mask);
1402         cpu_set_state_online(me);
1403         native_pv_lock_init();
1404 }
1405 
1406 void __init calculate_max_logical_packages(void)
1407 {
1408         int ncpus;
1409 
1410         /*
1411          * Today neither Intel nor AMD support heterogenous systems so
1412          * extrapolate the boot cpu's data to all packages.
1413          */
1414         ncpus = cpu_data(0).booted_cores * topology_max_smt_threads();
1415         __max_logical_packages = DIV_ROUND_UP(total_cpus, ncpus);
1416         pr_info("Max logical packages: %u\n", __max_logical_packages);
1417 }
1418 
1419 void __init native_smp_cpus_done(unsigned int max_cpus)
1420 {
1421         pr_debug("Boot done\n");
1422 
1423         calculate_max_logical_packages();
1424 
1425         if (x86_has_numa_in_package)
1426                 set_sched_topology(x86_numa_in_package_topology);
1427 
1428         nmi_selftest();
1429         impress_friends();
1430         mtrr_aps_init();
1431 }
1432 
1433 static int __initdata setup_possible_cpus = -1;
1434 static int __init _setup_possible_cpus(char *str)
1435 {
1436         get_option(&str, &setup_possible_cpus);
1437         return 0;
1438 }
1439 early_param("possible_cpus", _setup_possible_cpus);
1440 
1441 
1442 /*
1443  * cpu_possible_mask should be static, it cannot change as cpu's
1444  * are onlined, or offlined. The reason is per-cpu data-structures
1445  * are allocated by some modules at init time, and dont expect to
1446  * do this dynamically on cpu arrival/departure.
1447  * cpu_present_mask on the other hand can change dynamically.
1448  * In case when cpu_hotplug is not compiled, then we resort to current
1449  * behaviour, which is cpu_possible == cpu_present.
1450  * - Ashok Raj
1451  *
1452  * Three ways to find out the number of additional hotplug CPUs:
1453  * - If the BIOS specified disabled CPUs in ACPI/mptables use that.
1454  * - The user can overwrite it with possible_cpus=NUM
1455  * - Otherwise don't reserve additional CPUs.
1456  * We do this because additional CPUs waste a lot of memory.
1457  * -AK
1458  */
1459 __init void prefill_possible_map(void)
1460 {
1461         int i, possible;
1462 
1463         /* No boot processor was found in mptable or ACPI MADT */
1464         if (!num_processors) {
1465                 if (boot_cpu_has(X86_FEATURE_APIC)) {
1466                         int apicid = boot_cpu_physical_apicid;
1467                         int cpu = hard_smp_processor_id();
1468 
1469                         pr_warn("Boot CPU (id %d) not listed by BIOS\n", cpu);
1470 
1471                         /* Make sure boot cpu is enumerated */
1472                         if (apic->cpu_present_to_apicid(0) == BAD_APICID &&
1473                             apic->apic_id_valid(apicid))
1474                                 generic_processor_info(apicid, boot_cpu_apic_version);
1475                 }
1476 
1477                 if (!num_processors)
1478                         num_processors = 1;
1479         }
1480 
1481         i = setup_max_cpus ?: 1;
1482         if (setup_possible_cpus == -1) {
1483                 possible = num_processors;
1484 #ifdef CONFIG_HOTPLUG_CPU
1485                 if (setup_max_cpus)
1486                         possible += disabled_cpus;
1487 #else
1488                 if (possible > i)
1489                         possible = i;
1490 #endif
1491         } else
1492                 possible = setup_possible_cpus;
1493 
1494         total_cpus = max_t(int, possible, num_processors + disabled_cpus);
1495 
1496         /* nr_cpu_ids could be reduced via nr_cpus= */
1497         if (possible > nr_cpu_ids) {
1498                 pr_warn("%d Processors exceeds NR_CPUS limit of %u\n",
1499                         possible, nr_cpu_ids);
1500                 possible = nr_cpu_ids;
1501         }
1502 
1503 #ifdef CONFIG_HOTPLUG_CPU
1504         if (!setup_max_cpus)
1505 #endif
1506         if (possible > i) {
1507                 pr_warn("%d Processors exceeds max_cpus limit of %u\n",
1508                         possible, setup_max_cpus);
1509                 possible = i;
1510         }
1511 
1512         nr_cpu_ids = possible;
1513 
1514         pr_info("Allowing %d CPUs, %d hotplug CPUs\n",
1515                 possible, max_t(int, possible - num_processors, 0));
1516 
1517         reset_cpu_possible_mask();
1518 
1519         for (i = 0; i < possible; i++)
1520                 set_cpu_possible(i, true);
1521 }
1522 
1523 #ifdef CONFIG_HOTPLUG_CPU
1524 
1525 /* Recompute SMT state for all CPUs on offline */
1526 static void recompute_smt_state(void)
1527 {
1528         int max_threads, cpu;
1529 
1530         max_threads = 0;
1531         for_each_online_cpu (cpu) {
1532                 int threads = cpumask_weight(topology_sibling_cpumask(cpu));
1533 
1534                 if (threads > max_threads)
1535                         max_threads = threads;
1536         }
1537         __max_smt_threads = max_threads;
1538 }
1539 
1540 static void remove_siblinginfo(int cpu)
1541 {
1542         int sibling;
1543         struct cpuinfo_x86 *c = &cpu_data(cpu);
1544 
1545         for_each_cpu(sibling, topology_core_cpumask(cpu)) {
1546                 cpumask_clear_cpu(cpu, topology_core_cpumask(sibling));
1547                 /*/
1548                  * last thread sibling in this cpu core going down
1549                  */
1550                 if (cpumask_weight(topology_sibling_cpumask(cpu)) == 1)
1551                         cpu_data(sibling).booted_cores--;
1552         }
1553 
1554         for_each_cpu(sibling, topology_die_cpumask(cpu))
1555                 cpumask_clear_cpu(cpu, topology_die_cpumask(sibling));
1556         for_each_cpu(sibling, topology_sibling_cpumask(cpu))
1557                 cpumask_clear_cpu(cpu, topology_sibling_cpumask(sibling));
1558         for_each_cpu(sibling, cpu_llc_shared_mask(cpu))
1559                 cpumask_clear_cpu(cpu, cpu_llc_shared_mask(sibling));
1560         cpumask_clear(cpu_llc_shared_mask(cpu));
1561         cpumask_clear(topology_sibling_cpumask(cpu));
1562         cpumask_clear(topology_core_cpumask(cpu));
1563         cpumask_clear(topology_die_cpumask(cpu));
1564         c->cpu_core_id = 0;
1565         c->booted_cores = 0;
1566         cpumask_clear_cpu(cpu, cpu_sibling_setup_mask);
1567         recompute_smt_state();
1568 }
1569 
1570 static void remove_cpu_from_maps(int cpu)
1571 {
1572         set_cpu_online(cpu, false);
1573         cpumask_clear_cpu(cpu, cpu_callout_mask);
1574         cpumask_clear_cpu(cpu, cpu_callin_mask);
1575         /* was set by cpu_init() */
1576         cpumask_clear_cpu(cpu, cpu_initialized_mask);
1577         numa_remove_cpu(cpu);
1578 }
1579 
1580 void cpu_disable_common(void)
1581 {
1582         int cpu = smp_processor_id();
1583 
1584         remove_siblinginfo(cpu);
1585 
1586         /* It's now safe to remove this processor from the online map */
1587         lock_vector_lock();
1588         remove_cpu_from_maps(cpu);
1589         unlock_vector_lock();
1590         fixup_irqs();
1591         lapic_offline();
1592 }
1593 
1594 int native_cpu_disable(void)
1595 {
1596         int ret;
1597 
1598         ret = lapic_can_unplug_cpu();
1599         if (ret)
1600                 return ret;
1601 
1602         /*
1603          * Disable the local APIC. Otherwise IPI broadcasts will reach
1604          * it. It still responds normally to INIT, NMI, SMI, and SIPI
1605          * messages.
1606          */
1607         apic_soft_disable();
1608         cpu_disable_common();
1609 
1610         return 0;
1611 }
1612 
1613 int common_cpu_die(unsigned int cpu)
1614 {
1615         int ret = 0;
1616 
1617         /* We don't do anything here: idle task is faking death itself. */
1618 
1619         /* They ack this in play_dead() by setting CPU_DEAD */
1620         if (cpu_wait_death(cpu, 5)) {
1621                 if (system_state == SYSTEM_RUNNING)
1622                         pr_info("CPU %u is now offline\n", cpu);
1623         } else {
1624                 pr_err("CPU %u didn't die...\n", cpu);
1625                 ret = -1;
1626         }
1627 
1628         return ret;
1629 }
1630 
1631 void native_cpu_die(unsigned int cpu)
1632 {
1633         common_cpu_die(cpu);
1634 }
1635 
1636 void play_dead_common(void)
1637 {
1638         idle_task_exit();
1639 
1640         /* Ack it */
1641         (void)cpu_report_death();
1642 
1643         /*
1644          * With physical CPU hotplug, we should halt the cpu
1645          */
1646         local_irq_disable();
1647 }
1648 
1649 static bool wakeup_cpu0(void)
1650 {
1651         if (smp_processor_id() == 0 && enable_start_cpu0)
1652                 return true;
1653 
1654         return false;
1655 }
1656 
1657 /*
1658  * We need to flush the caches before going to sleep, lest we have
1659  * dirty data in our caches when we come back up.
1660  */
1661 static inline void mwait_play_dead(void)
1662 {
1663         unsigned int eax, ebx, ecx, edx;
1664         unsigned int highest_cstate = 0;
1665         unsigned int highest_subcstate = 0;
1666         void *mwait_ptr;
1667         int i;
1668 
1669         if (boot_cpu_data.x86_vendor == X86_VENDOR_AMD ||
1670             boot_cpu_data.x86_vendor == X86_VENDOR_HYGON)
1671                 return;
1672         if (!this_cpu_has(X86_FEATURE_MWAIT))
1673                 return;
1674         if (!this_cpu_has(X86_FEATURE_CLFLUSH))
1675                 return;
1676         if (__this_cpu_read(cpu_info.cpuid_level) < CPUID_MWAIT_LEAF)
1677                 return;
1678 
1679         eax = CPUID_MWAIT_LEAF;
1680         ecx = 0;
1681         native_cpuid(&eax, &ebx, &ecx, &edx);
1682 
1683         /*
1684          * eax will be 0 if EDX enumeration is not valid.
1685          * Initialized below to cstate, sub_cstate value when EDX is valid.
1686          */
1687         if (!(ecx & CPUID5_ECX_EXTENSIONS_SUPPORTED)) {
1688                 eax = 0;
1689         } else {
1690                 edx >>= MWAIT_SUBSTATE_SIZE;
1691                 for (i = 0; i < 7 && edx; i++, edx >>= MWAIT_SUBSTATE_SIZE) {
1692                         if (edx & MWAIT_SUBSTATE_MASK) {
1693                                 highest_cstate = i;
1694                                 highest_subcstate = edx & MWAIT_SUBSTATE_MASK;
1695                         }
1696                 }
1697                 eax = (highest_cstate << MWAIT_SUBSTATE_SIZE) |
1698                         (highest_subcstate - 1);
1699         }
1700 
1701         /*
1702          * This should be a memory location in a cache line which is
1703          * unlikely to be touched by other processors.  The actual
1704          * content is immaterial as it is not actually modified in any way.
1705          */
1706         mwait_ptr = &current_thread_info()->flags;
1707 
1708         wbinvd();
1709 
1710         while (1) {
1711                 /*
1712                  * The CLFLUSH is a workaround for erratum AAI65 for
1713                  * the Xeon 7400 series.  It's not clear it is actually
1714                  * needed, but it should be harmless in either case.
1715                  * The WBINVD is insufficient due to the spurious-wakeup
1716                  * case where we return around the loop.
1717                  */
1718                 mb();
1719                 clflush(mwait_ptr);
1720                 mb();
1721                 __monitor(mwait_ptr, 0, 0);
1722                 mb();
1723                 __mwait(eax, 0);
1724                 /*
1725                  * If NMI wants to wake up CPU0, start CPU0.
1726                  */
1727                 if (wakeup_cpu0())
1728                         start_cpu0();
1729         }
1730 }
1731 
1732 void hlt_play_dead(void)
1733 {
1734         if (__this_cpu_read(cpu_info.x86) >= 4)
1735                 wbinvd();
1736 
1737         while (1) {
1738                 native_halt();
1739                 /*
1740                  * If NMI wants to wake up CPU0, start CPU0.
1741                  */
1742                 if (wakeup_cpu0())
1743                         start_cpu0();
1744         }
1745 }
1746 
1747 void native_play_dead(void)
1748 {
1749         play_dead_common();
1750         tboot_shutdown(TB_SHUTDOWN_WFS);
1751 
1752         mwait_play_dead();      /* Only returns on failure */
1753         if (cpuidle_play_dead())
1754                 hlt_play_dead();
1755 }
1756 
1757 #else /* ... !CONFIG_HOTPLUG_CPU */
1758 int native_cpu_disable(void)
1759 {
1760         return -ENOSYS;
1761 }
1762 
1763 void native_cpu_die(unsigned int cpu)
1764 {
1765         /* We said "no" in __cpu_disable */
1766         BUG();
1767 }
1768 
1769 void native_play_dead(void)
1770 {
1771         BUG();
1772 }
1773 
1774 #endif
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root/arch/x86/kernel/smpboot.c

DEFINITIONS
