root/arch/x86/kvm/pmu.h

INCLUDED FROM

DEFINITIONS

1. pmc_bitmask
2. pmc_read_counter
3. pmc_stop_counter
4. pmc_is_gp
5. pmc_is_fixed
6. pmc_is_enabled
7. get_gp_pmc
8. get_fixed_pmc

   1 /* SPDX-License-Identifier: GPL-2.0 */
   2 #ifndef __KVM_X86_PMU_H
   3 #define __KVM_X86_PMU_H
   4 
   5 #include <linux/nospec.h>
   6 
   7 #define vcpu_to_pmu(vcpu) (&(vcpu)->arch.pmu)
   8 #define pmu_to_vcpu(pmu)  (container_of((pmu), struct kvm_vcpu, arch.pmu))
   9 #define pmc_to_pmu(pmc)   (&(pmc)->vcpu->arch.pmu)
  10 
  11 /* retrieve the 4 bits for EN and PMI out of IA32_FIXED_CTR_CTRL */
  12 #define fixed_ctrl_field(ctrl_reg, idx) (((ctrl_reg) >> ((idx)*4)) & 0xf)
  13 
  14 #define VMWARE_BACKDOOR_PMC_HOST_TSC            0x10000
  15 #define VMWARE_BACKDOOR_PMC_REAL_TIME           0x10001
  16 #define VMWARE_BACKDOOR_PMC_APPARENT_TIME       0x10002
  17 
  18 struct kvm_event_hw_type_mapping {
  19         u8 eventsel;
  20         u8 unit_mask;
  21         unsigned event_type;
  22 };
  23 
  24 struct kvm_pmu_ops {
  25         unsigned (*find_arch_event)(struct kvm_pmu *pmu, u8 event_select,
  26                                     u8 unit_mask);
  27         unsigned (*find_fixed_event)(int idx);
  28         bool (*pmc_is_enabled)(struct kvm_pmc *pmc);
  29         struct kvm_pmc *(*pmc_idx_to_pmc)(struct kvm_pmu *pmu, int pmc_idx);
  30         struct kvm_pmc *(*msr_idx_to_pmc)(struct kvm_vcpu *vcpu, unsigned idx,
  31                                           u64 *mask);
  32         int (*is_valid_msr_idx)(struct kvm_vcpu *vcpu, unsigned idx);
  33         bool (*is_valid_msr)(struct kvm_vcpu *vcpu, u32 msr);
  34         int (*get_msr)(struct kvm_vcpu *vcpu, u32 msr, u64 *data);
  35         int (*set_msr)(struct kvm_vcpu *vcpu, struct msr_data *msr_info);
  36         void (*refresh)(struct kvm_vcpu *vcpu);
  37         void (*init)(struct kvm_vcpu *vcpu);
  38         void (*reset)(struct kvm_vcpu *vcpu);
  39 };
  40 
  41 static inline u64 pmc_bitmask(struct kvm_pmc *pmc)
  42 {
  43         struct kvm_pmu *pmu = pmc_to_pmu(pmc);
  44 
  45         return pmu->counter_bitmask[pmc->type];
  46 }
  47 
  48 static inline u64 pmc_read_counter(struct kvm_pmc *pmc)
  49 {
  50         u64 counter, enabled, running;
  51 
  52         counter = pmc->counter;
  53         if (pmc->perf_event)
  54                 counter += perf_event_read_value(pmc->perf_event,
  55                                                  &enabled, &running);
  56         /* FIXME: Scaling needed? */
  57         return counter & pmc_bitmask(pmc);
  58 }
  59 
  60 static inline void pmc_stop_counter(struct kvm_pmc *pmc)
  61 {
  62         if (pmc->perf_event) {
  63                 pmc->counter = pmc_read_counter(pmc);
  64                 perf_event_release_kernel(pmc->perf_event);
  65                 pmc->perf_event = NULL;
  66         }
  67 }
  68 
  69 static inline bool pmc_is_gp(struct kvm_pmc *pmc)
  70 {
  71         return pmc->type == KVM_PMC_GP;
  72 }
  73 
  74 static inline bool pmc_is_fixed(struct kvm_pmc *pmc)
  75 {
  76         return pmc->type == KVM_PMC_FIXED;
  77 }
  78 
  79 static inline bool pmc_is_enabled(struct kvm_pmc *pmc)
  80 {
  81         return kvm_x86_ops->pmu_ops->pmc_is_enabled(pmc);
  82 }
  83 
  84 /* returns general purpose PMC with the specified MSR. Note that it can be
  85  * used for both PERFCTRn and EVNTSELn; that is why it accepts base as a
  86  * paramenter to tell them apart.
  87  */
  88 static inline struct kvm_pmc *get_gp_pmc(struct kvm_pmu *pmu, u32 msr,
  89                                          u32 base)
  90 {
  91         if (msr >= base && msr < base + pmu->nr_arch_gp_counters) {
  92                 u32 index = array_index_nospec(msr - base,
  93                                                pmu->nr_arch_gp_counters);
  94 
  95                 return &pmu->gp_counters[index];
  96         }
  97 
  98         return NULL;
  99 }
 100 
 101 /* returns fixed PMC with the specified MSR */
 102 static inline struct kvm_pmc *get_fixed_pmc(struct kvm_pmu *pmu, u32 msr)
 103 {
 104         int base = MSR_CORE_PERF_FIXED_CTR0;
 105 
 106         if (msr >= base && msr < base + pmu->nr_arch_fixed_counters) {
 107                 u32 index = array_index_nospec(msr - base,
 108                                                pmu->nr_arch_fixed_counters);
 109 
 110                 return &pmu->fixed_counters[index];
 111         }
 112 
 113         return NULL;
 114 }
 115 
 116 void reprogram_gp_counter(struct kvm_pmc *pmc, u64 eventsel);
 117 void reprogram_fixed_counter(struct kvm_pmc *pmc, u8 ctrl, int fixed_idx);
 118 void reprogram_counter(struct kvm_pmu *pmu, int pmc_idx);
 119 
 120 void kvm_pmu_deliver_pmi(struct kvm_vcpu *vcpu);
 121 void kvm_pmu_handle_event(struct kvm_vcpu *vcpu);
 122 int kvm_pmu_rdpmc(struct kvm_vcpu *vcpu, unsigned pmc, u64 *data);
 123 int kvm_pmu_is_valid_msr_idx(struct kvm_vcpu *vcpu, unsigned idx);
 124 bool kvm_pmu_is_valid_msr(struct kvm_vcpu *vcpu, u32 msr);
 125 int kvm_pmu_get_msr(struct kvm_vcpu *vcpu, u32 msr, u64 *data);
 126 int kvm_pmu_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info);
 127 void kvm_pmu_refresh(struct kvm_vcpu *vcpu);
 128 void kvm_pmu_reset(struct kvm_vcpu *vcpu);
 129 void kvm_pmu_init(struct kvm_vcpu *vcpu);
 130 void kvm_pmu_destroy(struct kvm_vcpu *vcpu);
 131 int kvm_vm_ioctl_set_pmu_event_filter(struct kvm *kvm, void __user *argp);
 132 
 133 bool is_vmware_backdoor_pmc(u32 pmc_idx);
 134 
 135 extern struct kvm_pmu_ops intel_pmu_ops;
 136 extern struct kvm_pmu_ops amd_pmu_ops;
 137 #endif /* __KVM_X86_PMU_H */