arch/x86/kvm/paging

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This source file includes following definitions.
gpte_to_gfn_lvl
FNAME
FNAME
FNAME
   1 /* SPDX-License-Identifier: GPL-2.0-only */
   2 /*
   3  * Kernel-based Virtual Machine driver for Linux
   4  *
   5  * This module enables machines with Intel VT-x extensions to run virtual
   6  * machines without emulation or binary translation.
   7  *
   8  * MMU support
   9  *
  10  * Copyright (C) 2006 Qumranet, Inc.
  11  * Copyright 2010 Red Hat, Inc. and/or its affiliates.
  12  *
  13  * Authors:
  14  *   Yaniv Kamay  <yaniv@qumranet.com>
  15  *   Avi Kivity   <avi@qumranet.com>
  16  */
  17 
  18 /*
  19  * We need the mmu code to access both 32-bit and 64-bit guest ptes,
  20  * so the code in this file is compiled twice, once per pte size.
  21  */
  22 
  23 #if PTTYPE == 64
  24         #define pt_element_t u64
  25         #define guest_walker guest_walker64
  26         #define FNAME(name) paging##64_##name
  27         #define PT_BASE_ADDR_MASK PT64_BASE_ADDR_MASK
  28         #define PT_LVL_ADDR_MASK(lvl) PT64_LVL_ADDR_MASK(lvl)
  29         #define PT_LVL_OFFSET_MASK(lvl) PT64_LVL_OFFSET_MASK(lvl)
  30         #define PT_INDEX(addr, level) PT64_INDEX(addr, level)
  31         #define PT_LEVEL_BITS PT64_LEVEL_BITS
  32         #define PT_GUEST_DIRTY_SHIFT PT_DIRTY_SHIFT
  33         #define PT_GUEST_ACCESSED_SHIFT PT_ACCESSED_SHIFT
  34         #define PT_HAVE_ACCESSED_DIRTY(mmu) true
  35         #ifdef CONFIG_X86_64
  36         #define PT_MAX_FULL_LEVELS PT64_ROOT_MAX_LEVEL
  37         #define CMPXCHG cmpxchg
  38         #else
  39         #define CMPXCHG cmpxchg64
  40         #define PT_MAX_FULL_LEVELS 2
  41         #endif
  42 #elif PTTYPE == 32
  43         #define pt_element_t u32
  44         #define guest_walker guest_walker32
  45         #define FNAME(name) paging##32_##name
  46         #define PT_BASE_ADDR_MASK PT32_BASE_ADDR_MASK
  47         #define PT_LVL_ADDR_MASK(lvl) PT32_LVL_ADDR_MASK(lvl)
  48         #define PT_LVL_OFFSET_MASK(lvl) PT32_LVL_OFFSET_MASK(lvl)
  49         #define PT_INDEX(addr, level) PT32_INDEX(addr, level)
  50         #define PT_LEVEL_BITS PT32_LEVEL_BITS
  51         #define PT_MAX_FULL_LEVELS 2
  52         #define PT_GUEST_DIRTY_SHIFT PT_DIRTY_SHIFT
  53         #define PT_GUEST_ACCESSED_SHIFT PT_ACCESSED_SHIFT
  54         #define PT_HAVE_ACCESSED_DIRTY(mmu) true
  55         #define CMPXCHG cmpxchg
  56 #elif PTTYPE == PTTYPE_EPT
  57         #define pt_element_t u64
  58         #define guest_walker guest_walkerEPT
  59         #define FNAME(name) ept_##name
  60         #define PT_BASE_ADDR_MASK PT64_BASE_ADDR_MASK
  61         #define PT_LVL_ADDR_MASK(lvl) PT64_LVL_ADDR_MASK(lvl)
  62         #define PT_LVL_OFFSET_MASK(lvl) PT64_LVL_OFFSET_MASK(lvl)
  63         #define PT_INDEX(addr, level) PT64_INDEX(addr, level)
  64         #define PT_LEVEL_BITS PT64_LEVEL_BITS
  65         #define PT_GUEST_DIRTY_SHIFT 9
  66         #define PT_GUEST_ACCESSED_SHIFT 8
  67         #define PT_HAVE_ACCESSED_DIRTY(mmu) ((mmu)->ept_ad)
  68         #define CMPXCHG cmpxchg64
  69         #define PT_MAX_FULL_LEVELS 4
  70 #else
  71         #error Invalid PTTYPE value
  72 #endif
  73 
  74 #define PT_GUEST_DIRTY_MASK    (1 << PT_GUEST_DIRTY_SHIFT)
  75 #define PT_GUEST_ACCESSED_MASK (1 << PT_GUEST_ACCESSED_SHIFT)
  76 
  77 #define gpte_to_gfn_lvl FNAME(gpte_to_gfn_lvl)
  78 #define gpte_to_gfn(pte) gpte_to_gfn_lvl((pte), PT_PAGE_TABLE_LEVEL)
  79 
  80 /*
  81  * The guest_walker structure emulates the behavior of the hardware page
  82  * table walker.
  83  */
  84 struct guest_walker {
  85         int level;
  86         unsigned max_level;
  87         gfn_t table_gfn[PT_MAX_FULL_LEVELS];
  88         pt_element_t ptes[PT_MAX_FULL_LEVELS];
  89         pt_element_t prefetch_ptes[PTE_PREFETCH_NUM];
  90         gpa_t pte_gpa[PT_MAX_FULL_LEVELS];
  91         pt_element_t __user *ptep_user[PT_MAX_FULL_LEVELS];
  92         bool pte_writable[PT_MAX_FULL_LEVELS];
  93         unsigned pt_access;
  94         unsigned pte_access;
  95         gfn_t gfn;
  96         struct x86_exception fault;
  97 };
  98 
  99 static gfn_t gpte_to_gfn_lvl(pt_element_t gpte, int lvl)
 100 {
 101         return (gpte & PT_LVL_ADDR_MASK(lvl)) >> PAGE_SHIFT;
 102 }
 103 
 104 static inline void FNAME(protect_clean_gpte)(struct kvm_mmu *mmu, unsigned *access,
 105                                              unsigned gpte)
 106 {
 107         unsigned mask;
 108 
 109         /* dirty bit is not supported, so no need to track it */
 110         if (!PT_HAVE_ACCESSED_DIRTY(mmu))
 111                 return;
 112 
 113         BUILD_BUG_ON(PT_WRITABLE_MASK != ACC_WRITE_MASK);
 114 
 115         mask = (unsigned)~ACC_WRITE_MASK;
 116         /* Allow write access to dirty gptes */
 117         mask |= (gpte >> (PT_GUEST_DIRTY_SHIFT - PT_WRITABLE_SHIFT)) &
 118                 PT_WRITABLE_MASK;
 119         *access &= mask;
 120 }
 121 
 122 static inline int FNAME(is_present_gpte)(unsigned long pte)
 123 {
 124 #if PTTYPE != PTTYPE_EPT
 125         return pte & PT_PRESENT_MASK;
 126 #else
 127         return pte & 7;
 128 #endif
 129 }
 130 
 131 static int FNAME(cmpxchg_gpte)(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu,
 132                                pt_element_t __user *ptep_user, unsigned index,
 133                                pt_element_t orig_pte, pt_element_t new_pte)
 134 {
 135         int npages;
 136         pt_element_t ret;
 137         pt_element_t *table;
 138         struct page *page;
 139 
 140         npages = get_user_pages_fast((unsigned long)ptep_user, 1, FOLL_WRITE, &page);
 141         if (likely(npages == 1)) {
 142                 table = kmap_atomic(page);
 143                 ret = CMPXCHG(&table[index], orig_pte, new_pte);
 144                 kunmap_atomic(table);
 145 
 146                 kvm_release_page_dirty(page);
 147         } else {
 148                 struct vm_area_struct *vma;
 149                 unsigned long vaddr = (unsigned long)ptep_user & PAGE_MASK;
 150                 unsigned long pfn;
 151                 unsigned long paddr;
 152 
 153                 down_read(&current->mm->mmap_sem);
 154                 vma = find_vma_intersection(current->mm, vaddr, vaddr + PAGE_SIZE);
 155                 if (!vma || !(vma->vm_flags & VM_PFNMAP)) {
 156                         up_read(&current->mm->mmap_sem);
 157                         return -EFAULT;
 158                 }
 159                 pfn = ((vaddr - vma->vm_start) >> PAGE_SHIFT) + vma->vm_pgoff;
 160                 paddr = pfn << PAGE_SHIFT;
 161                 table = memremap(paddr, PAGE_SIZE, MEMREMAP_WB);
 162                 if (!table) {
 163                         up_read(&current->mm->mmap_sem);
 164                         return -EFAULT;
 165                 }
 166                 ret = CMPXCHG(&table[index], orig_pte, new_pte);
 167                 memunmap(table);
 168                 up_read(&current->mm->mmap_sem);
 169         }
 170 
 171         return (ret != orig_pte);
 172 }
 173 
 174 static bool FNAME(prefetch_invalid_gpte)(struct kvm_vcpu *vcpu,
 175                                   struct kvm_mmu_page *sp, u64 *spte,
 176                                   u64 gpte)
 177 {
 178         if (is_rsvd_bits_set(vcpu->arch.mmu, gpte, PT_PAGE_TABLE_LEVEL))
 179                 goto no_present;
 180 
 181         if (!FNAME(is_present_gpte)(gpte))
 182                 goto no_present;
 183 
 184         /* if accessed bit is not supported prefetch non accessed gpte */
 185         if (PT_HAVE_ACCESSED_DIRTY(vcpu->arch.mmu) &&
 186             !(gpte & PT_GUEST_ACCESSED_MASK))
 187                 goto no_present;
 188 
 189         return false;
 190 
 191 no_present:
 192         drop_spte(vcpu->kvm, spte);
 193         return true;
 194 }
 195 
 196 /*
 197  * For PTTYPE_EPT, a page table can be executable but not readable
 198  * on supported processors. Therefore, set_spte does not automatically
 199  * set bit 0 if execute only is supported. Here, we repurpose ACC_USER_MASK
 200  * to signify readability since it isn't used in the EPT case
 201  */
 202 static inline unsigned FNAME(gpte_access)(u64 gpte)
 203 {
 204         unsigned access;
 205 #if PTTYPE == PTTYPE_EPT
 206         access = ((gpte & VMX_EPT_WRITABLE_MASK) ? ACC_WRITE_MASK : 0) |
 207                 ((gpte & VMX_EPT_EXECUTABLE_MASK) ? ACC_EXEC_MASK : 0) |
 208                 ((gpte & VMX_EPT_READABLE_MASK) ? ACC_USER_MASK : 0);
 209 #else
 210         BUILD_BUG_ON(ACC_EXEC_MASK != PT_PRESENT_MASK);
 211         BUILD_BUG_ON(ACC_EXEC_MASK != 1);
 212         access = gpte & (PT_WRITABLE_MASK | PT_USER_MASK | PT_PRESENT_MASK);
 213         /* Combine NX with P (which is set here) to get ACC_EXEC_MASK.  */
 214         access ^= (gpte >> PT64_NX_SHIFT);
 215 #endif
 216 
 217         return access;
 218 }
 219 
 220 static int FNAME(update_accessed_dirty_bits)(struct kvm_vcpu *vcpu,
 221                                              struct kvm_mmu *mmu,
 222                                              struct guest_walker *walker,
 223                                              int write_fault)
 224 {
 225         unsigned level, index;
 226         pt_element_t pte, orig_pte;
 227         pt_element_t __user *ptep_user;
 228         gfn_t table_gfn;
 229         int ret;
 230 
 231         /* dirty/accessed bits are not supported, so no need to update them */
 232         if (!PT_HAVE_ACCESSED_DIRTY(mmu))
 233                 return 0;
 234 
 235         for (level = walker->max_level; level >= walker->level; --level) {
 236                 pte = orig_pte = walker->ptes[level - 1];
 237                 table_gfn = walker->table_gfn[level - 1];
 238                 ptep_user = walker->ptep_user[level - 1];
 239                 index = offset_in_page(ptep_user) / sizeof(pt_element_t);
 240                 if (!(pte & PT_GUEST_ACCESSED_MASK)) {
 241                         trace_kvm_mmu_set_accessed_bit(table_gfn, index, sizeof(pte));
 242                         pte |= PT_GUEST_ACCESSED_MASK;
 243                 }
 244                 if (level == walker->level && write_fault &&
 245                                 !(pte & PT_GUEST_DIRTY_MASK)) {
 246                         trace_kvm_mmu_set_dirty_bit(table_gfn, index, sizeof(pte));
 247 #if PTTYPE == PTTYPE_EPT
 248                         if (kvm_arch_write_log_dirty(vcpu))
 249                                 return -EINVAL;
 250 #endif
 251                         pte |= PT_GUEST_DIRTY_MASK;
 252                 }
 253                 if (pte == orig_pte)
 254                         continue;
 255 
 256                 /*
 257                  * If the slot is read-only, simply do not process the accessed
 258                  * and dirty bits.  This is the correct thing to do if the slot
 259                  * is ROM, and page tables in read-as-ROM/write-as-MMIO slots
 260                  * are only supported if the accessed and dirty bits are already
 261                  * set in the ROM (so that MMIO writes are never needed).
 262                  *
 263                  * Note that NPT does not allow this at all and faults, since
 264                  * it always wants nested page table entries for the guest
 265                  * page tables to be writable.  And EPT works but will simply
 266                  * overwrite the read-only memory to set the accessed and dirty
 267                  * bits.
 268                  */
 269                 if (unlikely(!walker->pte_writable[level - 1]))
 270                         continue;
 271 
 272                 ret = FNAME(cmpxchg_gpte)(vcpu, mmu, ptep_user, index, orig_pte, pte);
 273                 if (ret)
 274                         return ret;
 275 
 276                 kvm_vcpu_mark_page_dirty(vcpu, table_gfn);
 277                 walker->ptes[level - 1] = pte;
 278         }
 279         return 0;
 280 }
 281 
 282 static inline unsigned FNAME(gpte_pkeys)(struct kvm_vcpu *vcpu, u64 gpte)
 283 {
 284         unsigned pkeys = 0;
 285 #if PTTYPE == 64
 286         pte_t pte = {.pte = gpte};
 287 
 288         pkeys = pte_flags_pkey(pte_flags(pte));
 289 #endif
 290         return pkeys;
 291 }
 292 
 293 /*
 294  * Fetch a guest pte for a guest virtual address, or for an L2's GPA.
 295  */
 296 static int FNAME(walk_addr_generic)(struct guest_walker *walker,
 297                                     struct kvm_vcpu *vcpu, struct kvm_mmu *mmu,
 298                                     gpa_t addr, u32 access)
 299 {
 300         int ret;
 301         pt_element_t pte;
 302         pt_element_t __user *uninitialized_var(ptep_user);
 303         gfn_t table_gfn;
 304         u64 pt_access, pte_access;
 305         unsigned index, accessed_dirty, pte_pkey;
 306         unsigned nested_access;
 307         gpa_t pte_gpa;
 308         bool have_ad;
 309         int offset;
 310         u64 walk_nx_mask = 0;
 311         const int write_fault = access & PFERR_WRITE_MASK;
 312         const int user_fault  = access & PFERR_USER_MASK;
 313         const int fetch_fault = access & PFERR_FETCH_MASK;
 314         u16 errcode = 0;
 315         gpa_t real_gpa;
 316         gfn_t gfn;
 317 
 318         trace_kvm_mmu_pagetable_walk(addr, access);
 319 retry_walk:
 320         walker->level = mmu->root_level;
 321         pte           = mmu->get_cr3(vcpu);
 322         have_ad       = PT_HAVE_ACCESSED_DIRTY(mmu);
 323 
 324 #if PTTYPE == 64
 325         walk_nx_mask = 1ULL << PT64_NX_SHIFT;
 326         if (walker->level == PT32E_ROOT_LEVEL) {
 327                 pte = mmu->get_pdptr(vcpu, (addr >> 30) & 3);
 328                 trace_kvm_mmu_paging_element(pte, walker->level);
 329                 if (!FNAME(is_present_gpte)(pte))
 330                         goto error;
 331                 --walker->level;
 332         }
 333 #endif
 334         walker->max_level = walker->level;
 335         ASSERT(!(is_long_mode(vcpu) && !is_pae(vcpu)));
 336 
 337         /*
 338          * FIXME: on Intel processors, loads of the PDPTE registers for PAE paging
 339          * by the MOV to CR instruction are treated as reads and do not cause the
 340          * processor to set the dirty flag in any EPT paging-structure entry.
 341          */
 342         nested_access = (have_ad ? PFERR_WRITE_MASK : 0) | PFERR_USER_MASK;
 343 
 344         pte_access = ~0;
 345         ++walker->level;
 346 
 347         do {
 348                 gfn_t real_gfn;
 349                 unsigned long host_addr;
 350 
 351                 pt_access = pte_access;
 352                 --walker->level;
 353 
 354                 index = PT_INDEX(addr, walker->level);
 355                 table_gfn = gpte_to_gfn(pte);
 356                 offset    = index * sizeof(pt_element_t);
 357                 pte_gpa   = gfn_to_gpa(table_gfn) + offset;
 358 
 359                 BUG_ON(walker->level < 1);
 360                 walker->table_gfn[walker->level - 1] = table_gfn;
 361                 walker->pte_gpa[walker->level - 1] = pte_gpa;
 362 
 363                 real_gfn = mmu->translate_gpa(vcpu, gfn_to_gpa(table_gfn),
 364                                               nested_access,
 365                                               &walker->fault);
 366 
 367                 /*
 368                  * FIXME: This can happen if emulation (for of an INS/OUTS
 369                  * instruction) triggers a nested page fault.  The exit
 370                  * qualification / exit info field will incorrectly have
 371                  * "guest page access" as the nested page fault's cause,
 372                  * instead of "guest page structure access".  To fix this,
 373                  * the x86_exception struct should be augmented with enough
 374                  * information to fix the exit_qualification or exit_info_1
 375                  * fields.
 376                  */
 377                 if (unlikely(real_gfn == UNMAPPED_GVA))
 378                         return 0;
 379 
 380                 real_gfn = gpa_to_gfn(real_gfn);
 381 
 382                 host_addr = kvm_vcpu_gfn_to_hva_prot(vcpu, real_gfn,
 383                                             &walker->pte_writable[walker->level - 1]);
 384                 if (unlikely(kvm_is_error_hva(host_addr)))
 385                         goto error;
 386 
 387                 ptep_user = (pt_element_t __user *)((void *)host_addr + offset);
 388                 if (unlikely(__copy_from_user(&pte, ptep_user, sizeof(pte))))
 389                         goto error;
 390                 walker->ptep_user[walker->level - 1] = ptep_user;
 391 
 392                 trace_kvm_mmu_paging_element(pte, walker->level);
 393 
 394                 /*
 395                  * Inverting the NX it lets us AND it like other
 396                  * permission bits.
 397                  */
 398                 pte_access = pt_access & (pte ^ walk_nx_mask);
 399 
 400                 if (unlikely(!FNAME(is_present_gpte)(pte)))
 401                         goto error;
 402 
 403                 if (unlikely(is_rsvd_bits_set(mmu, pte, walker->level))) {
 404                         errcode = PFERR_RSVD_MASK | PFERR_PRESENT_MASK;
 405                         goto error;
 406                 }
 407 
 408                 walker->ptes[walker->level - 1] = pte;
 409         } while (!is_last_gpte(mmu, walker->level, pte));
 410 
 411         pte_pkey = FNAME(gpte_pkeys)(vcpu, pte);
 412         accessed_dirty = have_ad ? pte_access & PT_GUEST_ACCESSED_MASK : 0;
 413 
 414         /* Convert to ACC_*_MASK flags for struct guest_walker.  */
 415         walker->pt_access = FNAME(gpte_access)(pt_access ^ walk_nx_mask);
 416         walker->pte_access = FNAME(gpte_access)(pte_access ^ walk_nx_mask);
 417         errcode = permission_fault(vcpu, mmu, walker->pte_access, pte_pkey, access);
 418         if (unlikely(errcode))
 419                 goto error;
 420 
 421         gfn = gpte_to_gfn_lvl(pte, walker->level);
 422         gfn += (addr & PT_LVL_OFFSET_MASK(walker->level)) >> PAGE_SHIFT;
 423 
 424         if (PTTYPE == 32 && walker->level == PT_DIRECTORY_LEVEL && is_cpuid_PSE36())
 425                 gfn += pse36_gfn_delta(pte);
 426 
 427         real_gpa = mmu->translate_gpa(vcpu, gfn_to_gpa(gfn), access, &walker->fault);
 428         if (real_gpa == UNMAPPED_GVA)
 429                 return 0;
 430 
 431         walker->gfn = real_gpa >> PAGE_SHIFT;
 432 
 433         if (!write_fault)
 434                 FNAME(protect_clean_gpte)(mmu, &walker->pte_access, pte);
 435         else
 436                 /*
 437                  * On a write fault, fold the dirty bit into accessed_dirty.
 438                  * For modes without A/D bits support accessed_dirty will be
 439                  * always clear.
 440                  */
 441                 accessed_dirty &= pte >>
 442                         (PT_GUEST_DIRTY_SHIFT - PT_GUEST_ACCESSED_SHIFT);
 443 
 444         if (unlikely(!accessed_dirty)) {
 445                 ret = FNAME(update_accessed_dirty_bits)(vcpu, mmu, walker, write_fault);
 446                 if (unlikely(ret < 0))
 447                         goto error;
 448                 else if (ret)
 449                         goto retry_walk;
 450         }
 451 
 452         pgprintk("%s: pte %llx pte_access %x pt_access %x\n",
 453                  __func__, (u64)pte, walker->pte_access, walker->pt_access);
 454         return 1;
 455 
 456 error:
 457         errcode |= write_fault | user_fault;
 458         if (fetch_fault && (mmu->nx ||
 459                             kvm_read_cr4_bits(vcpu, X86_CR4_SMEP)))
 460                 errcode |= PFERR_FETCH_MASK;
 461 
 462         walker->fault.vector = PF_VECTOR;
 463         walker->fault.error_code_valid = true;
 464         walker->fault.error_code = errcode;
 465 
 466 #if PTTYPE == PTTYPE_EPT
 467         /*
 468          * Use PFERR_RSVD_MASK in error_code to to tell if EPT
 469          * misconfiguration requires to be injected. The detection is
 470          * done by is_rsvd_bits_set() above.
 471          *
 472          * We set up the value of exit_qualification to inject:
 473          * [2:0] - Derive from the access bits. The exit_qualification might be
 474          *         out of date if it is serving an EPT misconfiguration.
 475          * [5:3] - Calculated by the page walk of the guest EPT page tables
 476          * [7:8] - Derived from [7:8] of real exit_qualification
 477          *
 478          * The other bits are set to 0.
 479          */
 480         if (!(errcode & PFERR_RSVD_MASK)) {
 481                 vcpu->arch.exit_qualification &= 0x180;
 482                 if (write_fault)
 483                         vcpu->arch.exit_qualification |= EPT_VIOLATION_ACC_WRITE;
 484                 if (user_fault)
 485                         vcpu->arch.exit_qualification |= EPT_VIOLATION_ACC_READ;
 486                 if (fetch_fault)
 487                         vcpu->arch.exit_qualification |= EPT_VIOLATION_ACC_INSTR;
 488                 vcpu->arch.exit_qualification |= (pte_access & 0x7) << 3;
 489         }
 490 #endif
 491         walker->fault.address = addr;
 492         walker->fault.nested_page_fault = mmu != vcpu->arch.walk_mmu;
 493 
 494         trace_kvm_mmu_walker_error(walker->fault.error_code);
 495         return 0;
 496 }
 497 
 498 static int FNAME(walk_addr)(struct guest_walker *walker,
 499                             struct kvm_vcpu *vcpu, gpa_t addr, u32 access)
 500 {
 501         return FNAME(walk_addr_generic)(walker, vcpu, vcpu->arch.mmu, addr,
 502                                         access);
 503 }
 504 
 505 #if PTTYPE != PTTYPE_EPT
 506 static int FNAME(walk_addr_nested)(struct guest_walker *walker,
 507                                    struct kvm_vcpu *vcpu, gva_t addr,
 508                                    u32 access)
 509 {
 510         return FNAME(walk_addr_generic)(walker, vcpu, &vcpu->arch.nested_mmu,
 511                                         addr, access);
 512 }
 513 #endif
 514 
 515 static bool
 516 FNAME(prefetch_gpte)(struct kvm_vcpu *vcpu, struct kvm_mmu_page *sp,
 517                      u64 *spte, pt_element_t gpte, bool no_dirty_log)
 518 {
 519         unsigned pte_access;
 520         gfn_t gfn;
 521         kvm_pfn_t pfn;
 522 
 523         if (FNAME(prefetch_invalid_gpte)(vcpu, sp, spte, gpte))
 524                 return false;
 525 
 526         pgprintk("%s: gpte %llx spte %p\n", __func__, (u64)gpte, spte);
 527 
 528         gfn = gpte_to_gfn(gpte);
 529         pte_access = sp->role.access & FNAME(gpte_access)(gpte);
 530         FNAME(protect_clean_gpte)(vcpu->arch.mmu, &pte_access, gpte);
 531         pfn = pte_prefetch_gfn_to_pfn(vcpu, gfn,
 532                         no_dirty_log && (pte_access & ACC_WRITE_MASK));
 533         if (is_error_pfn(pfn))
 534                 return false;
 535 
 536         /*
 537          * we call mmu_set_spte() with host_writable = true because
 538          * pte_prefetch_gfn_to_pfn always gets a writable pfn.
 539          */
 540         mmu_set_spte(vcpu, spte, pte_access, 0, PT_PAGE_TABLE_LEVEL, gfn, pfn,
 541                      true, true);
 542 
 543         kvm_release_pfn_clean(pfn);
 544         return true;
 545 }
 546 
 547 static void FNAME(update_pte)(struct kvm_vcpu *vcpu, struct kvm_mmu_page *sp,
 548                               u64 *spte, const void *pte)
 549 {
 550         pt_element_t gpte = *(const pt_element_t *)pte;
 551 
 552         FNAME(prefetch_gpte)(vcpu, sp, spte, gpte, false);
 553 }
 554 
 555 static bool FNAME(gpte_changed)(struct kvm_vcpu *vcpu,
 556                                 struct guest_walker *gw, int level)
 557 {
 558         pt_element_t curr_pte;
 559         gpa_t base_gpa, pte_gpa = gw->pte_gpa[level - 1];
 560         u64 mask;
 561         int r, index;
 562 
 563         if (level == PT_PAGE_TABLE_LEVEL) {
 564                 mask = PTE_PREFETCH_NUM * sizeof(pt_element_t) - 1;
 565                 base_gpa = pte_gpa & ~mask;
 566                 index = (pte_gpa - base_gpa) / sizeof(pt_element_t);
 567 
 568                 r = kvm_vcpu_read_guest_atomic(vcpu, base_gpa,
 569                                 gw->prefetch_ptes, sizeof(gw->prefetch_ptes));
 570                 curr_pte = gw->prefetch_ptes[index];
 571         } else
 572                 r = kvm_vcpu_read_guest_atomic(vcpu, pte_gpa,
 573                                   &curr_pte, sizeof(curr_pte));
 574 
 575         return r || curr_pte != gw->ptes[level - 1];
 576 }
 577 
 578 static void FNAME(pte_prefetch)(struct kvm_vcpu *vcpu, struct guest_walker *gw,
 579                                 u64 *sptep)
 580 {
 581         struct kvm_mmu_page *sp;
 582         pt_element_t *gptep = gw->prefetch_ptes;
 583         u64 *spte;
 584         int i;
 585 
 586         sp = page_header(__pa(sptep));
 587 
 588         if (sp->role.level > PT_PAGE_TABLE_LEVEL)
 589                 return;
 590 
 591         if (sp->role.direct)
 592                 return __direct_pte_prefetch(vcpu, sp, sptep);
 593 
 594         i = (sptep - sp->spt) & ~(PTE_PREFETCH_NUM - 1);
 595         spte = sp->spt + i;
 596 
 597         for (i = 0; i < PTE_PREFETCH_NUM; i++, spte++) {
 598                 if (spte == sptep)
 599                         continue;
 600 
 601                 if (is_shadow_present_pte(*spte))
 602                         continue;
 603 
 604                 if (!FNAME(prefetch_gpte)(vcpu, sp, spte, gptep[i], true))
 605                         break;
 606         }
 607 }
 608 
 609 /*
 610  * Fetch a shadow pte for a specific level in the paging hierarchy.
 611  * If the guest tries to write a write-protected page, we need to
 612  * emulate this operation, return 1 to indicate this case.
 613  */
 614 static int FNAME(fetch)(struct kvm_vcpu *vcpu, gpa_t addr,
 615                          struct guest_walker *gw,
 616                          int write_fault, int hlevel,
 617                          kvm_pfn_t pfn, bool map_writable, bool prefault,
 618                          bool lpage_disallowed)
 619 {
 620         struct kvm_mmu_page *sp = NULL;
 621         struct kvm_shadow_walk_iterator it;
 622         unsigned direct_access, access = gw->pt_access;
 623         int top_level, ret;
 624         gfn_t gfn, base_gfn;
 625 
 626         direct_access = gw->pte_access;
 627 
 628         top_level = vcpu->arch.mmu->root_level;
 629         if (top_level == PT32E_ROOT_LEVEL)
 630                 top_level = PT32_ROOT_LEVEL;
 631         /*
 632          * Verify that the top-level gpte is still there.  Since the page
 633          * is a root page, it is either write protected (and cannot be
 634          * changed from now on) or it is invalid (in which case, we don't
 635          * really care if it changes underneath us after this point).
 636          */
 637         if (FNAME(gpte_changed)(vcpu, gw, top_level))
 638                 goto out_gpte_changed;
 639 
 640         if (!VALID_PAGE(vcpu->arch.mmu->root_hpa))
 641                 goto out_gpte_changed;
 642 
 643         for (shadow_walk_init(&it, vcpu, addr);
 644              shadow_walk_okay(&it) && it.level > gw->level;
 645              shadow_walk_next(&it)) {
 646                 gfn_t table_gfn;
 647 
 648                 clear_sp_write_flooding_count(it.sptep);
 649                 drop_large_spte(vcpu, it.sptep);
 650 
 651                 sp = NULL;
 652                 if (!is_shadow_present_pte(*it.sptep)) {
 653                         table_gfn = gw->table_gfn[it.level - 2];
 654                         sp = kvm_mmu_get_page(vcpu, table_gfn, addr, it.level-1,
 655                                               false, access);
 656                 }
 657 
 658                 /*
 659                  * Verify that the gpte in the page we've just write
 660                  * protected is still there.
 661                  */
 662                 if (FNAME(gpte_changed)(vcpu, gw, it.level - 1))
 663                         goto out_gpte_changed;
 664 
 665                 if (sp)
 666                         link_shadow_page(vcpu, it.sptep, sp);
 667         }
 668 
 669         /*
 670          * FNAME(page_fault) might have clobbered the bottom bits of
 671          * gw->gfn, restore them from the virtual address.
 672          */
 673         gfn = gw->gfn | ((addr & PT_LVL_OFFSET_MASK(gw->level)) >> PAGE_SHIFT);
 674         base_gfn = gfn;
 675 
 676         trace_kvm_mmu_spte_requested(addr, gw->level, pfn);
 677 
 678         for (; shadow_walk_okay(&it); shadow_walk_next(&it)) {
 679                 clear_sp_write_flooding_count(it.sptep);
 680 
 681                 /*
 682                  * We cannot overwrite existing page tables with an NX
 683                  * large page, as the leaf could be executable.
 684                  */
 685                 disallowed_hugepage_adjust(it, gfn, &pfn, &hlevel);
 686 
 687                 base_gfn = gfn & ~(KVM_PAGES_PER_HPAGE(it.level) - 1);
 688                 if (it.level == hlevel)
 689                         break;
 690 
 691                 validate_direct_spte(vcpu, it.sptep, direct_access);
 692 
 693                 drop_large_spte(vcpu, it.sptep);
 694 
 695                 if (!is_shadow_present_pte(*it.sptep)) {
 696                         sp = kvm_mmu_get_page(vcpu, base_gfn, addr,
 697                                               it.level - 1, true, direct_access);
 698                         link_shadow_page(vcpu, it.sptep, sp);
 699                         if (lpage_disallowed)
 700                                 account_huge_nx_page(vcpu->kvm, sp);
 701                 }
 702         }
 703 
 704         ret = mmu_set_spte(vcpu, it.sptep, gw->pte_access, write_fault,
 705                            it.level, base_gfn, pfn, prefault, map_writable);
 706         FNAME(pte_prefetch)(vcpu, gw, it.sptep);
 707         ++vcpu->stat.pf_fixed;
 708         return ret;
 709 
 710 out_gpte_changed:
 711         return RET_PF_RETRY;
 712 }
 713 
 714  /*
 715  * To see whether the mapped gfn can write its page table in the current
 716  * mapping.
 717  *
 718  * It is the helper function of FNAME(page_fault). When guest uses large page
 719  * size to map the writable gfn which is used as current page table, we should
 720  * force kvm to use small page size to map it because new shadow page will be
 721  * created when kvm establishes shadow page table that stop kvm using large
 722  * page size. Do it early can avoid unnecessary #PF and emulation.
 723  *
 724  * @write_fault_to_shadow_pgtable will return true if the fault gfn is
 725  * currently used as its page table.
 726  *
 727  * Note: the PDPT page table is not checked for PAE-32 bit guest. It is ok
 728  * since the PDPT is always shadowed, that means, we can not use large page
 729  * size to map the gfn which is used as PDPT.
 730  */
 731 static bool
 732 FNAME(is_self_change_mapping)(struct kvm_vcpu *vcpu,
 733                               struct guest_walker *walker, int user_fault,
 734                               bool *write_fault_to_shadow_pgtable)
 735 {
 736         int level;
 737         gfn_t mask = ~(KVM_PAGES_PER_HPAGE(walker->level) - 1);
 738         bool self_changed = false;
 739 
 740         if (!(walker->pte_access & ACC_WRITE_MASK ||
 741               (!is_write_protection(vcpu) && !user_fault)))
 742                 return false;
 743 
 744         for (level = walker->level; level <= walker->max_level; level++) {
 745                 gfn_t gfn = walker->gfn ^ walker->table_gfn[level - 1];
 746 
 747                 self_changed |= !(gfn & mask);
 748                 *write_fault_to_shadow_pgtable |= !gfn;
 749         }
 750 
 751         return self_changed;
 752 }
 753 
 754 /*
 755  * Page fault handler.  There are several causes for a page fault:
 756  *   - there is no shadow pte for the guest pte
 757  *   - write access through a shadow pte marked read only so that we can set
 758  *     the dirty bit
 759  *   - write access to a shadow pte marked read only so we can update the page
 760  *     dirty bitmap, when userspace requests it
 761  *   - mmio access; in this case we will never install a present shadow pte
 762  *   - normal guest page fault due to the guest pte marked not present, not
 763  *     writable, or not executable
 764  *
 765  *  Returns: 1 if we need to emulate the instruction, 0 otherwise, or
 766  *           a negative value on error.
 767  */
 768 static int FNAME(page_fault)(struct kvm_vcpu *vcpu, gpa_t addr, u32 error_code,
 769                              bool prefault)
 770 {
 771         int write_fault = error_code & PFERR_WRITE_MASK;
 772         int user_fault = error_code & PFERR_USER_MASK;
 773         struct guest_walker walker;
 774         int r;
 775         kvm_pfn_t pfn;
 776         int level = PT_PAGE_TABLE_LEVEL;
 777         unsigned long mmu_seq;
 778         bool map_writable, is_self_change_mapping;
 779         bool lpage_disallowed = (error_code & PFERR_FETCH_MASK) &&
 780                                 is_nx_huge_page_enabled();
 781         bool force_pt_level = lpage_disallowed;
 782 
 783         pgprintk("%s: addr %lx err %x\n", __func__, addr, error_code);
 784 
 785         r = mmu_topup_memory_caches(vcpu);
 786         if (r)
 787                 return r;
 788 
 789         /*
 790          * If PFEC.RSVD is set, this is a shadow page fault.
 791          * The bit needs to be cleared before walking guest page tables.
 792          */
 793         error_code &= ~PFERR_RSVD_MASK;
 794 
 795         /*
 796          * Look up the guest pte for the faulting address.
 797          */
 798         r = FNAME(walk_addr)(&walker, vcpu, addr, error_code);
 799 
 800         /*
 801          * The page is not mapped by the guest.  Let the guest handle it.
 802          */
 803         if (!r) {
 804                 pgprintk("%s: guest page fault\n", __func__);
 805                 if (!prefault)
 806                         inject_page_fault(vcpu, &walker.fault);
 807 
 808                 return RET_PF_RETRY;
 809         }
 810 
 811         if (page_fault_handle_page_track(vcpu, error_code, walker.gfn)) {
 812                 shadow_page_table_clear_flood(vcpu, addr);
 813                 return RET_PF_EMULATE;
 814         }
 815 
 816         vcpu->arch.write_fault_to_shadow_pgtable = false;
 817 
 818         is_self_change_mapping = FNAME(is_self_change_mapping)(vcpu,
 819               &walker, user_fault, &vcpu->arch.write_fault_to_shadow_pgtable);
 820 
 821         if (walker.level >= PT_DIRECTORY_LEVEL && !is_self_change_mapping) {
 822                 level = mapping_level(vcpu, walker.gfn, &force_pt_level);
 823                 if (likely(!force_pt_level)) {
 824                         level = min(walker.level, level);
 825                         walker.gfn = walker.gfn & ~(KVM_PAGES_PER_HPAGE(level) - 1);
 826                 }
 827         } else
 828                 force_pt_level = true;
 829 
 830         mmu_seq = vcpu->kvm->mmu_notifier_seq;
 831         smp_rmb();
 832 
 833         if (try_async_pf(vcpu, prefault, walker.gfn, addr, &pfn, write_fault,
 834                          &map_writable))
 835                 return RET_PF_RETRY;
 836 
 837         if (handle_abnormal_pfn(vcpu, addr, walker.gfn, pfn, walker.pte_access, &r))
 838                 return r;
 839 
 840         /*
 841          * Do not change pte_access if the pfn is a mmio page, otherwise
 842          * we will cache the incorrect access into mmio spte.
 843          */
 844         if (write_fault && !(walker.pte_access & ACC_WRITE_MASK) &&
 845              !is_write_protection(vcpu) && !user_fault &&
 846               !is_noslot_pfn(pfn)) {
 847                 walker.pte_access |= ACC_WRITE_MASK;
 848                 walker.pte_access &= ~ACC_USER_MASK;
 849 
 850                 /*
 851                  * If we converted a user page to a kernel page,
 852                  * so that the kernel can write to it when cr0.wp=0,
 853                  * then we should prevent the kernel from executing it
 854                  * if SMEP is enabled.
 855                  */
 856                 if (kvm_read_cr4_bits(vcpu, X86_CR4_SMEP))
 857                         walker.pte_access &= ~ACC_EXEC_MASK;
 858         }
 859 
 860         r = RET_PF_RETRY;
 861         spin_lock(&vcpu->kvm->mmu_lock);
 862         if (mmu_notifier_retry(vcpu->kvm, mmu_seq))
 863                 goto out_unlock;
 864 
 865         kvm_mmu_audit(vcpu, AUDIT_PRE_PAGE_FAULT);
 866         if (make_mmu_pages_available(vcpu) < 0)
 867                 goto out_unlock;
 868         if (!force_pt_level)
 869                 transparent_hugepage_adjust(vcpu, walker.gfn, &pfn, &level);
 870         r = FNAME(fetch)(vcpu, addr, &walker, write_fault,
 871                          level, pfn, map_writable, prefault, lpage_disallowed);
 872         kvm_mmu_audit(vcpu, AUDIT_POST_PAGE_FAULT);
 873 
 874 out_unlock:
 875         spin_unlock(&vcpu->kvm->mmu_lock);
 876         kvm_release_pfn_clean(pfn);
 877         return r;
 878 }
 879 
 880 static gpa_t FNAME(get_level1_sp_gpa)(struct kvm_mmu_page *sp)
 881 {
 882         int offset = 0;
 883 
 884         WARN_ON(sp->role.level != PT_PAGE_TABLE_LEVEL);
 885 
 886         if (PTTYPE == 32)
 887                 offset = sp->role.quadrant << PT64_LEVEL_BITS;
 888 
 889         return gfn_to_gpa(sp->gfn) + offset * sizeof(pt_element_t);
 890 }
 891 
 892 static void FNAME(invlpg)(struct kvm_vcpu *vcpu, gva_t gva, hpa_t root_hpa)
 893 {
 894         struct kvm_shadow_walk_iterator iterator;
 895         struct kvm_mmu_page *sp;
 896         int level;
 897         u64 *sptep;
 898 
 899         vcpu_clear_mmio_info(vcpu, gva);
 900 
 901         /*
 902          * No need to check return value here, rmap_can_add() can
 903          * help us to skip pte prefetch later.
 904          */
 905         mmu_topup_memory_caches(vcpu);
 906 
 907         if (!VALID_PAGE(root_hpa)) {
 908                 WARN_ON(1);
 909                 return;
 910         }
 911 
 912         spin_lock(&vcpu->kvm->mmu_lock);
 913         for_each_shadow_entry_using_root(vcpu, root_hpa, gva, iterator) {
 914                 level = iterator.level;
 915                 sptep = iterator.sptep;
 916 
 917                 sp = page_header(__pa(sptep));
 918                 if (is_last_spte(*sptep, level)) {
 919                         pt_element_t gpte;
 920                         gpa_t pte_gpa;
 921 
 922                         if (!sp->unsync)
 923                                 break;
 924 
 925                         pte_gpa = FNAME(get_level1_sp_gpa)(sp);
 926                         pte_gpa += (sptep - sp->spt) * sizeof(pt_element_t);
 927 
 928                         if (mmu_page_zap_pte(vcpu->kvm, sp, sptep))
 929                                 kvm_flush_remote_tlbs_with_address(vcpu->kvm,
 930                                         sp->gfn, KVM_PAGES_PER_HPAGE(sp->role.level));
 931 
 932                         if (!rmap_can_add(vcpu))
 933                                 break;
 934 
 935                         if (kvm_vcpu_read_guest_atomic(vcpu, pte_gpa, &gpte,
 936                                                        sizeof(pt_element_t)))
 937                                 break;
 938 
 939                         FNAME(update_pte)(vcpu, sp, sptep, &gpte);
 940                 }
 941 
 942                 if (!is_shadow_present_pte(*sptep) || !sp->unsync_children)
 943                         break;
 944         }
 945         spin_unlock(&vcpu->kvm->mmu_lock);
 946 }
 947 
 948 /* Note, @addr is a GPA when gva_to_gpa() translates an L2 GPA to an L1 GPA. */
 949 static gpa_t FNAME(gva_to_gpa)(struct kvm_vcpu *vcpu, gpa_t addr, u32 access,
 950                                struct x86_exception *exception)
 951 {
 952         struct guest_walker walker;
 953         gpa_t gpa = UNMAPPED_GVA;
 954         int r;
 955 
 956         r = FNAME(walk_addr)(&walker, vcpu, addr, access);
 957 
 958         if (r) {
 959                 gpa = gfn_to_gpa(walker.gfn);
 960                 gpa |= addr & ~PAGE_MASK;
 961         } else if (exception)
 962                 *exception = walker.fault;
 963 
 964         return gpa;
 965 }
 966 
 967 #if PTTYPE != PTTYPE_EPT
 968 /* Note, gva_to_gpa_nested() is only used to translate L2 GVAs. */
 969 static gpa_t FNAME(gva_to_gpa_nested)(struct kvm_vcpu *vcpu, gpa_t vaddr,
 970                                       u32 access,
 971                                       struct x86_exception *exception)
 972 {
 973         struct guest_walker walker;
 974         gpa_t gpa = UNMAPPED_GVA;
 975         int r;
 976 
 977 #ifndef CONFIG_X86_64
 978         /* A 64-bit GVA should be impossible on 32-bit KVM. */
 979         WARN_ON_ONCE(vaddr >> 32);
 980 #endif
 981 
 982         r = FNAME(walk_addr_nested)(&walker, vcpu, vaddr, access);
 983 
 984         if (r) {
 985                 gpa = gfn_to_gpa(walker.gfn);
 986                 gpa |= vaddr & ~PAGE_MASK;
 987         } else if (exception)
 988                 *exception = walker.fault;
 989 
 990         return gpa;
 991 }
 992 #endif
 993 
 994 /*
 995  * Using the cached information from sp->gfns is safe because:
 996  * - The spte has a reference to the struct page, so the pfn for a given gfn
 997  *   can't change unless all sptes pointing to it are nuked first.
 998  *
 999  * Note:
1000  *   We should flush all tlbs if spte is dropped even though guest is
1001  *   responsible for it. Since if we don't, kvm_mmu_notifier_invalidate_page
1002  *   and kvm_mmu_notifier_invalidate_range_start detect the mapping page isn't
1003  *   used by guest then tlbs are not flushed, so guest is allowed to access the
1004  *   freed pages.
1005  *   And we increase kvm->tlbs_dirty to delay tlbs flush in this case.
1006  */
1007 static int FNAME(sync_page)(struct kvm_vcpu *vcpu, struct kvm_mmu_page *sp)
1008 {
1009         int i, nr_present = 0;
1010         bool host_writable;
1011         gpa_t first_pte_gpa;
1012         int set_spte_ret = 0;
1013 
1014         /* direct kvm_mmu_page can not be unsync. */
1015         BUG_ON(sp->role.direct);
1016 
1017         first_pte_gpa = FNAME(get_level1_sp_gpa)(sp);
1018 
1019         for (i = 0; i < PT64_ENT_PER_PAGE; i++) {
1020                 unsigned pte_access;
1021                 pt_element_t gpte;
1022                 gpa_t pte_gpa;
1023                 gfn_t gfn;
1024 
1025                 if (!sp->spt[i])
1026                         continue;
1027 
1028                 pte_gpa = first_pte_gpa + i * sizeof(pt_element_t);
1029 
1030                 if (kvm_vcpu_read_guest_atomic(vcpu, pte_gpa, &gpte,
1031                                                sizeof(pt_element_t)))
1032                         return 0;
1033 
1034                 if (FNAME(prefetch_invalid_gpte)(vcpu, sp, &sp->spt[i], gpte)) {
1035                         /*
1036                          * Update spte before increasing tlbs_dirty to make
1037                          * sure no tlb flush is lost after spte is zapped; see
1038                          * the comments in kvm_flush_remote_tlbs().
1039                          */
1040                         smp_wmb();
1041                         vcpu->kvm->tlbs_dirty++;
1042                         continue;
1043                 }
1044 
1045                 gfn = gpte_to_gfn(gpte);
1046                 pte_access = sp->role.access;
1047                 pte_access &= FNAME(gpte_access)(gpte);
1048                 FNAME(protect_clean_gpte)(vcpu->arch.mmu, &pte_access, gpte);
1049 
1050                 if (sync_mmio_spte(vcpu, &sp->spt[i], gfn, pte_access,
1051                       &nr_present))
1052                         continue;
1053 
1054                 if (gfn != sp->gfns[i]) {
1055                         drop_spte(vcpu->kvm, &sp->spt[i]);
1056                         /*
1057                          * The same as above where we are doing
1058                          * prefetch_invalid_gpte().
1059                          */
1060                         smp_wmb();
1061                         vcpu->kvm->tlbs_dirty++;
1062                         continue;
1063                 }
1064 
1065                 nr_present++;
1066 
1067                 host_writable = sp->spt[i] & SPTE_HOST_WRITEABLE;
1068 
1069                 set_spte_ret |= set_spte(vcpu, &sp->spt[i],
1070                                          pte_access, PT_PAGE_TABLE_LEVEL,
1071                                          gfn, spte_to_pfn(sp->spt[i]),
1072                                          true, false, host_writable);
1073         }
1074 
1075         if (set_spte_ret & SET_SPTE_NEED_REMOTE_TLB_FLUSH)
1076                 kvm_flush_remote_tlbs(vcpu->kvm);
1077 
1078         return nr_present;
1079 }
1080 
1081 #undef pt_element_t
1082 #undef guest_walker
1083 #undef FNAME
1084 #undef PT_BASE_ADDR_MASK
1085 #undef PT_INDEX
1086 #undef PT_LVL_ADDR_MASK
1087 #undef PT_LVL_OFFSET_MASK
1088 #undef PT_LEVEL_BITS
1089 #undef PT_MAX_FULL_LEVELS
1090 #undef gpte_to_gfn
1091 #undef gpte_to_gfn_lvl
1092 #undef CMPXCHG
1093 #undef PT_GUEST_ACCESSED_MASK
1094 #undef PT_GUEST_DIRTY_MASK
1095 #undef PT_GUEST_DIRTY_SHIFT
1096 #undef PT_GUEST_ACCESSED_SHIFT
1097 #undef PT_HAVE_ACCESSED_DIRTY
/* [<][>][^][v][top][bottom][index][help] */
root/arch/x86/kvm/paging_tmpl.h

INCLUDED FROM

DEFINITIONS
