This source file includes following definitions.
- reprogram_fixed_counters
- global_ctrl_changed
- intel_find_arch_event
- intel_find_fixed_event
- intel_pmc_is_enabled
- intel_pmc_idx_to_pmc
- intel_is_valid_msr_idx
- intel_msr_idx_to_pmc
- intel_is_valid_msr
- intel_pmu_get_msr
- intel_pmu_set_msr
- intel_pmu_refresh
- intel_pmu_init
- intel_pmu_reset
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11 #include <linux/types.h>
12 #include <linux/kvm_host.h>
13 #include <linux/perf_event.h>
14 #include <asm/perf_event.h>
15 #include "x86.h"
16 #include "cpuid.h"
17 #include "lapic.h"
18 #include "pmu.h"
19
20 static struct kvm_event_hw_type_mapping intel_arch_events[] = {
21
22 [0] = { 0x3c, 0x00, PERF_COUNT_HW_CPU_CYCLES },
23 [1] = { 0xc0, 0x00, PERF_COUNT_HW_INSTRUCTIONS },
24 [2] = { 0x3c, 0x01, PERF_COUNT_HW_BUS_CYCLES },
25 [3] = { 0x2e, 0x4f, PERF_COUNT_HW_CACHE_REFERENCES },
26 [4] = { 0x2e, 0x41, PERF_COUNT_HW_CACHE_MISSES },
27 [5] = { 0xc4, 0x00, PERF_COUNT_HW_BRANCH_INSTRUCTIONS },
28 [6] = { 0xc5, 0x00, PERF_COUNT_HW_BRANCH_MISSES },
29 [7] = { 0x00, 0x30, PERF_COUNT_HW_REF_CPU_CYCLES },
30 };
31
32
33 static int fixed_pmc_events[] = {1, 0, 7};
34
35 static void reprogram_fixed_counters(struct kvm_pmu *pmu, u64 data)
36 {
37 int i;
38
39 for (i = 0; i < pmu->nr_arch_fixed_counters; i++) {
40 u8 new_ctrl = fixed_ctrl_field(data, i);
41 u8 old_ctrl = fixed_ctrl_field(pmu->fixed_ctr_ctrl, i);
42 struct kvm_pmc *pmc;
43
44 pmc = get_fixed_pmc(pmu, MSR_CORE_PERF_FIXED_CTR0 + i);
45
46 if (old_ctrl == new_ctrl)
47 continue;
48
49 reprogram_fixed_counter(pmc, new_ctrl, i);
50 }
51
52 pmu->fixed_ctr_ctrl = data;
53 }
54
55
56 static void global_ctrl_changed(struct kvm_pmu *pmu, u64 data)
57 {
58 int bit;
59 u64 diff = pmu->global_ctrl ^ data;
60
61 pmu->global_ctrl = data;
62
63 for_each_set_bit(bit, (unsigned long *)&diff, X86_PMC_IDX_MAX)
64 reprogram_counter(pmu, bit);
65 }
66
67 static unsigned intel_find_arch_event(struct kvm_pmu *pmu,
68 u8 event_select,
69 u8 unit_mask)
70 {
71 int i;
72
73 for (i = 0; i < ARRAY_SIZE(intel_arch_events); i++)
74 if (intel_arch_events[i].eventsel == event_select
75 && intel_arch_events[i].unit_mask == unit_mask
76 && (pmu->available_event_types & (1 << i)))
77 break;
78
79 if (i == ARRAY_SIZE(intel_arch_events))
80 return PERF_COUNT_HW_MAX;
81
82 return intel_arch_events[i].event_type;
83 }
84
85 static unsigned intel_find_fixed_event(int idx)
86 {
87 u32 event;
88 size_t size = ARRAY_SIZE(fixed_pmc_events);
89
90 if (idx >= size)
91 return PERF_COUNT_HW_MAX;
92
93 event = fixed_pmc_events[array_index_nospec(idx, size)];
94 return intel_arch_events[event].event_type;
95 }
96
97
98 static bool intel_pmc_is_enabled(struct kvm_pmc *pmc)
99 {
100 struct kvm_pmu *pmu = pmc_to_pmu(pmc);
101
102 return test_bit(pmc->idx, (unsigned long *)&pmu->global_ctrl);
103 }
104
105 static struct kvm_pmc *intel_pmc_idx_to_pmc(struct kvm_pmu *pmu, int pmc_idx)
106 {
107 if (pmc_idx < INTEL_PMC_IDX_FIXED)
108 return get_gp_pmc(pmu, MSR_P6_EVNTSEL0 + pmc_idx,
109 MSR_P6_EVNTSEL0);
110 else {
111 u32 idx = pmc_idx - INTEL_PMC_IDX_FIXED;
112
113 return get_fixed_pmc(pmu, idx + MSR_CORE_PERF_FIXED_CTR0);
114 }
115 }
116
117
118 static int intel_is_valid_msr_idx(struct kvm_vcpu *vcpu, unsigned idx)
119 {
120 struct kvm_pmu *pmu = vcpu_to_pmu(vcpu);
121 bool fixed = idx & (1u << 30);
122
123 idx &= ~(3u << 30);
124
125 return (!fixed && idx >= pmu->nr_arch_gp_counters) ||
126 (fixed && idx >= pmu->nr_arch_fixed_counters);
127 }
128
129 static struct kvm_pmc *intel_msr_idx_to_pmc(struct kvm_vcpu *vcpu,
130 unsigned idx, u64 *mask)
131 {
132 struct kvm_pmu *pmu = vcpu_to_pmu(vcpu);
133 bool fixed = idx & (1u << 30);
134 struct kvm_pmc *counters;
135 unsigned int num_counters;
136
137 idx &= ~(3u << 30);
138 if (fixed) {
139 counters = pmu->fixed_counters;
140 num_counters = pmu->nr_arch_fixed_counters;
141 } else {
142 counters = pmu->gp_counters;
143 num_counters = pmu->nr_arch_gp_counters;
144 }
145 if (idx >= num_counters)
146 return NULL;
147 *mask &= pmu->counter_bitmask[fixed ? KVM_PMC_FIXED : KVM_PMC_GP];
148 return &counters[array_index_nospec(idx, num_counters)];
149 }
150
151 static bool intel_is_valid_msr(struct kvm_vcpu *vcpu, u32 msr)
152 {
153 struct kvm_pmu *pmu = vcpu_to_pmu(vcpu);
154 int ret;
155
156 switch (msr) {
157 case MSR_CORE_PERF_FIXED_CTR_CTRL:
158 case MSR_CORE_PERF_GLOBAL_STATUS:
159 case MSR_CORE_PERF_GLOBAL_CTRL:
160 case MSR_CORE_PERF_GLOBAL_OVF_CTRL:
161 ret = pmu->version > 1;
162 break;
163 default:
164 ret = get_gp_pmc(pmu, msr, MSR_IA32_PERFCTR0) ||
165 get_gp_pmc(pmu, msr, MSR_P6_EVNTSEL0) ||
166 get_fixed_pmc(pmu, msr);
167 break;
168 }
169
170 return ret;
171 }
172
173 static int intel_pmu_get_msr(struct kvm_vcpu *vcpu, u32 msr, u64 *data)
174 {
175 struct kvm_pmu *pmu = vcpu_to_pmu(vcpu);
176 struct kvm_pmc *pmc;
177
178 switch (msr) {
179 case MSR_CORE_PERF_FIXED_CTR_CTRL:
180 *data = pmu->fixed_ctr_ctrl;
181 return 0;
182 case MSR_CORE_PERF_GLOBAL_STATUS:
183 *data = pmu->global_status;
184 return 0;
185 case MSR_CORE_PERF_GLOBAL_CTRL:
186 *data = pmu->global_ctrl;
187 return 0;
188 case MSR_CORE_PERF_GLOBAL_OVF_CTRL:
189 *data = pmu->global_ovf_ctrl;
190 return 0;
191 default:
192 if ((pmc = get_gp_pmc(pmu, msr, MSR_IA32_PERFCTR0))) {
193 u64 val = pmc_read_counter(pmc);
194 *data = val & pmu->counter_bitmask[KVM_PMC_GP];
195 return 0;
196 } else if ((pmc = get_fixed_pmc(pmu, msr))) {
197 u64 val = pmc_read_counter(pmc);
198 *data = val & pmu->counter_bitmask[KVM_PMC_FIXED];
199 return 0;
200 } else if ((pmc = get_gp_pmc(pmu, msr, MSR_P6_EVNTSEL0))) {
201 *data = pmc->eventsel;
202 return 0;
203 }
204 }
205
206 return 1;
207 }
208
209 static int intel_pmu_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
210 {
211 struct kvm_pmu *pmu = vcpu_to_pmu(vcpu);
212 struct kvm_pmc *pmc;
213 u32 msr = msr_info->index;
214 u64 data = msr_info->data;
215
216 switch (msr) {
217 case MSR_CORE_PERF_FIXED_CTR_CTRL:
218 if (pmu->fixed_ctr_ctrl == data)
219 return 0;
220 if (!(data & 0xfffffffffffff444ull)) {
221 reprogram_fixed_counters(pmu, data);
222 return 0;
223 }
224 break;
225 case MSR_CORE_PERF_GLOBAL_STATUS:
226 if (msr_info->host_initiated) {
227 pmu->global_status = data;
228 return 0;
229 }
230 break;
231 case MSR_CORE_PERF_GLOBAL_CTRL:
232 if (pmu->global_ctrl == data)
233 return 0;
234 if (!(data & pmu->global_ctrl_mask)) {
235 global_ctrl_changed(pmu, data);
236 return 0;
237 }
238 break;
239 case MSR_CORE_PERF_GLOBAL_OVF_CTRL:
240 if (!(data & pmu->global_ovf_ctrl_mask)) {
241 if (!msr_info->host_initiated)
242 pmu->global_status &= ~data;
243 pmu->global_ovf_ctrl = data;
244 return 0;
245 }
246 break;
247 default:
248 if ((pmc = get_gp_pmc(pmu, msr, MSR_IA32_PERFCTR0))) {
249 if (msr_info->host_initiated)
250 pmc->counter = data;
251 else
252 pmc->counter = (s32)data;
253 return 0;
254 } else if ((pmc = get_fixed_pmc(pmu, msr))) {
255 pmc->counter = data;
256 return 0;
257 } else if ((pmc = get_gp_pmc(pmu, msr, MSR_P6_EVNTSEL0))) {
258 if (data == pmc->eventsel)
259 return 0;
260 if (!(data & pmu->reserved_bits)) {
261 reprogram_gp_counter(pmc, data);
262 return 0;
263 }
264 }
265 }
266
267 return 1;
268 }
269
270 static void intel_pmu_refresh(struct kvm_vcpu *vcpu)
271 {
272 struct kvm_pmu *pmu = vcpu_to_pmu(vcpu);
273 struct x86_pmu_capability x86_pmu;
274 struct kvm_cpuid_entry2 *entry;
275 union cpuid10_eax eax;
276 union cpuid10_edx edx;
277
278 pmu->nr_arch_gp_counters = 0;
279 pmu->nr_arch_fixed_counters = 0;
280 pmu->counter_bitmask[KVM_PMC_GP] = 0;
281 pmu->counter_bitmask[KVM_PMC_FIXED] = 0;
282 pmu->version = 0;
283 pmu->reserved_bits = 0xffffffff00200000ull;
284
285 entry = kvm_find_cpuid_entry(vcpu, 0xa, 0);
286 if (!entry)
287 return;
288 eax.full = entry->eax;
289 edx.full = entry->edx;
290
291 pmu->version = eax.split.version_id;
292 if (!pmu->version)
293 return;
294
295 perf_get_x86_pmu_capability(&x86_pmu);
296
297 pmu->nr_arch_gp_counters = min_t(int, eax.split.num_counters,
298 x86_pmu.num_counters_gp);
299 pmu->counter_bitmask[KVM_PMC_GP] = ((u64)1 << eax.split.bit_width) - 1;
300 pmu->available_event_types = ~entry->ebx &
301 ((1ull << eax.split.mask_length) - 1);
302
303 if (pmu->version == 1) {
304 pmu->nr_arch_fixed_counters = 0;
305 } else {
306 pmu->nr_arch_fixed_counters =
307 min_t(int, edx.split.num_counters_fixed,
308 x86_pmu.num_counters_fixed);
309 pmu->counter_bitmask[KVM_PMC_FIXED] =
310 ((u64)1 << edx.split.bit_width_fixed) - 1;
311 }
312
313 pmu->global_ctrl = ((1ull << pmu->nr_arch_gp_counters) - 1) |
314 (((1ull << pmu->nr_arch_fixed_counters) - 1) << INTEL_PMC_IDX_FIXED);
315 pmu->global_ctrl_mask = ~pmu->global_ctrl;
316 pmu->global_ovf_ctrl_mask = pmu->global_ctrl_mask
317 & ~(MSR_CORE_PERF_GLOBAL_OVF_CTRL_OVF_BUF |
318 MSR_CORE_PERF_GLOBAL_OVF_CTRL_COND_CHGD);
319 if (kvm_x86_ops->pt_supported())
320 pmu->global_ovf_ctrl_mask &=
321 ~MSR_CORE_PERF_GLOBAL_OVF_CTRL_TRACE_TOPA_PMI;
322
323 entry = kvm_find_cpuid_entry(vcpu, 7, 0);
324 if (entry &&
325 (boot_cpu_has(X86_FEATURE_HLE) || boot_cpu_has(X86_FEATURE_RTM)) &&
326 (entry->ebx & (X86_FEATURE_HLE|X86_FEATURE_RTM)))
327 pmu->reserved_bits ^= HSW_IN_TX|HSW_IN_TX_CHECKPOINTED;
328 }
329
330 static void intel_pmu_init(struct kvm_vcpu *vcpu)
331 {
332 int i;
333 struct kvm_pmu *pmu = vcpu_to_pmu(vcpu);
334
335 for (i = 0; i < INTEL_PMC_MAX_GENERIC; i++) {
336 pmu->gp_counters[i].type = KVM_PMC_GP;
337 pmu->gp_counters[i].vcpu = vcpu;
338 pmu->gp_counters[i].idx = i;
339 }
340
341 for (i = 0; i < INTEL_PMC_MAX_FIXED; i++) {
342 pmu->fixed_counters[i].type = KVM_PMC_FIXED;
343 pmu->fixed_counters[i].vcpu = vcpu;
344 pmu->fixed_counters[i].idx = i + INTEL_PMC_IDX_FIXED;
345 }
346 }
347
348 static void intel_pmu_reset(struct kvm_vcpu *vcpu)
349 {
350 struct kvm_pmu *pmu = vcpu_to_pmu(vcpu);
351 struct kvm_pmc *pmc = NULL;
352 int i;
353
354 for (i = 0; i < INTEL_PMC_MAX_GENERIC; i++) {
355 pmc = &pmu->gp_counters[i];
356
357 pmc_stop_counter(pmc);
358 pmc->counter = pmc->eventsel = 0;
359 }
360
361 for (i = 0; i < INTEL_PMC_MAX_FIXED; i++) {
362 pmc = &pmu->fixed_counters[i];
363
364 pmc_stop_counter(pmc);
365 pmc->counter = 0;
366 }
367
368 pmu->fixed_ctr_ctrl = pmu->global_ctrl = pmu->global_status =
369 pmu->global_ovf_ctrl = 0;
370 }
371
372 struct kvm_pmu_ops intel_pmu_ops = {
373 .find_arch_event = intel_find_arch_event,
374 .find_fixed_event = intel_find_fixed_event,
375 .pmc_is_enabled = intel_pmc_is_enabled,
376 .pmc_idx_to_pmc = intel_pmc_idx_to_pmc,
377 .msr_idx_to_pmc = intel_msr_idx_to_pmc,
378 .is_valid_msr_idx = intel_is_valid_msr_idx,
379 .is_valid_msr = intel_is_valid_msr,
380 .get_msr = intel_pmu_get_msr,
381 .set_msr = intel_pmu_set_msr,
382 .refresh = intel_pmu_refresh,
383 .init = intel_pmu_init,
384 .reset = intel_pmu_reset,
385 };