arch/riscv/include/asm/io.h

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This source file includes following definitions.
__raw_writeb
__raw_writew
__raw_writel
__raw_writeq
__raw_readb
__raw_readw
__raw_readl
__raw_readq
   1 /* SPDX-License-Identifier: GPL-2.0-only */
   2 /*
   3  * {read,write}{b,w,l,q} based on arch/arm64/include/asm/io.h
   4  *   which was based on arch/arm/include/io.h
   5  *
   6  * Copyright (C) 1996-2000 Russell King
   7  * Copyright (C) 2012 ARM Ltd.
   8  * Copyright (C) 2014 Regents of the University of California
   9  */
  10 
  11 #ifndef _ASM_RISCV_IO_H
  12 #define _ASM_RISCV_IO_H
  13 
  14 #include <linux/types.h>
  15 #include <asm/mmiowb.h>
  16 #include <asm/pgtable.h>
  17 
  18 extern void __iomem *ioremap(phys_addr_t offset, unsigned long size);
  19 
  20 /*
  21  * The RISC-V ISA doesn't yet specify how to query or modify PMAs, so we can't
  22  * change the properties of memory regions.  This should be fixed by the
  23  * upcoming platform spec.
  24  */
  25 #define ioremap_nocache(addr, size) ioremap((addr), (size))
  26 #define ioremap_wc(addr, size) ioremap((addr), (size))
  27 #define ioremap_wt(addr, size) ioremap((addr), (size))
  28 
  29 extern void iounmap(volatile void __iomem *addr);
  30 
  31 /* Generic IO read/write.  These perform native-endian accesses. */
  32 #define __raw_writeb __raw_writeb
  33 static inline void __raw_writeb(u8 val, volatile void __iomem *addr)
  34 {
  35         asm volatile("sb %0, 0(%1)" : : "r" (val), "r" (addr));
  36 }
  37 
  38 #define __raw_writew __raw_writew
  39 static inline void __raw_writew(u16 val, volatile void __iomem *addr)
  40 {
  41         asm volatile("sh %0, 0(%1)" : : "r" (val), "r" (addr));
  42 }
  43 
  44 #define __raw_writel __raw_writel
  45 static inline void __raw_writel(u32 val, volatile void __iomem *addr)
  46 {
  47         asm volatile("sw %0, 0(%1)" : : "r" (val), "r" (addr));
  48 }
  49 
  50 #ifdef CONFIG_64BIT
  51 #define __raw_writeq __raw_writeq
  52 static inline void __raw_writeq(u64 val, volatile void __iomem *addr)
  53 {
  54         asm volatile("sd %0, 0(%1)" : : "r" (val), "r" (addr));
  55 }
  56 #endif
  57 
  58 #define __raw_readb __raw_readb
  59 static inline u8 __raw_readb(const volatile void __iomem *addr)
  60 {
  61         u8 val;
  62 
  63         asm volatile("lb %0, 0(%1)" : "=r" (val) : "r" (addr));
  64         return val;
  65 }
  66 
  67 #define __raw_readw __raw_readw
  68 static inline u16 __raw_readw(const volatile void __iomem *addr)
  69 {
  70         u16 val;
  71 
  72         asm volatile("lh %0, 0(%1)" : "=r" (val) : "r" (addr));
  73         return val;
  74 }
  75 
  76 #define __raw_readl __raw_readl
  77 static inline u32 __raw_readl(const volatile void __iomem *addr)
  78 {
  79         u32 val;
  80 
  81         asm volatile("lw %0, 0(%1)" : "=r" (val) : "r" (addr));
  82         return val;
  83 }
  84 
  85 #ifdef CONFIG_64BIT
  86 #define __raw_readq __raw_readq
  87 static inline u64 __raw_readq(const volatile void __iomem *addr)
  88 {
  89         u64 val;
  90 
  91         asm volatile("ld %0, 0(%1)" : "=r" (val) : "r" (addr));
  92         return val;
  93 }
  94 #endif
  95 
  96 /*
  97  * Unordered I/O memory access primitives.  These are even more relaxed than
  98  * the relaxed versions, as they don't even order accesses between successive
  99  * operations to the I/O regions.
 100  */
 101 #define readb_cpu(c)            ({ u8  __r = __raw_readb(c); __r; })
 102 #define readw_cpu(c)            ({ u16 __r = le16_to_cpu((__force __le16)__raw_readw(c)); __r; })
 103 #define readl_cpu(c)            ({ u32 __r = le32_to_cpu((__force __le32)__raw_readl(c)); __r; })
 104 
 105 #define writeb_cpu(v,c)         ((void)__raw_writeb((v),(c)))
 106 #define writew_cpu(v,c)         ((void)__raw_writew((__force u16)cpu_to_le16(v),(c)))
 107 #define writel_cpu(v,c)         ((void)__raw_writel((__force u32)cpu_to_le32(v),(c)))
 108 
 109 #ifdef CONFIG_64BIT
 110 #define readq_cpu(c)            ({ u64 __r = le64_to_cpu((__force __le64)__raw_readq(c)); __r; })
 111 #define writeq_cpu(v,c)         ((void)__raw_writeq((__force u64)cpu_to_le64(v),(c)))
 112 #endif
 113 
 114 /*
 115  * Relaxed I/O memory access primitives. These follow the Device memory
 116  * ordering rules but do not guarantee any ordering relative to Normal memory
 117  * accesses.  These are defined to order the indicated access (either a read or
 118  * write) with all other I/O memory accesses. Since the platform specification
 119  * defines that all I/O regions are strongly ordered on channel 2, no explicit
 120  * fences are required to enforce this ordering.
 121  */
 122 /* FIXME: These are now the same as asm-generic */
 123 #define __io_rbr()              do {} while (0)
 124 #define __io_rar()              do {} while (0)
 125 #define __io_rbw()              do {} while (0)
 126 #define __io_raw()              do {} while (0)
 127 
 128 #define readb_relaxed(c)        ({ u8  __v; __io_rbr(); __v = readb_cpu(c); __io_rar(); __v; })
 129 #define readw_relaxed(c)        ({ u16 __v; __io_rbr(); __v = readw_cpu(c); __io_rar(); __v; })
 130 #define readl_relaxed(c)        ({ u32 __v; __io_rbr(); __v = readl_cpu(c); __io_rar(); __v; })
 131 
 132 #define writeb_relaxed(v,c)     ({ __io_rbw(); writeb_cpu((v),(c)); __io_raw(); })
 133 #define writew_relaxed(v,c)     ({ __io_rbw(); writew_cpu((v),(c)); __io_raw(); })
 134 #define writel_relaxed(v,c)     ({ __io_rbw(); writel_cpu((v),(c)); __io_raw(); })
 135 
 136 #ifdef CONFIG_64BIT
 137 #define readq_relaxed(c)        ({ u64 __v; __io_rbr(); __v = readq_cpu(c); __io_rar(); __v; })
 138 #define writeq_relaxed(v,c)     ({ __io_rbw(); writeq_cpu((v),(c)); __io_raw(); })
 139 #endif
 140 
 141 /*
 142  * I/O memory access primitives. Reads are ordered relative to any
 143  * following Normal memory access. Writes are ordered relative to any prior
 144  * Normal memory access.  The memory barriers here are necessary as RISC-V
 145  * doesn't define any ordering between the memory space and the I/O space.
 146  */
 147 #define __io_br()       do {} while (0)
 148 #define __io_ar(v)      __asm__ __volatile__ ("fence i,r" : : : "memory");
 149 #define __io_bw()       __asm__ __volatile__ ("fence w,o" : : : "memory");
 150 #define __io_aw()       mmiowb_set_pending()
 151 
 152 #define readb(c)        ({ u8  __v; __io_br(); __v = readb_cpu(c); __io_ar(__v); __v; })
 153 #define readw(c)        ({ u16 __v; __io_br(); __v = readw_cpu(c); __io_ar(__v); __v; })
 154 #define readl(c)        ({ u32 __v; __io_br(); __v = readl_cpu(c); __io_ar(__v); __v; })
 155 
 156 #define writeb(v,c)     ({ __io_bw(); writeb_cpu((v),(c)); __io_aw(); })
 157 #define writew(v,c)     ({ __io_bw(); writew_cpu((v),(c)); __io_aw(); })
 158 #define writel(v,c)     ({ __io_bw(); writel_cpu((v),(c)); __io_aw(); })
 159 
 160 #ifdef CONFIG_64BIT
 161 #define readq(c)        ({ u64 __v; __io_br(); __v = readq_cpu(c); __io_ar(__v); __v; })
 162 #define writeq(v,c)     ({ __io_bw(); writeq_cpu((v),(c)); __io_aw(); })
 163 #endif
 164 
 165 /*
 166  *  I/O port access constants.
 167  */
 168 #define IO_SPACE_LIMIT          (PCI_IO_SIZE - 1)
 169 #define PCI_IOBASE              ((void __iomem *)PCI_IO_START)
 170 
 171 /*
 172  * Emulation routines for the port-mapped IO space used by some PCI drivers.
 173  * These are defined as being "fully synchronous", but also "not guaranteed to
 174  * be fully ordered with respect to other memory and I/O operations".  We're
 175  * going to be on the safe side here and just make them:
 176  *  - Fully ordered WRT each other, by bracketing them with two fences.  The
 177  *    outer set contains both I/O so inX is ordered with outX, while the inner just
 178  *    needs the type of the access (I for inX and O for outX).
 179  *  - Ordered in the same manner as readX/writeX WRT memory by subsuming their
 180  *    fences.
 181  *  - Ordered WRT timer reads, so udelay and friends don't get elided by the
 182  *    implementation.
 183  * Note that there is no way to actually enforce that outX is a non-posted
 184  * operation on RISC-V, but hopefully the timer ordering constraint is
 185  * sufficient to ensure this works sanely on controllers that support I/O
 186  * writes.
 187  */
 188 #define __io_pbr()      __asm__ __volatile__ ("fence io,i"  : : : "memory");
 189 #define __io_par(v)     __asm__ __volatile__ ("fence i,ior" : : : "memory");
 190 #define __io_pbw()      __asm__ __volatile__ ("fence iow,o" : : : "memory");
 191 #define __io_paw()      __asm__ __volatile__ ("fence o,io"  : : : "memory");
 192 
 193 #define inb(c)          ({ u8  __v; __io_pbr(); __v = readb_cpu((void*)(PCI_IOBASE + (c))); __io_par(__v); __v; })
 194 #define inw(c)          ({ u16 __v; __io_pbr(); __v = readw_cpu((void*)(PCI_IOBASE + (c))); __io_par(__v); __v; })
 195 #define inl(c)          ({ u32 __v; __io_pbr(); __v = readl_cpu((void*)(PCI_IOBASE + (c))); __io_par(__v); __v; })
 196 
 197 #define outb(v,c)       ({ __io_pbw(); writeb_cpu((v),(void*)(PCI_IOBASE + (c))); __io_paw(); })
 198 #define outw(v,c)       ({ __io_pbw(); writew_cpu((v),(void*)(PCI_IOBASE + (c))); __io_paw(); })
 199 #define outl(v,c)       ({ __io_pbw(); writel_cpu((v),(void*)(PCI_IOBASE + (c))); __io_paw(); })
 200 
 201 #ifdef CONFIG_64BIT
 202 #define inq(c)          ({ u64 __v; __io_pbr(); __v = readq_cpu((void*)(c)); __io_par(__v); __v; })
 203 #define outq(v,c)       ({ __io_pbw(); writeq_cpu((v),(void*)(c)); __io_paw(); })
 204 #endif
 205 
 206 /*
 207  * Accesses from a single hart to a single I/O address must be ordered.  This
 208  * allows us to use the raw read macros, but we still need to fence before and
 209  * after the block to ensure ordering WRT other macros.  These are defined to
 210  * perform host-endian accesses so we use __raw instead of __cpu.
 211  */
 212 #define __io_reads_ins(port, ctype, len, bfence, afence)                        \
 213         static inline void __ ## port ## len(const volatile void __iomem *addr, \
 214                                              void *buffer,                      \
 215                                              unsigned int count)                \
 216         {                                                                       \
 217                 bfence;                                                         \
 218                 if (count) {                                                    \
 219                         ctype *buf = buffer;                                    \
 220                                                                                 \
 221                         do {                                                    \
 222                                 ctype x = __raw_read ## len(addr);              \
 223                                 *buf++ = x;                                     \
 224                         } while (--count);                                      \
 225                 }                                                               \
 226                 afence;                                                         \
 227         }
 228 
 229 #define __io_writes_outs(port, ctype, len, bfence, afence)                      \
 230         static inline void __ ## port ## len(volatile void __iomem *addr,       \
 231                                              const void *buffer,                \
 232                                              unsigned int count)                \
 233         {                                                                       \
 234                 bfence;                                                         \
 235                 if (count) {                                                    \
 236                         const ctype *buf = buffer;                              \
 237                                                                                 \
 238                         do {                                                    \
 239                                 __raw_write ## len(*buf++, addr);               \
 240                         } while (--count);                                      \
 241                 }                                                               \
 242                 afence;                                                         \
 243         }
 244 
 245 __io_reads_ins(reads,  u8, b, __io_br(), __io_ar(addr))
 246 __io_reads_ins(reads, u16, w, __io_br(), __io_ar(addr))
 247 __io_reads_ins(reads, u32, l, __io_br(), __io_ar(addr))
 248 #define readsb(addr, buffer, count) __readsb(addr, buffer, count)
 249 #define readsw(addr, buffer, count) __readsw(addr, buffer, count)
 250 #define readsl(addr, buffer, count) __readsl(addr, buffer, count)
 251 
 252 __io_reads_ins(ins,  u8, b, __io_pbr(), __io_par(addr))
 253 __io_reads_ins(ins, u16, w, __io_pbr(), __io_par(addr))
 254 __io_reads_ins(ins, u32, l, __io_pbr(), __io_par(addr))
 255 #define insb(addr, buffer, count) __insb((void __iomem *)(long)addr, buffer, count)
 256 #define insw(addr, buffer, count) __insw((void __iomem *)(long)addr, buffer, count)
 257 #define insl(addr, buffer, count) __insl((void __iomem *)(long)addr, buffer, count)
 258 
 259 __io_writes_outs(writes,  u8, b, __io_bw(), __io_aw())
 260 __io_writes_outs(writes, u16, w, __io_bw(), __io_aw())
 261 __io_writes_outs(writes, u32, l, __io_bw(), __io_aw())
 262 #define writesb(addr, buffer, count) __writesb(addr, buffer, count)
 263 #define writesw(addr, buffer, count) __writesw(addr, buffer, count)
 264 #define writesl(addr, buffer, count) __writesl(addr, buffer, count)
 265 
 266 __io_writes_outs(outs,  u8, b, __io_pbw(), __io_paw())
 267 __io_writes_outs(outs, u16, w, __io_pbw(), __io_paw())
 268 __io_writes_outs(outs, u32, l, __io_pbw(), __io_paw())
 269 #define outsb(addr, buffer, count) __outsb((void __iomem *)(long)addr, buffer, count)
 270 #define outsw(addr, buffer, count) __outsw((void __iomem *)(long)addr, buffer, count)
 271 #define outsl(addr, buffer, count) __outsl((void __iomem *)(long)addr, buffer, count)
 272 
 273 #ifdef CONFIG_64BIT
 274 __io_reads_ins(reads, u64, q, __io_br(), __io_ar(addr))
 275 #define readsq(addr, buffer, count) __readsq(addr, buffer, count)
 276 
 277 __io_reads_ins(ins, u64, q, __io_pbr(), __io_par(addr))
 278 #define insq(addr, buffer, count) __insq((void __iomem *)addr, buffer, count)
 279 
 280 __io_writes_outs(writes, u64, q, __io_bw(), __io_aw())
 281 #define writesq(addr, buffer, count) __writesq(addr, buffer, count)
 282 
 283 __io_writes_outs(outs, u64, q, __io_pbr(), __io_paw())
 284 #define outsq(addr, buffer, count) __outsq((void __iomem *)addr, buffer, count)
 285 #endif
 286 
 287 #include <asm-generic/io.h>
 288 
 289 #endif /* _ASM_RISCV_IO_H */
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root/arch/riscv/include/asm/io.h

INCLUDED FROM

DEFINITIONS
