This source file includes following definitions.
- x86_perf_event_update
- x86_pmu_extra_regs
- reserve_pmc_hardware
- release_pmc_hardware
- reserve_pmc_hardware
- release_pmc_hardware
- check_hw_exists
- hw_perf_event_destroy
- hw_perf_lbr_event_destroy
- x86_pmu_initialized
- set_ext_hw_attr
- x86_reserve_hardware
- x86_release_hardware
- x86_add_exclusive
- x86_del_exclusive
- x86_setup_perfctr
- precise_br_compat
- x86_pmu_max_precise
- x86_pmu_hw_config
- __x86_pmu_event_init
- x86_pmu_disable_all
- x86_pmu_disable
- x86_pmu_enable_all
- is_x86_event
- x86_get_pmu
- perf_sched_init
- perf_sched_save_state
- perf_sched_restore_state
- __perf_sched_find_counter
- perf_sched_find_counter
- perf_sched_next_event
- perf_assign_events
- x86_schedule_events
- collect_events
- x86_assign_hw_event
- x86_perf_rdpmc_index
- match_prev_assignment
- x86_pmu_enable
- x86_perf_event_set_period
- x86_pmu_enable_event
- x86_pmu_add
- x86_pmu_start
- perf_event_print_debug
- x86_pmu_stop
- x86_pmu_del
- x86_pmu_handle_irq
- perf_events_lapic_init
- perf_event_nmi_handler
- x86_pmu_prepare_cpu
- x86_pmu_dead_cpu
- x86_pmu_online_cpu
- x86_pmu_starting_cpu
- x86_pmu_dying_cpu
- pmu_check_apic
- events_sysfs_show
- events_ht_sysfs_show
- is_visible
- x86_event_sysfs_show
- init_hw_perf_events
- x86_pmu_read
- x86_pmu_start_txn
- x86_pmu_cancel_txn
- x86_pmu_commit_txn
- free_fake_cpuc
- allocate_fake_cpuc
- validate_event
- validate_group
- x86_pmu_event_init
- refresh_pce
- x86_pmu_event_mapped
- x86_pmu_event_unmapped
- x86_pmu_event_idx
- get_attr_rdpmc
- set_attr_rdpmc
- max_precise_show
- x86_pmu_sched_task
- perf_check_microcode
- x86_pmu_check_period
- x86_pmu_aux_output_match
- arch_perf_update_userpage
- perf_hw_regs
- perf_callchain_kernel
- valid_user_frame
- get_segment_base
- perf_callchain_user32
- perf_callchain_user32
- perf_callchain_user
- code_segment_base
- perf_instruction_pointer
- perf_misc_flags
- perf_get_x86_pmu_capability
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15 #include <linux/perf_event.h>
16 #include <linux/capability.h>
17 #include <linux/notifier.h>
18 #include <linux/hardirq.h>
19 #include <linux/kprobes.h>
20 #include <linux/export.h>
21 #include <linux/init.h>
22 #include <linux/kdebug.h>
23 #include <linux/sched/mm.h>
24 #include <linux/sched/clock.h>
25 #include <linux/uaccess.h>
26 #include <linux/slab.h>
27 #include <linux/cpu.h>
28 #include <linux/bitops.h>
29 #include <linux/device.h>
30 #include <linux/nospec.h>
31
32 #include <asm/apic.h>
33 #include <asm/stacktrace.h>
34 #include <asm/nmi.h>
35 #include <asm/smp.h>
36 #include <asm/alternative.h>
37 #include <asm/mmu_context.h>
38 #include <asm/tlbflush.h>
39 #include <asm/timer.h>
40 #include <asm/desc.h>
41 #include <asm/ldt.h>
42 #include <asm/unwind.h>
43
44 #include "perf_event.h"
45
46 struct x86_pmu x86_pmu __read_mostly;
47
48 DEFINE_PER_CPU(struct cpu_hw_events, cpu_hw_events) = {
49 .enabled = 1,
50 };
51
52 DEFINE_STATIC_KEY_FALSE(rdpmc_always_available_key);
53
54 u64 __read_mostly hw_cache_event_ids
55 [PERF_COUNT_HW_CACHE_MAX]
56 [PERF_COUNT_HW_CACHE_OP_MAX]
57 [PERF_COUNT_HW_CACHE_RESULT_MAX];
58 u64 __read_mostly hw_cache_extra_regs
59 [PERF_COUNT_HW_CACHE_MAX]
60 [PERF_COUNT_HW_CACHE_OP_MAX]
61 [PERF_COUNT_HW_CACHE_RESULT_MAX];
62
63
64
65
66
67
68 u64 x86_perf_event_update(struct perf_event *event)
69 {
70 struct hw_perf_event *hwc = &event->hw;
71 int shift = 64 - x86_pmu.cntval_bits;
72 u64 prev_raw_count, new_raw_count;
73 int idx = hwc->idx;
74 u64 delta;
75
76 if (idx == INTEL_PMC_IDX_FIXED_BTS)
77 return 0;
78
79
80
81
82
83
84
85
86 again:
87 prev_raw_count = local64_read(&hwc->prev_count);
88 rdpmcl(hwc->event_base_rdpmc, new_raw_count);
89
90 if (local64_cmpxchg(&hwc->prev_count, prev_raw_count,
91 new_raw_count) != prev_raw_count)
92 goto again;
93
94
95
96
97
98
99
100
101
102 delta = (new_raw_count << shift) - (prev_raw_count << shift);
103 delta >>= shift;
104
105 local64_add(delta, &event->count);
106 local64_sub(delta, &hwc->period_left);
107
108 return new_raw_count;
109 }
110
111
112
113
114 static int x86_pmu_extra_regs(u64 config, struct perf_event *event)
115 {
116 struct hw_perf_event_extra *reg;
117 struct extra_reg *er;
118
119 reg = &event->hw.extra_reg;
120
121 if (!x86_pmu.extra_regs)
122 return 0;
123
124 for (er = x86_pmu.extra_regs; er->msr; er++) {
125 if (er->event != (config & er->config_mask))
126 continue;
127 if (event->attr.config1 & ~er->valid_mask)
128 return -EINVAL;
129
130 if (!er->extra_msr_access)
131 return -ENXIO;
132
133 reg->idx = er->idx;
134 reg->config = event->attr.config1;
135 reg->reg = er->msr;
136 break;
137 }
138 return 0;
139 }
140
141 static atomic_t active_events;
142 static atomic_t pmc_refcount;
143 static DEFINE_MUTEX(pmc_reserve_mutex);
144
145 #ifdef CONFIG_X86_LOCAL_APIC
146
147 static bool reserve_pmc_hardware(void)
148 {
149 int i;
150
151 for (i = 0; i < x86_pmu.num_counters; i++) {
152 if (!reserve_perfctr_nmi(x86_pmu_event_addr(i)))
153 goto perfctr_fail;
154 }
155
156 for (i = 0; i < x86_pmu.num_counters; i++) {
157 if (!reserve_evntsel_nmi(x86_pmu_config_addr(i)))
158 goto eventsel_fail;
159 }
160
161 return true;
162
163 eventsel_fail:
164 for (i--; i >= 0; i--)
165 release_evntsel_nmi(x86_pmu_config_addr(i));
166
167 i = x86_pmu.num_counters;
168
169 perfctr_fail:
170 for (i--; i >= 0; i--)
171 release_perfctr_nmi(x86_pmu_event_addr(i));
172
173 return false;
174 }
175
176 static void release_pmc_hardware(void)
177 {
178 int i;
179
180 for (i = 0; i < x86_pmu.num_counters; i++) {
181 release_perfctr_nmi(x86_pmu_event_addr(i));
182 release_evntsel_nmi(x86_pmu_config_addr(i));
183 }
184 }
185
186 #else
187
188 static bool reserve_pmc_hardware(void) { return true; }
189 static void release_pmc_hardware(void) {}
190
191 #endif
192
193 static bool check_hw_exists(void)
194 {
195 u64 val, val_fail = -1, val_new= ~0;
196 int i, reg, reg_fail = -1, ret = 0;
197 int bios_fail = 0;
198 int reg_safe = -1;
199
200
201
202
203
204 for (i = 0; i < x86_pmu.num_counters; i++) {
205 reg = x86_pmu_config_addr(i);
206 ret = rdmsrl_safe(reg, &val);
207 if (ret)
208 goto msr_fail;
209 if (val & ARCH_PERFMON_EVENTSEL_ENABLE) {
210 bios_fail = 1;
211 val_fail = val;
212 reg_fail = reg;
213 } else {
214 reg_safe = i;
215 }
216 }
217
218 if (x86_pmu.num_counters_fixed) {
219 reg = MSR_ARCH_PERFMON_FIXED_CTR_CTRL;
220 ret = rdmsrl_safe(reg, &val);
221 if (ret)
222 goto msr_fail;
223 for (i = 0; i < x86_pmu.num_counters_fixed; i++) {
224 if (val & (0x03 << i*4)) {
225 bios_fail = 1;
226 val_fail = val;
227 reg_fail = reg;
228 }
229 }
230 }
231
232
233
234
235
236
237
238 if (reg_safe == -1) {
239 reg = reg_safe;
240 goto msr_fail;
241 }
242
243
244
245
246
247
248 reg = x86_pmu_event_addr(reg_safe);
249 if (rdmsrl_safe(reg, &val))
250 goto msr_fail;
251 val ^= 0xffffUL;
252 ret = wrmsrl_safe(reg, val);
253 ret |= rdmsrl_safe(reg, &val_new);
254 if (ret || val != val_new)
255 goto msr_fail;
256
257
258
259
260 if (bios_fail) {
261 pr_cont("Broken BIOS detected, complain to your hardware vendor.\n");
262 pr_err(FW_BUG "the BIOS has corrupted hw-PMU resources (MSR %x is %Lx)\n",
263 reg_fail, val_fail);
264 }
265
266 return true;
267
268 msr_fail:
269 if (boot_cpu_has(X86_FEATURE_HYPERVISOR)) {
270 pr_cont("PMU not available due to virtualization, using software events only.\n");
271 } else {
272 pr_cont("Broken PMU hardware detected, using software events only.\n");
273 pr_err("Failed to access perfctr msr (MSR %x is %Lx)\n",
274 reg, val_new);
275 }
276
277 return false;
278 }
279
280 static void hw_perf_event_destroy(struct perf_event *event)
281 {
282 x86_release_hardware();
283 atomic_dec(&active_events);
284 }
285
286 void hw_perf_lbr_event_destroy(struct perf_event *event)
287 {
288 hw_perf_event_destroy(event);
289
290
291 x86_del_exclusive(x86_lbr_exclusive_lbr);
292 }
293
294 static inline int x86_pmu_initialized(void)
295 {
296 return x86_pmu.handle_irq != NULL;
297 }
298
299 static inline int
300 set_ext_hw_attr(struct hw_perf_event *hwc, struct perf_event *event)
301 {
302 struct perf_event_attr *attr = &event->attr;
303 unsigned int cache_type, cache_op, cache_result;
304 u64 config, val;
305
306 config = attr->config;
307
308 cache_type = (config >> 0) & 0xff;
309 if (cache_type >= PERF_COUNT_HW_CACHE_MAX)
310 return -EINVAL;
311 cache_type = array_index_nospec(cache_type, PERF_COUNT_HW_CACHE_MAX);
312
313 cache_op = (config >> 8) & 0xff;
314 if (cache_op >= PERF_COUNT_HW_CACHE_OP_MAX)
315 return -EINVAL;
316 cache_op = array_index_nospec(cache_op, PERF_COUNT_HW_CACHE_OP_MAX);
317
318 cache_result = (config >> 16) & 0xff;
319 if (cache_result >= PERF_COUNT_HW_CACHE_RESULT_MAX)
320 return -EINVAL;
321 cache_result = array_index_nospec(cache_result, PERF_COUNT_HW_CACHE_RESULT_MAX);
322
323 val = hw_cache_event_ids[cache_type][cache_op][cache_result];
324
325 if (val == 0)
326 return -ENOENT;
327
328 if (val == -1)
329 return -EINVAL;
330
331 hwc->config |= val;
332 attr->config1 = hw_cache_extra_regs[cache_type][cache_op][cache_result];
333 return x86_pmu_extra_regs(val, event);
334 }
335
336 int x86_reserve_hardware(void)
337 {
338 int err = 0;
339
340 if (!atomic_inc_not_zero(&pmc_refcount)) {
341 mutex_lock(&pmc_reserve_mutex);
342 if (atomic_read(&pmc_refcount) == 0) {
343 if (!reserve_pmc_hardware())
344 err = -EBUSY;
345 else
346 reserve_ds_buffers();
347 }
348 if (!err)
349 atomic_inc(&pmc_refcount);
350 mutex_unlock(&pmc_reserve_mutex);
351 }
352
353 return err;
354 }
355
356 void x86_release_hardware(void)
357 {
358 if (atomic_dec_and_mutex_lock(&pmc_refcount, &pmc_reserve_mutex)) {
359 release_pmc_hardware();
360 release_ds_buffers();
361 mutex_unlock(&pmc_reserve_mutex);
362 }
363 }
364
365
366
367
368
369 int x86_add_exclusive(unsigned int what)
370 {
371 int i;
372
373
374
375
376
377 if (x86_pmu.lbr_pt_coexist && what == x86_lbr_exclusive_pt)
378 goto out;
379
380 if (!atomic_inc_not_zero(&x86_pmu.lbr_exclusive[what])) {
381 mutex_lock(&pmc_reserve_mutex);
382 for (i = 0; i < ARRAY_SIZE(x86_pmu.lbr_exclusive); i++) {
383 if (i != what && atomic_read(&x86_pmu.lbr_exclusive[i]))
384 goto fail_unlock;
385 }
386 atomic_inc(&x86_pmu.lbr_exclusive[what]);
387 mutex_unlock(&pmc_reserve_mutex);
388 }
389
390 out:
391 atomic_inc(&active_events);
392 return 0;
393
394 fail_unlock:
395 mutex_unlock(&pmc_reserve_mutex);
396 return -EBUSY;
397 }
398
399 void x86_del_exclusive(unsigned int what)
400 {
401 atomic_dec(&active_events);
402
403
404
405
406 if (x86_pmu.lbr_pt_coexist && what == x86_lbr_exclusive_pt)
407 return;
408
409 atomic_dec(&x86_pmu.lbr_exclusive[what]);
410 }
411
412 int x86_setup_perfctr(struct perf_event *event)
413 {
414 struct perf_event_attr *attr = &event->attr;
415 struct hw_perf_event *hwc = &event->hw;
416 u64 config;
417
418 if (!is_sampling_event(event)) {
419 hwc->sample_period = x86_pmu.max_period;
420 hwc->last_period = hwc->sample_period;
421 local64_set(&hwc->period_left, hwc->sample_period);
422 }
423
424 if (attr->type == PERF_TYPE_RAW)
425 return x86_pmu_extra_regs(event->attr.config, event);
426
427 if (attr->type == PERF_TYPE_HW_CACHE)
428 return set_ext_hw_attr(hwc, event);
429
430 if (attr->config >= x86_pmu.max_events)
431 return -EINVAL;
432
433 attr->config = array_index_nospec((unsigned long)attr->config, x86_pmu.max_events);
434
435
436
437
438 config = x86_pmu.event_map(attr->config);
439
440 if (config == 0)
441 return -ENOENT;
442
443 if (config == -1LL)
444 return -EINVAL;
445
446 hwc->config |= config;
447
448 return 0;
449 }
450
451
452
453
454
455
456
457 static inline int precise_br_compat(struct perf_event *event)
458 {
459 u64 m = event->attr.branch_sample_type;
460 u64 b = 0;
461
462
463 if (!(m & PERF_SAMPLE_BRANCH_ANY))
464 return 0;
465
466 m &= PERF_SAMPLE_BRANCH_KERNEL | PERF_SAMPLE_BRANCH_USER;
467
468 if (!event->attr.exclude_user)
469 b |= PERF_SAMPLE_BRANCH_USER;
470
471 if (!event->attr.exclude_kernel)
472 b |= PERF_SAMPLE_BRANCH_KERNEL;
473
474
475
476
477
478 return m == b;
479 }
480
481 int x86_pmu_max_precise(void)
482 {
483 int precise = 0;
484
485
486 if (x86_pmu.pebs_active && !x86_pmu.pebs_broken) {
487 precise++;
488
489
490 if (x86_pmu.lbr_nr || x86_pmu.intel_cap.pebs_format >= 2)
491 precise++;
492
493 if (x86_pmu.pebs_prec_dist)
494 precise++;
495 }
496 return precise;
497 }
498
499 int x86_pmu_hw_config(struct perf_event *event)
500 {
501 if (event->attr.precise_ip) {
502 int precise = x86_pmu_max_precise();
503
504 if (event->attr.precise_ip > precise)
505 return -EOPNOTSUPP;
506
507
508 if (!is_sampling_event(event))
509 return -EINVAL;
510 }
511
512
513
514
515 if (event->attr.precise_ip > 1 && x86_pmu.intel_cap.pebs_format < 2) {
516 u64 *br_type = &event->attr.branch_sample_type;
517
518 if (has_branch_stack(event)) {
519 if (!precise_br_compat(event))
520 return -EOPNOTSUPP;
521
522
523
524 } else {
525
526
527
528
529
530
531
532 *br_type = PERF_SAMPLE_BRANCH_ANY;
533
534 if (!event->attr.exclude_user)
535 *br_type |= PERF_SAMPLE_BRANCH_USER;
536
537 if (!event->attr.exclude_kernel)
538 *br_type |= PERF_SAMPLE_BRANCH_KERNEL;
539 }
540 }
541
542 if (event->attr.branch_sample_type & PERF_SAMPLE_BRANCH_CALL_STACK)
543 event->attach_state |= PERF_ATTACH_TASK_DATA;
544
545
546
547
548
549 event->hw.config = ARCH_PERFMON_EVENTSEL_INT;
550
551
552
553
554 if (!event->attr.exclude_user)
555 event->hw.config |= ARCH_PERFMON_EVENTSEL_USR;
556 if (!event->attr.exclude_kernel)
557 event->hw.config |= ARCH_PERFMON_EVENTSEL_OS;
558
559 if (event->attr.type == PERF_TYPE_RAW)
560 event->hw.config |= event->attr.config & X86_RAW_EVENT_MASK;
561
562 if (event->attr.sample_period && x86_pmu.limit_period) {
563 if (x86_pmu.limit_period(event, event->attr.sample_period) >
564 event->attr.sample_period)
565 return -EINVAL;
566 }
567
568
569 if (unlikely(event->attr.sample_regs_user & PERF_REG_EXTENDED_MASK))
570 return -EINVAL;
571
572
573
574
575 if (unlikely(event->attr.sample_regs_intr & PERF_REG_EXTENDED_MASK)) {
576 if (!(event->pmu->capabilities & PERF_PMU_CAP_EXTENDED_REGS))
577 return -EINVAL;
578
579 if (!event->attr.precise_ip)
580 return -EINVAL;
581 }
582
583 return x86_setup_perfctr(event);
584 }
585
586
587
588
589 static int __x86_pmu_event_init(struct perf_event *event)
590 {
591 int err;
592
593 if (!x86_pmu_initialized())
594 return -ENODEV;
595
596 err = x86_reserve_hardware();
597 if (err)
598 return err;
599
600 atomic_inc(&active_events);
601 event->destroy = hw_perf_event_destroy;
602
603 event->hw.idx = -1;
604 event->hw.last_cpu = -1;
605 event->hw.last_tag = ~0ULL;
606
607
608 event->hw.extra_reg.idx = EXTRA_REG_NONE;
609 event->hw.branch_reg.idx = EXTRA_REG_NONE;
610
611 return x86_pmu.hw_config(event);
612 }
613
614 void x86_pmu_disable_all(void)
615 {
616 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
617 int idx;
618
619 for (idx = 0; idx < x86_pmu.num_counters; idx++) {
620 u64 val;
621
622 if (!test_bit(idx, cpuc->active_mask))
623 continue;
624 rdmsrl(x86_pmu_config_addr(idx), val);
625 if (!(val & ARCH_PERFMON_EVENTSEL_ENABLE))
626 continue;
627 val &= ~ARCH_PERFMON_EVENTSEL_ENABLE;
628 wrmsrl(x86_pmu_config_addr(idx), val);
629 }
630 }
631
632
633
634
635
636
637
638
639
640
641
642
643
644
645 static void x86_pmu_disable(struct pmu *pmu)
646 {
647 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
648
649 if (!x86_pmu_initialized())
650 return;
651
652 if (!cpuc->enabled)
653 return;
654
655 cpuc->n_added = 0;
656 cpuc->enabled = 0;
657 barrier();
658
659 x86_pmu.disable_all();
660 }
661
662 void x86_pmu_enable_all(int added)
663 {
664 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
665 int idx;
666
667 for (idx = 0; idx < x86_pmu.num_counters; idx++) {
668 struct hw_perf_event *hwc = &cpuc->events[idx]->hw;
669
670 if (!test_bit(idx, cpuc->active_mask))
671 continue;
672
673 __x86_pmu_enable_event(hwc, ARCH_PERFMON_EVENTSEL_ENABLE);
674 }
675 }
676
677 static struct pmu pmu;
678
679 static inline int is_x86_event(struct perf_event *event)
680 {
681 return event->pmu == &pmu;
682 }
683
684 struct pmu *x86_get_pmu(void)
685 {
686 return &pmu;
687 }
688
689
690
691
692
693
694
695 struct sched_state {
696 int weight;
697 int event;
698 int counter;
699 int unassigned;
700 int nr_gp;
701 unsigned long used[BITS_TO_LONGS(X86_PMC_IDX_MAX)];
702 };
703
704
705 #define SCHED_STATES_MAX 2
706
707 struct perf_sched {
708 int max_weight;
709 int max_events;
710 int max_gp;
711 int saved_states;
712 struct event_constraint **constraints;
713 struct sched_state state;
714 struct sched_state saved[SCHED_STATES_MAX];
715 };
716
717
718
719
720 static void perf_sched_init(struct perf_sched *sched, struct event_constraint **constraints,
721 int num, int wmin, int wmax, int gpmax)
722 {
723 int idx;
724
725 memset(sched, 0, sizeof(*sched));
726 sched->max_events = num;
727 sched->max_weight = wmax;
728 sched->max_gp = gpmax;
729 sched->constraints = constraints;
730
731 for (idx = 0; idx < num; idx++) {
732 if (constraints[idx]->weight == wmin)
733 break;
734 }
735
736 sched->state.event = idx;
737 sched->state.weight = wmin;
738 sched->state.unassigned = num;
739 }
740
741 static void perf_sched_save_state(struct perf_sched *sched)
742 {
743 if (WARN_ON_ONCE(sched->saved_states >= SCHED_STATES_MAX))
744 return;
745
746 sched->saved[sched->saved_states] = sched->state;
747 sched->saved_states++;
748 }
749
750 static bool perf_sched_restore_state(struct perf_sched *sched)
751 {
752 if (!sched->saved_states)
753 return false;
754
755 sched->saved_states--;
756 sched->state = sched->saved[sched->saved_states];
757
758
759 clear_bit(sched->state.counter++, sched->state.used);
760
761 return true;
762 }
763
764
765
766
767
768 static bool __perf_sched_find_counter(struct perf_sched *sched)
769 {
770 struct event_constraint *c;
771 int idx;
772
773 if (!sched->state.unassigned)
774 return false;
775
776 if (sched->state.event >= sched->max_events)
777 return false;
778
779 c = sched->constraints[sched->state.event];
780
781 if (c->idxmsk64 & (~0ULL << INTEL_PMC_IDX_FIXED)) {
782 idx = INTEL_PMC_IDX_FIXED;
783 for_each_set_bit_from(idx, c->idxmsk, X86_PMC_IDX_MAX) {
784 if (!__test_and_set_bit(idx, sched->state.used))
785 goto done;
786 }
787 }
788
789
790 idx = sched->state.counter;
791 for_each_set_bit_from(idx, c->idxmsk, INTEL_PMC_IDX_FIXED) {
792 if (!__test_and_set_bit(idx, sched->state.used)) {
793 if (sched->state.nr_gp++ >= sched->max_gp)
794 return false;
795
796 goto done;
797 }
798 }
799
800 return false;
801
802 done:
803 sched->state.counter = idx;
804
805 if (c->overlap)
806 perf_sched_save_state(sched);
807
808 return true;
809 }
810
811 static bool perf_sched_find_counter(struct perf_sched *sched)
812 {
813 while (!__perf_sched_find_counter(sched)) {
814 if (!perf_sched_restore_state(sched))
815 return false;
816 }
817
818 return true;
819 }
820
821
822
823
824
825 static bool perf_sched_next_event(struct perf_sched *sched)
826 {
827 struct event_constraint *c;
828
829 if (!sched->state.unassigned || !--sched->state.unassigned)
830 return false;
831
832 do {
833
834 sched->state.event++;
835 if (sched->state.event >= sched->max_events) {
836
837 sched->state.event = 0;
838 sched->state.weight++;
839 if (sched->state.weight > sched->max_weight)
840 return false;
841 }
842 c = sched->constraints[sched->state.event];
843 } while (c->weight != sched->state.weight);
844
845 sched->state.counter = 0;
846
847 return true;
848 }
849
850
851
852
853 int perf_assign_events(struct event_constraint **constraints, int n,
854 int wmin, int wmax, int gpmax, int *assign)
855 {
856 struct perf_sched sched;
857
858 perf_sched_init(&sched, constraints, n, wmin, wmax, gpmax);
859
860 do {
861 if (!perf_sched_find_counter(&sched))
862 break;
863 if (assign)
864 assign[sched.state.event] = sched.state.counter;
865 } while (perf_sched_next_event(&sched));
866
867 return sched.state.unassigned;
868 }
869 EXPORT_SYMBOL_GPL(perf_assign_events);
870
871 int x86_schedule_events(struct cpu_hw_events *cpuc, int n, int *assign)
872 {
873 struct event_constraint *c;
874 unsigned long used_mask[BITS_TO_LONGS(X86_PMC_IDX_MAX)];
875 struct perf_event *e;
876 int n0, i, wmin, wmax, unsched = 0;
877 struct hw_perf_event *hwc;
878
879 bitmap_zero(used_mask, X86_PMC_IDX_MAX);
880
881
882
883
884
885
886
887
888 n0 = cpuc->n_events;
889 if (cpuc->txn_flags & PERF_PMU_TXN_ADD)
890 n0 -= cpuc->n_txn;
891
892 if (x86_pmu.start_scheduling)
893 x86_pmu.start_scheduling(cpuc);
894
895 for (i = 0, wmin = X86_PMC_IDX_MAX, wmax = 0; i < n; i++) {
896 c = cpuc->event_constraint[i];
897
898
899
900
901
902 WARN_ON_ONCE((c && i >= n0) || (!c && i < n0));
903
904
905
906
907
908
909 if (!c || (c->flags & PERF_X86_EVENT_DYNAMIC)) {
910 c = x86_pmu.get_event_constraints(cpuc, i, cpuc->event_list[i]);
911 cpuc->event_constraint[i] = c;
912 }
913
914 wmin = min(wmin, c->weight);
915 wmax = max(wmax, c->weight);
916 }
917
918
919
920
921 for (i = 0; i < n; i++) {
922 hwc = &cpuc->event_list[i]->hw;
923 c = cpuc->event_constraint[i];
924
925
926 if (hwc->idx == -1)
927 break;
928
929
930 if (!test_bit(hwc->idx, c->idxmsk))
931 break;
932
933
934 if (test_bit(hwc->idx, used_mask))
935 break;
936
937 __set_bit(hwc->idx, used_mask);
938 if (assign)
939 assign[i] = hwc->idx;
940 }
941
942
943 if (i != n) {
944 int gpmax = x86_pmu.num_counters;
945
946
947
948
949
950
951
952
953
954
955
956 if (is_ht_workaround_enabled() && !cpuc->is_fake &&
957 READ_ONCE(cpuc->excl_cntrs->exclusive_present))
958 gpmax /= 2;
959
960 unsched = perf_assign_events(cpuc->event_constraint, n, wmin,
961 wmax, gpmax, assign);
962 }
963
964
965
966
967
968
969
970
971
972
973
974 if (!unsched && assign) {
975 for (i = 0; i < n; i++) {
976 e = cpuc->event_list[i];
977 if (x86_pmu.commit_scheduling)
978 x86_pmu.commit_scheduling(cpuc, i, assign[i]);
979 }
980 } else {
981 for (i = n0; i < n; i++) {
982 e = cpuc->event_list[i];
983
984
985
986
987 if (x86_pmu.put_event_constraints)
988 x86_pmu.put_event_constraints(cpuc, e);
989
990 cpuc->event_constraint[i] = NULL;
991 }
992 }
993
994 if (x86_pmu.stop_scheduling)
995 x86_pmu.stop_scheduling(cpuc);
996
997 return unsched ? -EINVAL : 0;
998 }
999
1000
1001
1002
1003
1004 static int collect_events(struct cpu_hw_events *cpuc, struct perf_event *leader, bool dogrp)
1005 {
1006 struct perf_event *event;
1007 int n, max_count;
1008
1009 max_count = x86_pmu.num_counters + x86_pmu.num_counters_fixed;
1010
1011
1012 n = cpuc->n_events;
1013 if (!cpuc->n_events)
1014 cpuc->pebs_output = 0;
1015
1016 if (!cpuc->is_fake && leader->attr.precise_ip) {
1017
1018
1019
1020
1021
1022 if (is_pebs_pt(leader) && !leader->aux_event)
1023 return -EINVAL;
1024
1025
1026
1027
1028 if (cpuc->pebs_output &&
1029 cpuc->pebs_output != is_pebs_pt(leader) + 1)
1030 return -EINVAL;
1031
1032 cpuc->pebs_output = is_pebs_pt(leader) + 1;
1033 }
1034
1035 if (is_x86_event(leader)) {
1036 if (n >= max_count)
1037 return -EINVAL;
1038 cpuc->event_list[n] = leader;
1039 n++;
1040 }
1041 if (!dogrp)
1042 return n;
1043
1044 for_each_sibling_event(event, leader) {
1045 if (!is_x86_event(event) ||
1046 event->state <= PERF_EVENT_STATE_OFF)
1047 continue;
1048
1049 if (n >= max_count)
1050 return -EINVAL;
1051
1052 cpuc->event_list[n] = event;
1053 n++;
1054 }
1055 return n;
1056 }
1057
1058 static inline void x86_assign_hw_event(struct perf_event *event,
1059 struct cpu_hw_events *cpuc, int i)
1060 {
1061 struct hw_perf_event *hwc = &event->hw;
1062
1063 hwc->idx = cpuc->assign[i];
1064 hwc->last_cpu = smp_processor_id();
1065 hwc->last_tag = ++cpuc->tags[i];
1066
1067 if (hwc->idx == INTEL_PMC_IDX_FIXED_BTS) {
1068 hwc->config_base = 0;
1069 hwc->event_base = 0;
1070 } else if (hwc->idx >= INTEL_PMC_IDX_FIXED) {
1071 hwc->config_base = MSR_ARCH_PERFMON_FIXED_CTR_CTRL;
1072 hwc->event_base = MSR_ARCH_PERFMON_FIXED_CTR0 + (hwc->idx - INTEL_PMC_IDX_FIXED);
1073 hwc->event_base_rdpmc = (hwc->idx - INTEL_PMC_IDX_FIXED) | 1<<30;
1074 } else {
1075 hwc->config_base = x86_pmu_config_addr(hwc->idx);
1076 hwc->event_base = x86_pmu_event_addr(hwc->idx);
1077 hwc->event_base_rdpmc = x86_pmu_rdpmc_index(hwc->idx);
1078 }
1079 }
1080
1081
1082
1083
1084
1085
1086
1087
1088
1089
1090
1091
1092
1093
1094
1095 int x86_perf_rdpmc_index(struct perf_event *event)
1096 {
1097 lockdep_assert_irqs_disabled();
1098
1099 return event->hw.event_base_rdpmc;
1100 }
1101
1102 static inline int match_prev_assignment(struct hw_perf_event *hwc,
1103 struct cpu_hw_events *cpuc,
1104 int i)
1105 {
1106 return hwc->idx == cpuc->assign[i] &&
1107 hwc->last_cpu == smp_processor_id() &&
1108 hwc->last_tag == cpuc->tags[i];
1109 }
1110
1111 static void x86_pmu_start(struct perf_event *event, int flags);
1112
1113 static void x86_pmu_enable(struct pmu *pmu)
1114 {
1115 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
1116 struct perf_event *event;
1117 struct hw_perf_event *hwc;
1118 int i, added = cpuc->n_added;
1119
1120 if (!x86_pmu_initialized())
1121 return;
1122
1123 if (cpuc->enabled)
1124 return;
1125
1126 if (cpuc->n_added) {
1127 int n_running = cpuc->n_events - cpuc->n_added;
1128
1129
1130
1131
1132
1133
1134 for (i = 0; i < n_running; i++) {
1135 event = cpuc->event_list[i];
1136 hwc = &event->hw;
1137
1138
1139
1140
1141
1142
1143
1144 if (hwc->idx == -1 ||
1145 match_prev_assignment(hwc, cpuc, i))
1146 continue;
1147
1148
1149
1150
1151
1152 if (hwc->state & PERF_HES_STOPPED)
1153 hwc->state |= PERF_HES_ARCH;
1154
1155 x86_pmu_stop(event, PERF_EF_UPDATE);
1156 }
1157
1158
1159
1160
1161 for (i = 0; i < cpuc->n_events; i++) {
1162 event = cpuc->event_list[i];
1163 hwc = &event->hw;
1164
1165 if (!match_prev_assignment(hwc, cpuc, i))
1166 x86_assign_hw_event(event, cpuc, i);
1167 else if (i < n_running)
1168 continue;
1169
1170 if (hwc->state & PERF_HES_ARCH)
1171 continue;
1172
1173 x86_pmu_start(event, PERF_EF_RELOAD);
1174 }
1175 cpuc->n_added = 0;
1176 perf_events_lapic_init();
1177 }
1178
1179 cpuc->enabled = 1;
1180 barrier();
1181
1182 x86_pmu.enable_all(added);
1183 }
1184
1185 static DEFINE_PER_CPU(u64 [X86_PMC_IDX_MAX], pmc_prev_left);
1186
1187
1188
1189
1190
1191 int x86_perf_event_set_period(struct perf_event *event)
1192 {
1193 struct hw_perf_event *hwc = &event->hw;
1194 s64 left = local64_read(&hwc->period_left);
1195 s64 period = hwc->sample_period;
1196 int ret = 0, idx = hwc->idx;
1197
1198 if (idx == INTEL_PMC_IDX_FIXED_BTS)
1199 return 0;
1200
1201
1202
1203
1204 if (unlikely(left <= -period)) {
1205 left = period;
1206 local64_set(&hwc->period_left, left);
1207 hwc->last_period = period;
1208 ret = 1;
1209 }
1210
1211 if (unlikely(left <= 0)) {
1212 left += period;
1213 local64_set(&hwc->period_left, left);
1214 hwc->last_period = period;
1215 ret = 1;
1216 }
1217
1218
1219
1220 if (unlikely(left < 2))
1221 left = 2;
1222
1223 if (left > x86_pmu.max_period)
1224 left = x86_pmu.max_period;
1225
1226 if (x86_pmu.limit_period)
1227 left = x86_pmu.limit_period(event, left);
1228
1229 per_cpu(pmc_prev_left[idx], smp_processor_id()) = left;
1230
1231
1232
1233
1234
1235 local64_set(&hwc->prev_count, (u64)-left);
1236
1237 wrmsrl(hwc->event_base, (u64)(-left) & x86_pmu.cntval_mask);
1238
1239
1240
1241
1242
1243
1244 if (x86_pmu.perfctr_second_write) {
1245 wrmsrl(hwc->event_base,
1246 (u64)(-left) & x86_pmu.cntval_mask);
1247 }
1248
1249 perf_event_update_userpage(event);
1250
1251 return ret;
1252 }
1253
1254 void x86_pmu_enable_event(struct perf_event *event)
1255 {
1256 if (__this_cpu_read(cpu_hw_events.enabled))
1257 __x86_pmu_enable_event(&event->hw,
1258 ARCH_PERFMON_EVENTSEL_ENABLE);
1259 }
1260
1261
1262
1263
1264
1265
1266
1267 static int x86_pmu_add(struct perf_event *event, int flags)
1268 {
1269 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
1270 struct hw_perf_event *hwc;
1271 int assign[X86_PMC_IDX_MAX];
1272 int n, n0, ret;
1273
1274 hwc = &event->hw;
1275
1276 n0 = cpuc->n_events;
1277 ret = n = collect_events(cpuc, event, false);
1278 if (ret < 0)
1279 goto out;
1280
1281 hwc->state = PERF_HES_UPTODATE | PERF_HES_STOPPED;
1282 if (!(flags & PERF_EF_START))
1283 hwc->state |= PERF_HES_ARCH;
1284
1285
1286
1287
1288
1289
1290
1291
1292
1293 if (cpuc->txn_flags & PERF_PMU_TXN_ADD)
1294 goto done_collect;
1295
1296 ret = x86_pmu.schedule_events(cpuc, n, assign);
1297 if (ret)
1298 goto out;
1299
1300
1301
1302
1303 memcpy(cpuc->assign, assign, n*sizeof(int));
1304
1305 done_collect:
1306
1307
1308
1309
1310 cpuc->n_events = n;
1311 cpuc->n_added += n - n0;
1312 cpuc->n_txn += n - n0;
1313
1314 if (x86_pmu.add) {
1315
1316
1317
1318
1319 x86_pmu.add(event);
1320 }
1321
1322 ret = 0;
1323 out:
1324 return ret;
1325 }
1326
1327 static void x86_pmu_start(struct perf_event *event, int flags)
1328 {
1329 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
1330 int idx = event->hw.idx;
1331
1332 if (WARN_ON_ONCE(!(event->hw.state & PERF_HES_STOPPED)))
1333 return;
1334
1335 if (WARN_ON_ONCE(idx == -1))
1336 return;
1337
1338 if (flags & PERF_EF_RELOAD) {
1339 WARN_ON_ONCE(!(event->hw.state & PERF_HES_UPTODATE));
1340 x86_perf_event_set_period(event);
1341 }
1342
1343 event->hw.state = 0;
1344
1345 cpuc->events[idx] = event;
1346 __set_bit(idx, cpuc->active_mask);
1347 __set_bit(idx, cpuc->running);
1348 x86_pmu.enable(event);
1349 perf_event_update_userpage(event);
1350 }
1351
1352 void perf_event_print_debug(void)
1353 {
1354 u64 ctrl, status, overflow, pmc_ctrl, pmc_count, prev_left, fixed;
1355 u64 pebs, debugctl;
1356 struct cpu_hw_events *cpuc;
1357 unsigned long flags;
1358 int cpu, idx;
1359
1360 if (!x86_pmu.num_counters)
1361 return;
1362
1363 local_irq_save(flags);
1364
1365 cpu = smp_processor_id();
1366 cpuc = &per_cpu(cpu_hw_events, cpu);
1367
1368 if (x86_pmu.version >= 2) {
1369 rdmsrl(MSR_CORE_PERF_GLOBAL_CTRL, ctrl);
1370 rdmsrl(MSR_CORE_PERF_GLOBAL_STATUS, status);
1371 rdmsrl(MSR_CORE_PERF_GLOBAL_OVF_CTRL, overflow);
1372 rdmsrl(MSR_ARCH_PERFMON_FIXED_CTR_CTRL, fixed);
1373
1374 pr_info("\n");
1375 pr_info("CPU#%d: ctrl: %016llx\n", cpu, ctrl);
1376 pr_info("CPU#%d: status: %016llx\n", cpu, status);
1377 pr_info("CPU#%d: overflow: %016llx\n", cpu, overflow);
1378 pr_info("CPU#%d: fixed: %016llx\n", cpu, fixed);
1379 if (x86_pmu.pebs_constraints) {
1380 rdmsrl(MSR_IA32_PEBS_ENABLE, pebs);
1381 pr_info("CPU#%d: pebs: %016llx\n", cpu, pebs);
1382 }
1383 if (x86_pmu.lbr_nr) {
1384 rdmsrl(MSR_IA32_DEBUGCTLMSR, debugctl);
1385 pr_info("CPU#%d: debugctl: %016llx\n", cpu, debugctl);
1386 }
1387 }
1388 pr_info("CPU#%d: active: %016llx\n", cpu, *(u64 *)cpuc->active_mask);
1389
1390 for (idx = 0; idx < x86_pmu.num_counters; idx++) {
1391 rdmsrl(x86_pmu_config_addr(idx), pmc_ctrl);
1392 rdmsrl(x86_pmu_event_addr(idx), pmc_count);
1393
1394 prev_left = per_cpu(pmc_prev_left[idx], cpu);
1395
1396 pr_info("CPU#%d: gen-PMC%d ctrl: %016llx\n",
1397 cpu, idx, pmc_ctrl);
1398 pr_info("CPU#%d: gen-PMC%d count: %016llx\n",
1399 cpu, idx, pmc_count);
1400 pr_info("CPU#%d: gen-PMC%d left: %016llx\n",
1401 cpu, idx, prev_left);
1402 }
1403 for (idx = 0; idx < x86_pmu.num_counters_fixed; idx++) {
1404 rdmsrl(MSR_ARCH_PERFMON_FIXED_CTR0 + idx, pmc_count);
1405
1406 pr_info("CPU#%d: fixed-PMC%d count: %016llx\n",
1407 cpu, idx, pmc_count);
1408 }
1409 local_irq_restore(flags);
1410 }
1411
1412 void x86_pmu_stop(struct perf_event *event, int flags)
1413 {
1414 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
1415 struct hw_perf_event *hwc = &event->hw;
1416
1417 if (test_bit(hwc->idx, cpuc->active_mask)) {
1418 x86_pmu.disable(event);
1419 __clear_bit(hwc->idx, cpuc->active_mask);
1420 cpuc->events[hwc->idx] = NULL;
1421 WARN_ON_ONCE(hwc->state & PERF_HES_STOPPED);
1422 hwc->state |= PERF_HES_STOPPED;
1423 }
1424
1425 if ((flags & PERF_EF_UPDATE) && !(hwc->state & PERF_HES_UPTODATE)) {
1426
1427
1428
1429
1430 x86_perf_event_update(event);
1431 hwc->state |= PERF_HES_UPTODATE;
1432 }
1433 }
1434
1435 static void x86_pmu_del(struct perf_event *event, int flags)
1436 {
1437 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
1438 int i;
1439
1440
1441
1442
1443
1444
1445
1446
1447
1448 if (cpuc->txn_flags & PERF_PMU_TXN_ADD)
1449 goto do_del;
1450
1451
1452
1453
1454 x86_pmu_stop(event, PERF_EF_UPDATE);
1455
1456 for (i = 0; i < cpuc->n_events; i++) {
1457 if (event == cpuc->event_list[i])
1458 break;
1459 }
1460
1461 if (WARN_ON_ONCE(i == cpuc->n_events))
1462 return;
1463
1464
1465 if (i >= cpuc->n_events - cpuc->n_added)
1466 --cpuc->n_added;
1467
1468 if (x86_pmu.put_event_constraints)
1469 x86_pmu.put_event_constraints(cpuc, event);
1470
1471
1472 while (++i < cpuc->n_events) {
1473 cpuc->event_list[i-1] = cpuc->event_list[i];
1474 cpuc->event_constraint[i-1] = cpuc->event_constraint[i];
1475 }
1476 cpuc->event_constraint[i-1] = NULL;
1477 --cpuc->n_events;
1478
1479 perf_event_update_userpage(event);
1480
1481 do_del:
1482 if (x86_pmu.del) {
1483
1484
1485
1486
1487 x86_pmu.del(event);
1488 }
1489 }
1490
1491 int x86_pmu_handle_irq(struct pt_regs *regs)
1492 {
1493 struct perf_sample_data data;
1494 struct cpu_hw_events *cpuc;
1495 struct perf_event *event;
1496 int idx, handled = 0;
1497 u64 val;
1498
1499 cpuc = this_cpu_ptr(&cpu_hw_events);
1500
1501
1502
1503
1504
1505
1506
1507
1508
1509 apic_write(APIC_LVTPC, APIC_DM_NMI);
1510
1511 for (idx = 0; idx < x86_pmu.num_counters; idx++) {
1512 if (!test_bit(idx, cpuc->active_mask))
1513 continue;
1514
1515 event = cpuc->events[idx];
1516
1517 val = x86_perf_event_update(event);
1518 if (val & (1ULL << (x86_pmu.cntval_bits - 1)))
1519 continue;
1520
1521
1522
1523
1524 handled++;
1525 perf_sample_data_init(&data, 0, event->hw.last_period);
1526
1527 if (!x86_perf_event_set_period(event))
1528 continue;
1529
1530 if (perf_event_overflow(event, &data, regs))
1531 x86_pmu_stop(event, 0);
1532 }
1533
1534 if (handled)
1535 inc_irq_stat(apic_perf_irqs);
1536
1537 return handled;
1538 }
1539
1540 void perf_events_lapic_init(void)
1541 {
1542 if (!x86_pmu.apic || !x86_pmu_initialized())
1543 return;
1544
1545
1546
1547
1548 apic_write(APIC_LVTPC, APIC_DM_NMI);
1549 }
1550
1551 static int
1552 perf_event_nmi_handler(unsigned int cmd, struct pt_regs *regs)
1553 {
1554 u64 start_clock;
1555 u64 finish_clock;
1556 int ret;
1557
1558
1559
1560
1561
1562 if (!atomic_read(&active_events))
1563 return NMI_DONE;
1564
1565 start_clock = sched_clock();
1566 ret = x86_pmu.handle_irq(regs);
1567 finish_clock = sched_clock();
1568
1569 perf_sample_event_took(finish_clock - start_clock);
1570
1571 return ret;
1572 }
1573 NOKPROBE_SYMBOL(perf_event_nmi_handler);
1574
1575 struct event_constraint emptyconstraint;
1576 struct event_constraint unconstrained;
1577
1578 static int x86_pmu_prepare_cpu(unsigned int cpu)
1579 {
1580 struct cpu_hw_events *cpuc = &per_cpu(cpu_hw_events, cpu);
1581 int i;
1582
1583 for (i = 0 ; i < X86_PERF_KFREE_MAX; i++)
1584 cpuc->kfree_on_online[i] = NULL;
1585 if (x86_pmu.cpu_prepare)
1586 return x86_pmu.cpu_prepare(cpu);
1587 return 0;
1588 }
1589
1590 static int x86_pmu_dead_cpu(unsigned int cpu)
1591 {
1592 if (x86_pmu.cpu_dead)
1593 x86_pmu.cpu_dead(cpu);
1594 return 0;
1595 }
1596
1597 static int x86_pmu_online_cpu(unsigned int cpu)
1598 {
1599 struct cpu_hw_events *cpuc = &per_cpu(cpu_hw_events, cpu);
1600 int i;
1601
1602 for (i = 0 ; i < X86_PERF_KFREE_MAX; i++) {
1603 kfree(cpuc->kfree_on_online[i]);
1604 cpuc->kfree_on_online[i] = NULL;
1605 }
1606 return 0;
1607 }
1608
1609 static int x86_pmu_starting_cpu(unsigned int cpu)
1610 {
1611 if (x86_pmu.cpu_starting)
1612 x86_pmu.cpu_starting(cpu);
1613 return 0;
1614 }
1615
1616 static int x86_pmu_dying_cpu(unsigned int cpu)
1617 {
1618 if (x86_pmu.cpu_dying)
1619 x86_pmu.cpu_dying(cpu);
1620 return 0;
1621 }
1622
1623 static void __init pmu_check_apic(void)
1624 {
1625 if (boot_cpu_has(X86_FEATURE_APIC))
1626 return;
1627
1628 x86_pmu.apic = 0;
1629 pr_info("no APIC, boot with the \"lapic\" boot parameter to force-enable it.\n");
1630 pr_info("no hardware sampling interrupt available.\n");
1631
1632
1633
1634
1635
1636
1637
1638 pmu.capabilities |= PERF_PMU_CAP_NO_INTERRUPT;
1639
1640 }
1641
1642 static struct attribute_group x86_pmu_format_group __ro_after_init = {
1643 .name = "format",
1644 .attrs = NULL,
1645 };
1646
1647 ssize_t events_sysfs_show(struct device *dev, struct device_attribute *attr, char *page)
1648 {
1649 struct perf_pmu_events_attr *pmu_attr =
1650 container_of(attr, struct perf_pmu_events_attr, attr);
1651 u64 config = 0;
1652
1653 if (pmu_attr->id < x86_pmu.max_events)
1654 config = x86_pmu.event_map(pmu_attr->id);
1655
1656
1657 if (pmu_attr->event_str)
1658 return sprintf(page, "%s", pmu_attr->event_str);
1659
1660 return x86_pmu.events_sysfs_show(page, config);
1661 }
1662 EXPORT_SYMBOL_GPL(events_sysfs_show);
1663
1664 ssize_t events_ht_sysfs_show(struct device *dev, struct device_attribute *attr,
1665 char *page)
1666 {
1667 struct perf_pmu_events_ht_attr *pmu_attr =
1668 container_of(attr, struct perf_pmu_events_ht_attr, attr);
1669
1670
1671
1672
1673
1674
1675
1676
1677
1678
1679
1680
1681 return sprintf(page, "%s",
1682 topology_max_smt_threads() > 1 ?
1683 pmu_attr->event_str_ht :
1684 pmu_attr->event_str_noht);
1685 }
1686
1687 EVENT_ATTR(cpu-cycles, CPU_CYCLES );
1688 EVENT_ATTR(instructions, INSTRUCTIONS );
1689 EVENT_ATTR(cache-references, CACHE_REFERENCES );
1690 EVENT_ATTR(cache-misses, CACHE_MISSES );
1691 EVENT_ATTR(branch-instructions, BRANCH_INSTRUCTIONS );
1692 EVENT_ATTR(branch-misses, BRANCH_MISSES );
1693 EVENT_ATTR(bus-cycles, BUS_CYCLES );
1694 EVENT_ATTR(stalled-cycles-frontend, STALLED_CYCLES_FRONTEND );
1695 EVENT_ATTR(stalled-cycles-backend, STALLED_CYCLES_BACKEND );
1696 EVENT_ATTR(ref-cycles, REF_CPU_CYCLES );
1697
1698 static struct attribute *empty_attrs;
1699
1700 static struct attribute *events_attr[] = {
1701 EVENT_PTR(CPU_CYCLES),
1702 EVENT_PTR(INSTRUCTIONS),
1703 EVENT_PTR(CACHE_REFERENCES),
1704 EVENT_PTR(CACHE_MISSES),
1705 EVENT_PTR(BRANCH_INSTRUCTIONS),
1706 EVENT_PTR(BRANCH_MISSES),
1707 EVENT_PTR(BUS_CYCLES),
1708 EVENT_PTR(STALLED_CYCLES_FRONTEND),
1709 EVENT_PTR(STALLED_CYCLES_BACKEND),
1710 EVENT_PTR(REF_CPU_CYCLES),
1711 NULL,
1712 };
1713
1714
1715
1716
1717
1718 static umode_t
1719 is_visible(struct kobject *kobj, struct attribute *attr, int idx)
1720 {
1721 struct perf_pmu_events_attr *pmu_attr;
1722
1723 if (idx >= x86_pmu.max_events)
1724 return 0;
1725
1726 pmu_attr = container_of(attr, struct perf_pmu_events_attr, attr.attr);
1727
1728 return pmu_attr->event_str || x86_pmu.event_map(idx) ? attr->mode : 0;
1729 }
1730
1731 static struct attribute_group x86_pmu_events_group __ro_after_init = {
1732 .name = "events",
1733 .attrs = events_attr,
1734 .is_visible = is_visible,
1735 };
1736
1737 ssize_t x86_event_sysfs_show(char *page, u64 config, u64 event)
1738 {
1739 u64 umask = (config & ARCH_PERFMON_EVENTSEL_UMASK) >> 8;
1740 u64 cmask = (config & ARCH_PERFMON_EVENTSEL_CMASK) >> 24;
1741 bool edge = (config & ARCH_PERFMON_EVENTSEL_EDGE);
1742 bool pc = (config & ARCH_PERFMON_EVENTSEL_PIN_CONTROL);
1743 bool any = (config & ARCH_PERFMON_EVENTSEL_ANY);
1744 bool inv = (config & ARCH_PERFMON_EVENTSEL_INV);
1745 ssize_t ret;
1746
1747
1748
1749
1750
1751 ret = sprintf(page, "event=0x%02llx", event);
1752
1753 if (umask)
1754 ret += sprintf(page + ret, ",umask=0x%02llx", umask);
1755
1756 if (edge)
1757 ret += sprintf(page + ret, ",edge");
1758
1759 if (pc)
1760 ret += sprintf(page + ret, ",pc");
1761
1762 if (any)
1763 ret += sprintf(page + ret, ",any");
1764
1765 if (inv)
1766 ret += sprintf(page + ret, ",inv");
1767
1768 if (cmask)
1769 ret += sprintf(page + ret, ",cmask=0x%02llx", cmask);
1770
1771 ret += sprintf(page + ret, "\n");
1772
1773 return ret;
1774 }
1775
1776 static struct attribute_group x86_pmu_attr_group;
1777 static struct attribute_group x86_pmu_caps_group;
1778
1779 static int __init init_hw_perf_events(void)
1780 {
1781 struct x86_pmu_quirk *quirk;
1782 int err;
1783
1784 pr_info("Performance Events: ");
1785
1786 switch (boot_cpu_data.x86_vendor) {
1787 case X86_VENDOR_INTEL:
1788 err = intel_pmu_init();
1789 break;
1790 case X86_VENDOR_AMD:
1791 err = amd_pmu_init();
1792 break;
1793 case X86_VENDOR_HYGON:
1794 err = amd_pmu_init();
1795 x86_pmu.name = "HYGON";
1796 break;
1797 default:
1798 err = -ENOTSUPP;
1799 }
1800 if (err != 0) {
1801 pr_cont("no PMU driver, software events only.\n");
1802 return 0;
1803 }
1804
1805 pmu_check_apic();
1806
1807
1808 if (!check_hw_exists())
1809 return 0;
1810
1811 pr_cont("%s PMU driver.\n", x86_pmu.name);
1812
1813 x86_pmu.attr_rdpmc = 1;
1814
1815 for (quirk = x86_pmu.quirks; quirk; quirk = quirk->next)
1816 quirk->func();
1817
1818 if (!x86_pmu.intel_ctrl)
1819 x86_pmu.intel_ctrl = (1 << x86_pmu.num_counters) - 1;
1820
1821 perf_events_lapic_init();
1822 register_nmi_handler(NMI_LOCAL, perf_event_nmi_handler, 0, "PMI");
1823
1824 unconstrained = (struct event_constraint)
1825 __EVENT_CONSTRAINT(0, (1ULL << x86_pmu.num_counters) - 1,
1826 0, x86_pmu.num_counters, 0, 0);
1827
1828 x86_pmu_format_group.attrs = x86_pmu.format_attrs;
1829
1830 if (!x86_pmu.events_sysfs_show)
1831 x86_pmu_events_group.attrs = &empty_attrs;
1832
1833 pmu.attr_update = x86_pmu.attr_update;
1834
1835 pr_info("... version: %d\n", x86_pmu.version);
1836 pr_info("... bit width: %d\n", x86_pmu.cntval_bits);
1837 pr_info("... generic registers: %d\n", x86_pmu.num_counters);
1838 pr_info("... value mask: %016Lx\n", x86_pmu.cntval_mask);
1839 pr_info("... max period: %016Lx\n", x86_pmu.max_period);
1840 pr_info("... fixed-purpose events: %d\n", x86_pmu.num_counters_fixed);
1841 pr_info("... event mask: %016Lx\n", x86_pmu.intel_ctrl);
1842
1843
1844
1845
1846
1847 err = cpuhp_setup_state(CPUHP_PERF_X86_PREPARE, "perf/x86:prepare",
1848 x86_pmu_prepare_cpu, x86_pmu_dead_cpu);
1849 if (err)
1850 return err;
1851
1852 err = cpuhp_setup_state(CPUHP_AP_PERF_X86_STARTING,
1853 "perf/x86:starting", x86_pmu_starting_cpu,
1854 x86_pmu_dying_cpu);
1855 if (err)
1856 goto out;
1857
1858 err = cpuhp_setup_state(CPUHP_AP_PERF_X86_ONLINE, "perf/x86:online",
1859 x86_pmu_online_cpu, NULL);
1860 if (err)
1861 goto out1;
1862
1863 err = perf_pmu_register(&pmu, "cpu", PERF_TYPE_RAW);
1864 if (err)
1865 goto out2;
1866
1867 return 0;
1868
1869 out2:
1870 cpuhp_remove_state(CPUHP_AP_PERF_X86_ONLINE);
1871 out1:
1872 cpuhp_remove_state(CPUHP_AP_PERF_X86_STARTING);
1873 out:
1874 cpuhp_remove_state(CPUHP_PERF_X86_PREPARE);
1875 return err;
1876 }
1877 early_initcall(init_hw_perf_events);
1878
1879 static inline void x86_pmu_read(struct perf_event *event)
1880 {
1881 if (x86_pmu.read)
1882 return x86_pmu.read(event);
1883 x86_perf_event_update(event);
1884 }
1885
1886
1887
1888
1889
1890
1891
1892
1893
1894
1895 static void x86_pmu_start_txn(struct pmu *pmu, unsigned int txn_flags)
1896 {
1897 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
1898
1899 WARN_ON_ONCE(cpuc->txn_flags);
1900
1901 cpuc->txn_flags = txn_flags;
1902 if (txn_flags & ~PERF_PMU_TXN_ADD)
1903 return;
1904
1905 perf_pmu_disable(pmu);
1906 __this_cpu_write(cpu_hw_events.n_txn, 0);
1907 }
1908
1909
1910
1911
1912
1913
1914 static void x86_pmu_cancel_txn(struct pmu *pmu)
1915 {
1916 unsigned int txn_flags;
1917 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
1918
1919 WARN_ON_ONCE(!cpuc->txn_flags);
1920
1921 txn_flags = cpuc->txn_flags;
1922 cpuc->txn_flags = 0;
1923 if (txn_flags & ~PERF_PMU_TXN_ADD)
1924 return;
1925
1926
1927
1928
1929
1930 __this_cpu_sub(cpu_hw_events.n_added, __this_cpu_read(cpu_hw_events.n_txn));
1931 __this_cpu_sub(cpu_hw_events.n_events, __this_cpu_read(cpu_hw_events.n_txn));
1932 perf_pmu_enable(pmu);
1933 }
1934
1935
1936
1937
1938
1939
1940
1941
1942 static int x86_pmu_commit_txn(struct pmu *pmu)
1943 {
1944 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
1945 int assign[X86_PMC_IDX_MAX];
1946 int n, ret;
1947
1948 WARN_ON_ONCE(!cpuc->txn_flags);
1949
1950 if (cpuc->txn_flags & ~PERF_PMU_TXN_ADD) {
1951 cpuc->txn_flags = 0;
1952 return 0;
1953 }
1954
1955 n = cpuc->n_events;
1956
1957 if (!x86_pmu_initialized())
1958 return -EAGAIN;
1959
1960 ret = x86_pmu.schedule_events(cpuc, n, assign);
1961 if (ret)
1962 return ret;
1963
1964
1965
1966
1967
1968 memcpy(cpuc->assign, assign, n*sizeof(int));
1969
1970 cpuc->txn_flags = 0;
1971 perf_pmu_enable(pmu);
1972 return 0;
1973 }
1974
1975
1976
1977
1978
1979
1980
1981
1982 static void free_fake_cpuc(struct cpu_hw_events *cpuc)
1983 {
1984 intel_cpuc_finish(cpuc);
1985 kfree(cpuc);
1986 }
1987
1988 static struct cpu_hw_events *allocate_fake_cpuc(void)
1989 {
1990 struct cpu_hw_events *cpuc;
1991 int cpu = raw_smp_processor_id();
1992
1993 cpuc = kzalloc(sizeof(*cpuc), GFP_KERNEL);
1994 if (!cpuc)
1995 return ERR_PTR(-ENOMEM);
1996 cpuc->is_fake = 1;
1997
1998 if (intel_cpuc_prepare(cpuc, cpu))
1999 goto error;
2000
2001 return cpuc;
2002 error:
2003 free_fake_cpuc(cpuc);
2004 return ERR_PTR(-ENOMEM);
2005 }
2006
2007
2008
2009
2010 static int validate_event(struct perf_event *event)
2011 {
2012 struct cpu_hw_events *fake_cpuc;
2013 struct event_constraint *c;
2014 int ret = 0;
2015
2016 fake_cpuc = allocate_fake_cpuc();
2017 if (IS_ERR(fake_cpuc))
2018 return PTR_ERR(fake_cpuc);
2019
2020 c = x86_pmu.get_event_constraints(fake_cpuc, 0, event);
2021
2022 if (!c || !c->weight)
2023 ret = -EINVAL;
2024
2025 if (x86_pmu.put_event_constraints)
2026 x86_pmu.put_event_constraints(fake_cpuc, event);
2027
2028 free_fake_cpuc(fake_cpuc);
2029
2030 return ret;
2031 }
2032
2033
2034
2035
2036
2037
2038
2039
2040
2041
2042
2043
2044 static int validate_group(struct perf_event *event)
2045 {
2046 struct perf_event *leader = event->group_leader;
2047 struct cpu_hw_events *fake_cpuc;
2048 int ret = -EINVAL, n;
2049
2050 fake_cpuc = allocate_fake_cpuc();
2051 if (IS_ERR(fake_cpuc))
2052 return PTR_ERR(fake_cpuc);
2053
2054
2055
2056
2057
2058
2059 n = collect_events(fake_cpuc, leader, true);
2060 if (n < 0)
2061 goto out;
2062
2063 fake_cpuc->n_events = n;
2064 n = collect_events(fake_cpuc, event, false);
2065 if (n < 0)
2066 goto out;
2067
2068 fake_cpuc->n_events = 0;
2069 ret = x86_pmu.schedule_events(fake_cpuc, n, NULL);
2070
2071 out:
2072 free_fake_cpuc(fake_cpuc);
2073 return ret;
2074 }
2075
2076 static int x86_pmu_event_init(struct perf_event *event)
2077 {
2078 struct pmu *tmp;
2079 int err;
2080
2081 switch (event->attr.type) {
2082 case PERF_TYPE_RAW:
2083 case PERF_TYPE_HARDWARE:
2084 case PERF_TYPE_HW_CACHE:
2085 break;
2086
2087 default:
2088 return -ENOENT;
2089 }
2090
2091 err = __x86_pmu_event_init(event);
2092 if (!err) {
2093
2094
2095
2096
2097
2098 tmp = event->pmu;
2099 event->pmu = &pmu;
2100
2101 if (event->group_leader != event)
2102 err = validate_group(event);
2103 else
2104 err = validate_event(event);
2105
2106 event->pmu = tmp;
2107 }
2108 if (err) {
2109 if (event->destroy)
2110 event->destroy(event);
2111 }
2112
2113 if (READ_ONCE(x86_pmu.attr_rdpmc) &&
2114 !(event->hw.flags & PERF_X86_EVENT_LARGE_PEBS))
2115 event->hw.flags |= PERF_X86_EVENT_RDPMC_ALLOWED;
2116
2117 return err;
2118 }
2119
2120 static void refresh_pce(void *ignored)
2121 {
2122 load_mm_cr4_irqsoff(this_cpu_read(cpu_tlbstate.loaded_mm));
2123 }
2124
2125 static void x86_pmu_event_mapped(struct perf_event *event, struct mm_struct *mm)
2126 {
2127 if (!(event->hw.flags & PERF_X86_EVENT_RDPMC_ALLOWED))
2128 return;
2129
2130
2131
2132
2133
2134
2135
2136
2137
2138
2139
2140 lockdep_assert_held_write(&mm->mmap_sem);
2141
2142 if (atomic_inc_return(&mm->context.perf_rdpmc_allowed) == 1)
2143 on_each_cpu_mask(mm_cpumask(mm), refresh_pce, NULL, 1);
2144 }
2145
2146 static void x86_pmu_event_unmapped(struct perf_event *event, struct mm_struct *mm)
2147 {
2148
2149 if (!(event->hw.flags & PERF_X86_EVENT_RDPMC_ALLOWED))
2150 return;
2151
2152 if (atomic_dec_and_test(&mm->context.perf_rdpmc_allowed))
2153 on_each_cpu_mask(mm_cpumask(mm), refresh_pce, NULL, 1);
2154 }
2155
2156 static int x86_pmu_event_idx(struct perf_event *event)
2157 {
2158 int idx = event->hw.idx;
2159
2160 if (!(event->hw.flags & PERF_X86_EVENT_RDPMC_ALLOWED))
2161 return 0;
2162
2163 if (x86_pmu.num_counters_fixed && idx >= INTEL_PMC_IDX_FIXED) {
2164 idx -= INTEL_PMC_IDX_FIXED;
2165 idx |= 1 << 30;
2166 }
2167
2168 return idx + 1;
2169 }
2170
2171 static ssize_t get_attr_rdpmc(struct device *cdev,
2172 struct device_attribute *attr,
2173 char *buf)
2174 {
2175 return snprintf(buf, 40, "%d\n", x86_pmu.attr_rdpmc);
2176 }
2177
2178 static ssize_t set_attr_rdpmc(struct device *cdev,
2179 struct device_attribute *attr,
2180 const char *buf, size_t count)
2181 {
2182 unsigned long val;
2183 ssize_t ret;
2184
2185 ret = kstrtoul(buf, 0, &val);
2186 if (ret)
2187 return ret;
2188
2189 if (val > 2)
2190 return -EINVAL;
2191
2192 if (x86_pmu.attr_rdpmc_broken)
2193 return -ENOTSUPP;
2194
2195 if ((val == 2) != (x86_pmu.attr_rdpmc == 2)) {
2196
2197
2198
2199
2200
2201 if (val == 2)
2202 static_branch_inc(&rdpmc_always_available_key);
2203 else
2204 static_branch_dec(&rdpmc_always_available_key);
2205 on_each_cpu(refresh_pce, NULL, 1);
2206 }
2207
2208 x86_pmu.attr_rdpmc = val;
2209
2210 return count;
2211 }
2212
2213 static DEVICE_ATTR(rdpmc, S_IRUSR | S_IWUSR, get_attr_rdpmc, set_attr_rdpmc);
2214
2215 static struct attribute *x86_pmu_attrs[] = {
2216 &dev_attr_rdpmc.attr,
2217 NULL,
2218 };
2219
2220 static struct attribute_group x86_pmu_attr_group __ro_after_init = {
2221 .attrs = x86_pmu_attrs,
2222 };
2223
2224 static ssize_t max_precise_show(struct device *cdev,
2225 struct device_attribute *attr,
2226 char *buf)
2227 {
2228 return snprintf(buf, PAGE_SIZE, "%d\n", x86_pmu_max_precise());
2229 }
2230
2231 static DEVICE_ATTR_RO(max_precise);
2232
2233 static struct attribute *x86_pmu_caps_attrs[] = {
2234 &dev_attr_max_precise.attr,
2235 NULL
2236 };
2237
2238 static struct attribute_group x86_pmu_caps_group __ro_after_init = {
2239 .name = "caps",
2240 .attrs = x86_pmu_caps_attrs,
2241 };
2242
2243 static const struct attribute_group *x86_pmu_attr_groups[] = {
2244 &x86_pmu_attr_group,
2245 &x86_pmu_format_group,
2246 &x86_pmu_events_group,
2247 &x86_pmu_caps_group,
2248 NULL,
2249 };
2250
2251 static void x86_pmu_sched_task(struct perf_event_context *ctx, bool sched_in)
2252 {
2253 if (x86_pmu.sched_task)
2254 x86_pmu.sched_task(ctx, sched_in);
2255 }
2256
2257 void perf_check_microcode(void)
2258 {
2259 if (x86_pmu.check_microcode)
2260 x86_pmu.check_microcode();
2261 }
2262
2263 static int x86_pmu_check_period(struct perf_event *event, u64 value)
2264 {
2265 if (x86_pmu.check_period && x86_pmu.check_period(event, value))
2266 return -EINVAL;
2267
2268 if (value && x86_pmu.limit_period) {
2269 if (x86_pmu.limit_period(event, value) > value)
2270 return -EINVAL;
2271 }
2272
2273 return 0;
2274 }
2275
2276 static int x86_pmu_aux_output_match(struct perf_event *event)
2277 {
2278 if (!(pmu.capabilities & PERF_PMU_CAP_AUX_OUTPUT))
2279 return 0;
2280
2281 if (x86_pmu.aux_output_match)
2282 return x86_pmu.aux_output_match(event);
2283
2284 return 0;
2285 }
2286
2287 static struct pmu pmu = {
2288 .pmu_enable = x86_pmu_enable,
2289 .pmu_disable = x86_pmu_disable,
2290
2291 .attr_groups = x86_pmu_attr_groups,
2292
2293 .event_init = x86_pmu_event_init,
2294
2295 .event_mapped = x86_pmu_event_mapped,
2296 .event_unmapped = x86_pmu_event_unmapped,
2297
2298 .add = x86_pmu_add,
2299 .del = x86_pmu_del,
2300 .start = x86_pmu_start,
2301 .stop = x86_pmu_stop,
2302 .read = x86_pmu_read,
2303
2304 .start_txn = x86_pmu_start_txn,
2305 .cancel_txn = x86_pmu_cancel_txn,
2306 .commit_txn = x86_pmu_commit_txn,
2307
2308 .event_idx = x86_pmu_event_idx,
2309 .sched_task = x86_pmu_sched_task,
2310 .task_ctx_size = sizeof(struct x86_perf_task_context),
2311 .check_period = x86_pmu_check_period,
2312
2313 .aux_output_match = x86_pmu_aux_output_match,
2314 };
2315
2316 void arch_perf_update_userpage(struct perf_event *event,
2317 struct perf_event_mmap_page *userpg, u64 now)
2318 {
2319 struct cyc2ns_data data;
2320 u64 offset;
2321
2322 userpg->cap_user_time = 0;
2323 userpg->cap_user_time_zero = 0;
2324 userpg->cap_user_rdpmc =
2325 !!(event->hw.flags & PERF_X86_EVENT_RDPMC_ALLOWED);
2326 userpg->pmc_width = x86_pmu.cntval_bits;
2327
2328 if (!using_native_sched_clock() || !sched_clock_stable())
2329 return;
2330
2331 cyc2ns_read_begin(&data);
2332
2333 offset = data.cyc2ns_offset + __sched_clock_offset;
2334
2335
2336
2337
2338
2339 userpg->cap_user_time = 1;
2340 userpg->time_mult = data.cyc2ns_mul;
2341 userpg->time_shift = data.cyc2ns_shift;
2342 userpg->time_offset = offset - now;
2343
2344
2345
2346
2347
2348 if (!event->attr.use_clockid) {
2349 userpg->cap_user_time_zero = 1;
2350 userpg->time_zero = offset;
2351 }
2352
2353 cyc2ns_read_end();
2354 }
2355
2356
2357
2358
2359
2360 static bool perf_hw_regs(struct pt_regs *regs)
2361 {
2362 return regs->flags & X86_EFLAGS_FIXED;
2363 }
2364
2365 void
2366 perf_callchain_kernel(struct perf_callchain_entry_ctx *entry, struct pt_regs *regs)
2367 {
2368 struct unwind_state state;
2369 unsigned long addr;
2370
2371 if (perf_guest_cbs && perf_guest_cbs->is_in_guest()) {
2372
2373 return;
2374 }
2375
2376 if (perf_callchain_store(entry, regs->ip))
2377 return;
2378
2379 if (perf_hw_regs(regs))
2380 unwind_start(&state, current, regs, NULL);
2381 else
2382 unwind_start(&state, current, NULL, (void *)regs->sp);
2383
2384 for (; !unwind_done(&state); unwind_next_frame(&state)) {
2385 addr = unwind_get_return_address(&state);
2386 if (!addr || perf_callchain_store(entry, addr))
2387 return;
2388 }
2389 }
2390
2391 static inline int
2392 valid_user_frame(const void __user *fp, unsigned long size)
2393 {
2394 return (__range_not_ok(fp, size, TASK_SIZE) == 0);
2395 }
2396
2397 static unsigned long get_segment_base(unsigned int segment)
2398 {
2399 struct desc_struct *desc;
2400 unsigned int idx = segment >> 3;
2401
2402 if ((segment & SEGMENT_TI_MASK) == SEGMENT_LDT) {
2403 #ifdef CONFIG_MODIFY_LDT_SYSCALL
2404 struct ldt_struct *ldt;
2405
2406
2407 ldt = READ_ONCE(current->active_mm->context.ldt);
2408 if (!ldt || idx >= ldt->nr_entries)
2409 return 0;
2410
2411 desc = &ldt->entries[idx];
2412 #else
2413 return 0;
2414 #endif
2415 } else {
2416 if (idx >= GDT_ENTRIES)
2417 return 0;
2418
2419 desc = raw_cpu_ptr(gdt_page.gdt) + idx;
2420 }
2421
2422 return get_desc_base(desc);
2423 }
2424
2425 #ifdef CONFIG_IA32_EMULATION
2426
2427 #include <linux/compat.h>
2428
2429 static inline int
2430 perf_callchain_user32(struct pt_regs *regs, struct perf_callchain_entry_ctx *entry)
2431 {
2432
2433 unsigned long ss_base, cs_base;
2434 struct stack_frame_ia32 frame;
2435 const void __user *fp;
2436
2437 if (!test_thread_flag(TIF_IA32))
2438 return 0;
2439
2440 cs_base = get_segment_base(regs->cs);
2441 ss_base = get_segment_base(regs->ss);
2442
2443 fp = compat_ptr(ss_base + regs->bp);
2444 pagefault_disable();
2445 while (entry->nr < entry->max_stack) {
2446 unsigned long bytes;
2447 frame.next_frame = 0;
2448 frame.return_address = 0;
2449
2450 if (!valid_user_frame(fp, sizeof(frame)))
2451 break;
2452
2453 bytes = __copy_from_user_nmi(&frame.next_frame, fp, 4);
2454 if (bytes != 0)
2455 break;
2456 bytes = __copy_from_user_nmi(&frame.return_address, fp+4, 4);
2457 if (bytes != 0)
2458 break;
2459
2460 perf_callchain_store(entry, cs_base + frame.return_address);
2461 fp = compat_ptr(ss_base + frame.next_frame);
2462 }
2463 pagefault_enable();
2464 return 1;
2465 }
2466 #else
2467 static inline int
2468 perf_callchain_user32(struct pt_regs *regs, struct perf_callchain_entry_ctx *entry)
2469 {
2470 return 0;
2471 }
2472 #endif
2473
2474 void
2475 perf_callchain_user(struct perf_callchain_entry_ctx *entry, struct pt_regs *regs)
2476 {
2477 struct stack_frame frame;
2478 const unsigned long __user *fp;
2479
2480 if (perf_guest_cbs && perf_guest_cbs->is_in_guest()) {
2481
2482 return;
2483 }
2484
2485
2486
2487
2488 if (regs->flags & (X86_VM_MASK | PERF_EFLAGS_VM))
2489 return;
2490
2491 fp = (unsigned long __user *)regs->bp;
2492
2493 perf_callchain_store(entry, regs->ip);
2494
2495 if (!nmi_uaccess_okay())
2496 return;
2497
2498 if (perf_callchain_user32(regs, entry))
2499 return;
2500
2501 pagefault_disable();
2502 while (entry->nr < entry->max_stack) {
2503 unsigned long bytes;
2504
2505 frame.next_frame = NULL;
2506 frame.return_address = 0;
2507
2508 if (!valid_user_frame(fp, sizeof(frame)))
2509 break;
2510
2511 bytes = __copy_from_user_nmi(&frame.next_frame, fp, sizeof(*fp));
2512 if (bytes != 0)
2513 break;
2514 bytes = __copy_from_user_nmi(&frame.return_address, fp + 1, sizeof(*fp));
2515 if (bytes != 0)
2516 break;
2517
2518 perf_callchain_store(entry, frame.return_address);
2519 fp = (void __user *)frame.next_frame;
2520 }
2521 pagefault_enable();
2522 }
2523
2524
2525
2526
2527
2528
2529
2530
2531
2532
2533
2534
2535
2536
2537 static unsigned long code_segment_base(struct pt_regs *regs)
2538 {
2539
2540
2541
2542
2543
2544 #ifdef CONFIG_X86_32
2545
2546
2547
2548
2549 if (regs->flags & X86_VM_MASK)
2550 return 0x10 * regs->cs;
2551
2552 if (user_mode(regs) && regs->cs != __USER_CS)
2553 return get_segment_base(regs->cs);
2554 #else
2555 if (user_mode(regs) && !user_64bit_mode(regs) &&
2556 regs->cs != __USER32_CS)
2557 return get_segment_base(regs->cs);
2558 #endif
2559 return 0;
2560 }
2561
2562 unsigned long perf_instruction_pointer(struct pt_regs *regs)
2563 {
2564 if (perf_guest_cbs && perf_guest_cbs->is_in_guest())
2565 return perf_guest_cbs->get_guest_ip();
2566
2567 return regs->ip + code_segment_base(regs);
2568 }
2569
2570 unsigned long perf_misc_flags(struct pt_regs *regs)
2571 {
2572 int misc = 0;
2573
2574 if (perf_guest_cbs && perf_guest_cbs->is_in_guest()) {
2575 if (perf_guest_cbs->is_user_mode())
2576 misc |= PERF_RECORD_MISC_GUEST_USER;
2577 else
2578 misc |= PERF_RECORD_MISC_GUEST_KERNEL;
2579 } else {
2580 if (user_mode(regs))
2581 misc |= PERF_RECORD_MISC_USER;
2582 else
2583 misc |= PERF_RECORD_MISC_KERNEL;
2584 }
2585
2586 if (regs->flags & PERF_EFLAGS_EXACT)
2587 misc |= PERF_RECORD_MISC_EXACT_IP;
2588
2589 return misc;
2590 }
2591
2592 void perf_get_x86_pmu_capability(struct x86_pmu_capability *cap)
2593 {
2594 cap->version = x86_pmu.version;
2595 cap->num_counters_gp = x86_pmu.num_counters;
2596 cap->num_counters_fixed = x86_pmu.num_counters_fixed;
2597 cap->bit_width_gp = x86_pmu.cntval_bits;
2598 cap->bit_width_fixed = x86_pmu.cntval_bits;
2599 cap->events_mask = (unsigned int)x86_pmu.events_maskl;
2600 cap->events_mask_len = x86_pmu.events_mask_len;
2601 }
2602 EXPORT_SYMBOL_GPL(perf_get_x86_pmu_capability);