1
2
3
4
5
6
7 #ifndef __ASM_CPU_SH4_CACHE_H
8 #define __ASM_CPU_SH4_CACHE_H
9
10 #define L1_CACHE_SHIFT 5
11
12 #define SH_CACHE_VALID 1
13 #define SH_CACHE_UPDATED 2
14 #define SH_CACHE_COMBINED 4
15 #define SH_CACHE_ASSOC 8
16
17 #define SH_CCR 0xff00001c
18 #define CCR_CACHE_OCE 0x0001
19 #define CCR_CACHE_WT 0x0002
20 #define CCR_CACHE_CB 0x0004
21 #define CCR_CACHE_OCI 0x0008
22 #define CCR_CACHE_ORA 0x0020
23 #define CCR_CACHE_OIX 0x0080
24 #define CCR_CACHE_ICE 0x0100
25 #define CCR_CACHE_ICI 0x0800
26 #define CCR_CACHE_IIX 0x8000
27 #ifndef CONFIG_CPU_SH4A
28 #define CCR_CACHE_EMODE 0x80000000
29 #endif
30
31
32 #define CCR_CACHE_ENABLE (CCR_CACHE_OCE|CCR_CACHE_ICE)
33 #define CCR_CACHE_INVALIDATE (CCR_CACHE_OCI|CCR_CACHE_ICI)
34
35 #define CACHE_IC_ADDRESS_ARRAY 0xf0000000
36 #define CACHE_OC_ADDRESS_ARRAY 0xf4000000
37
38 #define RAMCR 0xFF000074
39
40 #endif
41