root/arch/sh/include/mach-se/mach/se7721.h

INCLUDED FROM

   1 /* SPDX-License-Identifier: GPL-2.0
   2  *
   3  * Copyright (C) 2008 Renesas Solutions Corp.
   4  *
   5  * Hitachi UL SolutionEngine 7721 Support.
   6  */
   7 
   8 #ifndef __ASM_SH_SE7721_H
   9 #define __ASM_SH_SE7721_H
  10 
  11 #include <linux/sh_intc.h>
  12 #include <asm/addrspace.h>
  13 
  14 /* Box specific addresses. */
  15 #define SE_AREA0_WIDTH  2               /* Area0: 32bit */
  16 #define PA_ROM          0xa0000000      /* EPROM */
  17 #define PA_ROM_SIZE     0x00200000      /* EPROM size 2M byte */
  18 #define PA_FROM         0xa1000000      /* Flash-ROM */
  19 #define PA_FROM_SIZE    0x01000000      /* Flash-ROM size 16M byte */
  20 #define PA_EXT1         0xa4000000
  21 #define PA_EXT1_SIZE    0x04000000
  22 #define PA_SDRAM        0xaC000000      /* SDRAM(Area3) 64MB */
  23 #define PA_SDRAM_SIZE   0x04000000
  24 
  25 #define PA_EXT4         0xb0000000
  26 #define PA_EXT4_SIZE    0x04000000
  27 
  28 #define PA_PERIPHERAL   0xB8000000
  29 
  30 #define PA_PCIC         PA_PERIPHERAL
  31 #define PA_MRSHPC       (PA_PERIPHERAL + 0x003fffe0)
  32 #define PA_MRSHPC_MW1   (PA_PERIPHERAL + 0x00400000)
  33 #define PA_MRSHPC_MW2   (PA_PERIPHERAL + 0x00500000)
  34 #define PA_MRSHPC_IO    (PA_PERIPHERAL + 0x00600000)
  35 #define MRSHPC_OPTION   (PA_MRSHPC + 6)
  36 #define MRSHPC_CSR      (PA_MRSHPC + 8)
  37 #define MRSHPC_ISR      (PA_MRSHPC + 10)
  38 #define MRSHPC_ICR      (PA_MRSHPC + 12)
  39 #define MRSHPC_CPWCR    (PA_MRSHPC + 14)
  40 #define MRSHPC_MW0CR1   (PA_MRSHPC + 16)
  41 #define MRSHPC_MW1CR1   (PA_MRSHPC + 18)
  42 #define MRSHPC_IOWCR1   (PA_MRSHPC + 20)
  43 #define MRSHPC_MW0CR2   (PA_MRSHPC + 22)
  44 #define MRSHPC_MW1CR2   (PA_MRSHPC + 24)
  45 #define MRSHPC_IOWCR2   (PA_MRSHPC + 26)
  46 #define MRSHPC_CDCR     (PA_MRSHPC + 28)
  47 #define MRSHPC_PCIC_INFO        (PA_MRSHPC + 30)
  48 
  49 #define PA_LED          0xB6800000      /* 8bit LED */
  50 #define PA_FPGA         0xB7000000      /* FPGA base address */
  51 
  52 #define MRSHPC_IRQ0     evt2irq(0x340)
  53 
  54 #define FPGA_ILSR1      (PA_FPGA + 0x02)
  55 #define FPGA_ILSR2      (PA_FPGA + 0x03)
  56 #define FPGA_ILSR3      (PA_FPGA + 0x04)
  57 #define FPGA_ILSR4      (PA_FPGA + 0x05)
  58 #define FPGA_ILSR5      (PA_FPGA + 0x06)
  59 #define FPGA_ILSR6      (PA_FPGA + 0x07)
  60 #define FPGA_ILSR7      (PA_FPGA + 0x08)
  61 #define FPGA_ILSR8      (PA_FPGA + 0x09)
  62 
  63 void init_se7721_IRQ(void);
  64 
  65 #define __IO_PREFIX             se7721
  66 #include <asm/io_generic.h>
  67 
  68 #endif  /* __ASM_SH_SE7721_H */