root/arch/sh/include/cpu-sh2a/cpu/cache.h

INCLUDED FROM

   1 /* SPDX-License-Identifier: GPL-2.0
   2  *
   3  * include/asm-sh/cpu-sh2a/cache.h
   4  *
   5  * Copyright (C) 2004 Paul Mundt
   6  */
   7 #ifndef __ASM_CPU_SH2A_CACHE_H
   8 #define __ASM_CPU_SH2A_CACHE_H
   9 
  10 #define L1_CACHE_SHIFT  4
  11 
  12 #define SH_CACHE_VALID          1
  13 #define SH_CACHE_UPDATED        2
  14 #define SH_CACHE_COMBINED       4
  15 #define SH_CACHE_ASSOC          8
  16 
  17 #define SH_CCR          0xfffc1000 /* CCR1 */
  18 #define SH_CCR2         0xfffc1004
  19 
  20 /*
  21  * Most of the SH-2A CCR1 definitions resemble the SH-4 ones. All others not
  22  * listed here are reserved.
  23  */
  24 #define CCR_CACHE_CB    0x0000  /* Hack */
  25 #define CCR_CACHE_OCE   0x0001
  26 #define CCR_CACHE_WT    0x0002
  27 #define CCR_CACHE_OCI   0x0008  /* OCF */
  28 #define CCR_CACHE_ICE   0x0100
  29 #define CCR_CACHE_ICI   0x0800  /* ICF */
  30 
  31 #define CACHE_IC_ADDRESS_ARRAY  0xf0000000
  32 #define CACHE_OC_ADDRESS_ARRAY  0xf0800000
  33 
  34 #define CCR_CACHE_ENABLE        (CCR_CACHE_OCE | CCR_CACHE_ICE)
  35 #define CCR_CACHE_INVALIDATE    (CCR_CACHE_OCI | CCR_CACHE_ICI)
  36 #define CCR_ICACHE_INVALIDATE   CCR_CACHE_ICI
  37 #define CCR_OCACHE_INVALIDATE   CCR_CACHE_OCI
  38 #define CACHE_PHYSADDR_MASK     0x1ffffc00
  39 
  40 #endif /* __ASM_CPU_SH2A_CACHE_H */