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2 #ifndef __ASM_SH_RENESAS_SH7785LCR_H
3 #define __ASM_SH_RENESAS_SH7785LCR_H
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23 #define NOR_FLASH_ADDR 0x00000000
24 #define NOR_FLASH_SIZE 0x04000000
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26 #define PLD_BASE_ADDR 0x04000000
27 #define PLD_PCICR (PLD_BASE_ADDR + 0x00)
28 #define PLD_LCD_BK_CONTR (PLD_BASE_ADDR + 0x02)
29 #define PLD_LOCALCR (PLD_BASE_ADDR + 0x04)
30 #define PLD_POFCR (PLD_BASE_ADDR + 0x06)
31 #define PLD_LEDCR (PLD_BASE_ADDR + 0x08)
32 #define PLD_SWSR (PLD_BASE_ADDR + 0x0a)
33 #define PLD_VERSR (PLD_BASE_ADDR + 0x0c)
34 #define PLD_MMSR (PLD_BASE_ADDR + 0x0e)
35
36 #define PCA9564_ADDR 0x06000000
37 #define PCA9564_SIZE 0x00000100
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39 #define PCA9564_PROTO_32BIT_ADDR 0x14000000
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41 #define SM107_MEM_ADDR 0x10000000
42 #define SM107_MEM_SIZE 0x00e00000
43 #define SM107_REG_ADDR 0x13e00000
44 #define SM107_REG_SIZE 0x00200000
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46 #if defined(CONFIG_SH_SH7785LCR_29BIT_PHYSMAPS)
47 #define R8A66597_ADDR 0x14000000
48 #define CG200_ADDR 0x18000000
49 #else
50 #define R8A66597_ADDR 0x08000000
51 #define CG200_ADDR 0x0c000000
52 #endif
53
54 #define R8A66597_SIZE 0x00000100
55 #define CG200_SIZE 0x00010000
56
57 #endif
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