root/arch/sh/drivers/pci/pci-sh7751.h

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   1 /* SPDX-License-Identifier: GPL-2.0
   2  *
   3  *      Low-Level PCI Support for SH7751 targets
   4  *
   5  *  Dustin McIntire (dustin@sensoria.com) (c) 2001
   6  *  Paul Mundt (lethal@linux-sh.org) (c) 2003
   7  */
   8 
   9 #ifndef _PCI_SH7751_H_
  10 #define _PCI_SH7751_H_
  11 
  12 /* Platform Specific Values */
  13 #define SH7751_VENDOR_ID             0x1054
  14 #define SH7751_DEVICE_ID             0x3505
  15 #define SH7751R_DEVICE_ID            0x350e
  16 
  17 /* SH7751 Specific Values */
  18 #define SH7751_PCI_CONFIG_BASE       0xFD000000  /* Config space base addr */
  19 #define SH7751_PCI_CONFIG_SIZE       0x1000000   /* Config space size */
  20 #define SH7751_PCI_MEMORY_BASE       0xFD000000  /* Memory space base addr */
  21 #define SH7751_PCI_MEM_SIZE          0x01000000  /* Size of Memory window */
  22 #define SH7751_PCI_IO_BASE           0xFE240000  /* IO space base address */
  23 #define SH7751_PCI_IO_SIZE           0x40000     /* Size of IO window */
  24 
  25 #define SH7751_PCIREG_BASE           0xFE200000  /* PCI regs base address */
  26 
  27 #define SH7751_PCICONF0            0x0           /* PCI Config Reg 0 */
  28   #define SH7751_PCICONF0_DEVID      0xFFFF0000  /* Device ID */
  29   #define SH7751_PCICONF0_VNDID      0x0000FFFF  /* Vendor ID */
  30 #define SH7751_PCICONF1            0x4           /* PCI Config Reg 1 */
  31   #define SH7751_PCICONF1_DPE        0x80000000  /* Data Parity Error */
  32   #define SH7751_PCICONF1_SSE        0x40000000  /* System Error Status */
  33   #define SH7751_PCICONF1_RMA        0x20000000  /* Master Abort */
  34   #define SH7751_PCICONF1_RTA        0x10000000  /* Target Abort Rx Status */
  35   #define SH7751_PCICONF1_STA        0x08000000  /* Target Abort Exec Status */
  36   #define SH7751_PCICONF1_DEV        0x06000000  /* Timing Status */
  37   #define SH7751_PCICONF1_DPD        0x01000000  /* Data Parity Status */
  38   #define SH7751_PCICONF1_FBBC       0x00800000  /* Back 2 Back Status */
  39   #define SH7751_PCICONF1_UDF        0x00400000  /* User Defined Status */
  40   #define SH7751_PCICONF1_66M        0x00200000  /* 66Mhz Operation Status */
  41   #define SH7751_PCICONF1_PM         0x00100000  /* Power Management Status */
  42   #define SH7751_PCICONF1_PBBE       0x00000200  /* Back 2 Back Control */
  43   #define SH7751_PCICONF1_SER        0x00000100  /* SERR Output Control */
  44   #define SH7751_PCICONF1_WCC        0x00000080  /* Wait Cycle Control */
  45   #define SH7751_PCICONF1_PER        0x00000040  /* Parity Error Response */
  46   #define SH7751_PCICONF1_VPS        0x00000020  /* VGA Pallet Snoop */
  47   #define SH7751_PCICONF1_MWIE       0x00000010  /* Memory Write+Invalidate */
  48   #define SH7751_PCICONF1_SPC        0x00000008  /* Special Cycle Control */
  49   #define SH7751_PCICONF1_BUM        0x00000004  /* Bus Master Control */
  50   #define SH7751_PCICONF1_MES        0x00000002  /* Memory Space Control */
  51   #define SH7751_PCICONF1_IOS        0x00000001  /* I/O Space Control */
  52 #define SH7751_PCICONF2            0x8           /* PCI Config Reg 2 */
  53   #define SH7751_PCICONF2_BCC        0xFF000000  /* Base Class Code */
  54   #define SH7751_PCICONF2_SCC        0x00FF0000  /* Sub-Class Code */
  55   #define SH7751_PCICONF2_RLPI       0x0000FF00  /* Programming Interface */
  56   #define SH7751_PCICONF2_REV        0x000000FF  /* Revision ID */
  57 #define SH7751_PCICONF3            0xC           /* PCI Config Reg 3 */
  58   #define SH7751_PCICONF3_BIST7      0x80000000  /* Bist Supported */
  59   #define SH7751_PCICONF3_BIST6      0x40000000  /* Bist Executing */
  60   #define SH7751_PCICONF3_BIST3_0    0x0F000000  /* Bist Passed */
  61   #define SH7751_PCICONF3_HD7        0x00800000  /* Single Function device */
  62   #define SH7751_PCICONF3_HD6_0      0x007F0000  /* Configuration Layout */
  63   #define SH7751_PCICONF3_LAT        0x0000FF00  /* Latency Timer */
  64   #define SH7751_PCICONF3_CLS        0x000000FF  /* Cache Line Size */
  65 #define SH7751_PCICONF4            0x10          /* PCI Config Reg 4 */
  66   #define SH7751_PCICONF4_BASE       0xFFFFFFFC  /* I/O Space Base Addr */
  67   #define SH7751_PCICONF4_ASI        0x00000001  /* Address Space Type */
  68 #define SH7751_PCICONF5            0x14          /* PCI Config Reg 5 */
  69   #define SH7751_PCICONF5_BASE       0xFFFFFFF0  /* Mem Space Base Addr */
  70   #define SH7751_PCICONF5_LAP        0x00000008  /* Prefetch Enabled */
  71   #define SH7751_PCICONF5_LAT        0x00000006  /* Local Memory type */
  72   #define SH7751_PCICONF5_ASI        0x00000001  /* Address Space Type */
  73 #define SH7751_PCICONF6            0x18          /* PCI Config Reg 6 */
  74   #define SH7751_PCICONF6_BASE       0xFFFFFFF0  /* Mem Space Base Addr */
  75   #define SH7751_PCICONF6_LAP        0x00000008  /* Prefetch Enabled */
  76   #define SH7751_PCICONF6_LAT        0x00000006  /* Local Memory type */
  77   #define SH7751_PCICONF6_ASI        0x00000001  /* Address Space Type */
  78 /* PCICONF7 - PCICONF10 are undefined */
  79 #define SH7751_PCICONF11           0x2C          /* PCI Config Reg 11 */
  80   #define SH7751_PCICONF11_SSID      0xFFFF0000  /* Subsystem ID */
  81   #define SH7751_PCICONF11_SVID      0x0000FFFF  /* Subsystem Vendor ID */
  82 /* PCICONF12 is undefined */
  83 #define SH7751_PCICONF13           0x34          /* PCI Config Reg 13 */
  84   #define SH7751_PCICONF13_CPTR      0x000000FF  /* PM function pointer */
  85 /* PCICONF14 is undefined */
  86 #define SH7751_PCICONF15           0x3C          /* PCI Config Reg 15 */
  87   #define SH7751_PCICONF15_IPIN      0x000000FF  /* Interrupt Pin */
  88 #define SH7751_PCICONF16           0x40          /* PCI Config Reg 16 */
  89   #define SH7751_PCICONF16_PMES      0xF8000000  /* PME Support */
  90   #define SH7751_PCICONF16_D2S       0x04000000  /* D2 Support */
  91   #define SH7751_PCICONF16_D1S       0x02000000  /* D1 Support */
  92   #define SH7751_PCICONF16_DSI       0x00200000  /* Bit Device Init. */
  93   #define SH7751_PCICONF16_PMCK      0x00080000  /* Clock for PME req. */
  94   #define SH7751_PCICONF16_VER       0x00070000  /* PM Version */
  95   #define SH7751_PCICONF16_NIP       0x0000FF00  /* Next Item Pointer */
  96   #define SH7751_PCICONF16_CID       0x000000FF  /* Capability Identifier */
  97 #define SH7751_PCICONF17           0x44          /* PCI Config Reg 17 */
  98   #define SH7751_PCICONF17_DATA      0xFF000000  /* Data field for PM */
  99   #define SH7751_PCICONF17_PMES      0x00800000  /* PME Status */
 100   #define SH7751_PCICONF17_DSCL      0x00600000  /* Data Scaling Value */
 101   #define SH7751_PCICONF17_DSEL      0x001E0000  /* Data Select */
 102   #define SH7751_PCICONF17_PMEN      0x00010000  /* PME Enable */
 103   #define SH7751_PCICONF17_PWST      0x00000003  /* Power State */
 104 /* SH7715 Internal PCI Registers */
 105 
 106 /* Memory Control Registers */
 107 #define SH7751_BCR1                0xFF800000    /* Memory BCR1 Register */
 108 #define SH7751_BCR2                0xFF800004    /* Memory BCR2 Register */
 109 #define SH7751_BCR3                0xFF800050    /* Memory BCR3 Register */
 110 #define SH7751_BCR4                0xFE0A00F0    /* Memory BCR4 Register */
 111 #define SH7751_WCR1                0xFF800008    /* Wait Control 1 Register */
 112 #define SH7751_WCR2                0xFF80000C    /* Wait Control 2 Register */
 113 #define SH7751_WCR3                0xFF800010    /* Wait Control 3 Register */
 114 #define SH7751_MCR                 0xFF800014    /* Memory Control Register */
 115 
 116 /* General Memory Config Addresses */
 117 #define SH7751_CS0_BASE_ADDR       0x0
 118 #define SH7751_MEM_REGION_SIZE     0x04000000
 119 #define SH7751_CS1_BASE_ADDR       (SH7751_CS0_BASE_ADDR + SH7751_MEM_REGION_SIZE)
 120 #define SH7751_CS2_BASE_ADDR       (SH7751_CS1_BASE_ADDR + SH7751_MEM_REGION_SIZE)
 121 #define SH7751_CS3_BASE_ADDR       (SH7751_CS2_BASE_ADDR + SH7751_MEM_REGION_SIZE)
 122 #define SH7751_CS4_BASE_ADDR       (SH7751_CS3_BASE_ADDR + SH7751_MEM_REGION_SIZE)
 123 #define SH7751_CS5_BASE_ADDR       (SH7751_CS4_BASE_ADDR + SH7751_MEM_REGION_SIZE)
 124 #define SH7751_CS6_BASE_ADDR       (SH7751_CS5_BASE_ADDR + SH7751_MEM_REGION_SIZE)
 125 
 126 #endif /* _PCI_SH7751_H_ */
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