root/arch/sh/boards/mach-se/7343/irq.c

DEFINITIONS

1. se7343_irq_demux
2. se7343_domain_init
3. se7343_gc_init
4. init_7343se_IRQ

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * Hitachi UL SolutionEngine 7343 FPGA IRQ Support.
   4  *
   5  * Copyright (C) 2008  Yoshihiro Shimoda
   6  * Copyright (C) 2012  Paul Mundt
   7  *
   8  * Based on linux/arch/sh/boards/se/7343/irq.c
   9  * Copyright (C) 2007  Nobuhiro Iwamatsu
  10  */
  11 #define DRV_NAME "SE7343-FPGA"
  12 #define pr_fmt(fmt) DRV_NAME ": " fmt
  13 
  14 #include <linux/init.h>
  15 #include <linux/irq.h>
  16 #include <linux/interrupt.h>
  17 #include <linux/irqdomain.h>
  18 #include <linux/io.h>
  19 #include <linux/sizes.h>
  20 #include <mach-se/mach/se7343.h>
  21 
  22 #define PA_CPLD_BASE_ADDR       0x11400000
  23 #define PA_CPLD_ST_REG          0x08    /* CPLD Interrupt status register */
  24 #define PA_CPLD_IMSK_REG        0x0a    /* CPLD Interrupt mask register */
  25 
  26 static void __iomem *se7343_irq_regs;
  27 struct irq_domain *se7343_irq_domain;
  28 
  29 static void se7343_irq_demux(struct irq_desc *desc)
  30 {
  31         struct irq_data *data = irq_desc_get_irq_data(desc);
  32         struct irq_chip *chip = irq_data_get_irq_chip(data);
  33         unsigned long mask;
  34         int bit;
  35 
  36         chip->irq_mask_ack(data);
  37 
  38         mask = ioread16(se7343_irq_regs + PA_CPLD_ST_REG);
  39 
  40         for_each_set_bit(bit, &mask, SE7343_FPGA_IRQ_NR)
  41                 generic_handle_irq(irq_linear_revmap(se7343_irq_domain, bit));
  42 
  43         chip->irq_unmask(data);
  44 }
  45 
  46 static void __init se7343_domain_init(void)
  47 {
  48         int i;
  49 
  50         se7343_irq_domain = irq_domain_add_linear(NULL, SE7343_FPGA_IRQ_NR,
  51                                                   &irq_domain_simple_ops, NULL);
  52         if (unlikely(!se7343_irq_domain)) {
  53                 printk("Failed to get IRQ domain\n");
  54                 return;
  55         }
  56 
  57         for (i = 0; i < SE7343_FPGA_IRQ_NR; i++) {
  58                 int irq = irq_create_mapping(se7343_irq_domain, i);
  59 
  60                 if (unlikely(irq == 0)) {
  61                         printk("Failed to allocate IRQ %d\n", i);
  62                         return;
  63                 }
  64         }
  65 }
  66 
  67 static void __init se7343_gc_init(void)
  68 {
  69         struct irq_chip_generic *gc;
  70         struct irq_chip_type *ct;
  71         unsigned int irq_base;
  72 
  73         irq_base = irq_linear_revmap(se7343_irq_domain, 0);
  74 
  75         gc = irq_alloc_generic_chip(DRV_NAME, 1, irq_base, se7343_irq_regs,
  76                                     handle_level_irq);
  77         if (unlikely(!gc))
  78                 return;
  79 
  80         ct = gc->chip_types;
  81         ct->chip.irq_mask = irq_gc_mask_set_bit;
  82         ct->chip.irq_unmask = irq_gc_mask_clr_bit;
  83 
  84         ct->regs.mask = PA_CPLD_IMSK_REG;
  85 
  86         irq_setup_generic_chip(gc, IRQ_MSK(SE7343_FPGA_IRQ_NR),
  87                                IRQ_GC_INIT_MASK_CACHE,
  88                                IRQ_NOREQUEST | IRQ_NOPROBE, 0);
  89 
  90         irq_set_chained_handler(IRQ0_IRQ, se7343_irq_demux);
  91         irq_set_irq_type(IRQ0_IRQ, IRQ_TYPE_LEVEL_LOW);
  92 
  93         irq_set_chained_handler(IRQ1_IRQ, se7343_irq_demux);
  94         irq_set_irq_type(IRQ1_IRQ, IRQ_TYPE_LEVEL_LOW);
  95 
  96         irq_set_chained_handler(IRQ4_IRQ, se7343_irq_demux);
  97         irq_set_irq_type(IRQ4_IRQ, IRQ_TYPE_LEVEL_LOW);
  98 
  99         irq_set_chained_handler(IRQ5_IRQ, se7343_irq_demux);
 100         irq_set_irq_type(IRQ5_IRQ, IRQ_TYPE_LEVEL_LOW);
 101 }
 102 
 103 /*
 104  * Initialize IRQ setting
 105  */
 106 void __init init_7343se_IRQ(void)
 107 {
 108         se7343_irq_regs = ioremap(PA_CPLD_BASE_ADDR, SZ_16);
 109         if (unlikely(!se7343_irq_regs)) {
 110                 pr_err("Failed to remap CPLD\n");
 111                 return;
 112         }
 113 
 114         /*
 115          * All FPGA IRQs disabled by default
 116          */
 117         iowrite16(0, se7343_irq_regs + PA_CPLD_IMSK_REG);
 118 
 119         __raw_writew(0x2000, 0xb03fffec);       /* mrshpc irq enable */
 120 
 121         se7343_domain_init();
 122         se7343_gc_init();
 123 }