This source file includes following definitions.
- usb_port_power
- sh7264_devices_setup
- plat_irq_setup
- plat_early_device_setup
1
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6
7 #include <linux/platform_device.h>
8 #include <linux/init.h>
9 #include <linux/serial.h>
10 #include <linux/serial_sci.h>
11 #include <linux/usb/r8a66597.h>
12 #include <linux/sh_timer.h>
13 #include <linux/io.h>
14
15 enum {
16 UNUSED = 0,
17
18
19 IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7,
20 PINT0, PINT1, PINT2, PINT3, PINT4, PINT5, PINT6, PINT7,
21
22 DMAC0, DMAC1, DMAC2, DMAC3, DMAC4, DMAC5, DMAC6, DMAC7,
23 DMAC8, DMAC9, DMAC10, DMAC11, DMAC12, DMAC13, DMAC14, DMAC15,
24 USB, VDC3, CMT0, CMT1, BSC, WDT,
25 MTU0_ABCD, MTU0_VEF, MTU1_AB, MTU1_VU, MTU2_AB, MTU2_VU,
26 MTU3_ABCD, MTU3_TCI3V, MTU4_ABCD, MTU4_TCI4V,
27 PWMT1, PWMT2, ADC_ADI,
28 SSIF0, SSII1, SSII2, SSII3,
29 RSPDIF,
30 IIC30, IIC31, IIC32, IIC33,
31 SCIF0_BRI, SCIF0_ERI, SCIF0_RXI, SCIF0_TXI,
32 SCIF1_BRI, SCIF1_ERI, SCIF1_RXI, SCIF1_TXI,
33 SCIF2_BRI, SCIF2_ERI, SCIF2_RXI, SCIF2_TXI,
34 SCIF3_BRI, SCIF3_ERI, SCIF3_RXI, SCIF3_TXI,
35 SCIF4_BRI, SCIF4_ERI, SCIF4_RXI, SCIF4_TXI,
36 SCIF5_BRI, SCIF5_ERI, SCIF5_RXI, SCIF5_TXI,
37 SCIF6_BRI, SCIF6_ERI, SCIF6_RXI, SCIF6_TXI,
38 SCIF7_BRI, SCIF7_ERI, SCIF7_RXI, SCIF7_TXI,
39 SIO_FIFO, RSPIC0, RSPIC1,
40 RCAN0, RCAN1, IEBC, CD_ROMD,
41 NFMC, SDHI, RTC,
42 SRCC0, SRCC1, DCOMU, OFFI, IFEI,
43
44
45 PINT, SCIF0, SCIF1, SCIF2, SCIF3, SCIF4, SCIF5, SCIF6, SCIF7,
46 };
47
48 static struct intc_vect vectors[] __initdata = {
49 INTC_IRQ(IRQ0, 64), INTC_IRQ(IRQ1, 65),
50 INTC_IRQ(IRQ2, 66), INTC_IRQ(IRQ3, 67),
51 INTC_IRQ(IRQ4, 68), INTC_IRQ(IRQ5, 69),
52 INTC_IRQ(IRQ6, 70), INTC_IRQ(IRQ7, 71),
53
54 INTC_IRQ(PINT0, 80), INTC_IRQ(PINT1, 81),
55 INTC_IRQ(PINT2, 82), INTC_IRQ(PINT3, 83),
56 INTC_IRQ(PINT4, 84), INTC_IRQ(PINT5, 85),
57 INTC_IRQ(PINT6, 86), INTC_IRQ(PINT7, 87),
58
59 INTC_IRQ(DMAC0, 108), INTC_IRQ(DMAC0, 109),
60 INTC_IRQ(DMAC1, 112), INTC_IRQ(DMAC1, 113),
61 INTC_IRQ(DMAC2, 116), INTC_IRQ(DMAC2, 117),
62 INTC_IRQ(DMAC3, 120), INTC_IRQ(DMAC3, 121),
63 INTC_IRQ(DMAC4, 124), INTC_IRQ(DMAC4, 125),
64 INTC_IRQ(DMAC5, 128), INTC_IRQ(DMAC5, 129),
65 INTC_IRQ(DMAC6, 132), INTC_IRQ(DMAC6, 133),
66 INTC_IRQ(DMAC7, 136), INTC_IRQ(DMAC7, 137),
67 INTC_IRQ(DMAC8, 140), INTC_IRQ(DMAC8, 141),
68 INTC_IRQ(DMAC9, 144), INTC_IRQ(DMAC9, 145),
69 INTC_IRQ(DMAC10, 148), INTC_IRQ(DMAC10, 149),
70 INTC_IRQ(DMAC11, 152), INTC_IRQ(DMAC11, 153),
71 INTC_IRQ(DMAC12, 156), INTC_IRQ(DMAC12, 157),
72 INTC_IRQ(DMAC13, 160), INTC_IRQ(DMAC13, 161),
73 INTC_IRQ(DMAC14, 164), INTC_IRQ(DMAC14, 165),
74 INTC_IRQ(DMAC15, 168), INTC_IRQ(DMAC15, 169),
75
76 INTC_IRQ(USB, 170),
77 INTC_IRQ(VDC3, 171), INTC_IRQ(VDC3, 172),
78 INTC_IRQ(VDC3, 173), INTC_IRQ(VDC3, 174),
79 INTC_IRQ(CMT0, 175), INTC_IRQ(CMT1, 176),
80 INTC_IRQ(BSC, 177), INTC_IRQ(WDT, 178),
81
82 INTC_IRQ(MTU0_ABCD, 179), INTC_IRQ(MTU0_ABCD, 180),
83 INTC_IRQ(MTU0_ABCD, 181), INTC_IRQ(MTU0_ABCD, 182),
84 INTC_IRQ(MTU0_VEF, 183),
85 INTC_IRQ(MTU0_VEF, 184), INTC_IRQ(MTU0_VEF, 185),
86 INTC_IRQ(MTU1_AB, 186), INTC_IRQ(MTU1_AB, 187),
87 INTC_IRQ(MTU1_VU, 188), INTC_IRQ(MTU1_VU, 189),
88 INTC_IRQ(MTU2_AB, 190), INTC_IRQ(MTU2_AB, 191),
89 INTC_IRQ(MTU2_VU, 192), INTC_IRQ(MTU2_VU, 193),
90 INTC_IRQ(MTU3_ABCD, 194), INTC_IRQ(MTU3_ABCD, 195),
91 INTC_IRQ(MTU3_ABCD, 196), INTC_IRQ(MTU3_ABCD, 197),
92 INTC_IRQ(MTU3_TCI3V, 198),
93 INTC_IRQ(MTU4_ABCD, 199), INTC_IRQ(MTU4_ABCD, 200),
94 INTC_IRQ(MTU4_ABCD, 201), INTC_IRQ(MTU4_ABCD, 202),
95 INTC_IRQ(MTU4_TCI4V, 203),
96
97 INTC_IRQ(PWMT1, 204), INTC_IRQ(PWMT2, 205),
98
99 INTC_IRQ(ADC_ADI, 206),
100
101 INTC_IRQ(SSIF0, 207), INTC_IRQ(SSIF0, 208),
102 INTC_IRQ(SSIF0, 209),
103 INTC_IRQ(SSII1, 210), INTC_IRQ(SSII1, 211),
104 INTC_IRQ(SSII2, 212), INTC_IRQ(SSII2, 213),
105 INTC_IRQ(SSII3, 214), INTC_IRQ(SSII3, 215),
106
107 INTC_IRQ(RSPDIF, 216),
108
109 INTC_IRQ(IIC30, 217), INTC_IRQ(IIC30, 218),
110 INTC_IRQ(IIC30, 219), INTC_IRQ(IIC30, 220),
111 INTC_IRQ(IIC30, 221),
112 INTC_IRQ(IIC31, 222), INTC_IRQ(IIC31, 223),
113 INTC_IRQ(IIC31, 224), INTC_IRQ(IIC31, 225),
114 INTC_IRQ(IIC31, 226),
115 INTC_IRQ(IIC32, 227), INTC_IRQ(IIC32, 228),
116 INTC_IRQ(IIC32, 229), INTC_IRQ(IIC32, 230),
117 INTC_IRQ(IIC32, 231),
118
119 INTC_IRQ(SCIF0_BRI, 232), INTC_IRQ(SCIF0_ERI, 233),
120 INTC_IRQ(SCIF0_RXI, 234), INTC_IRQ(SCIF0_TXI, 235),
121 INTC_IRQ(SCIF1_BRI, 236), INTC_IRQ(SCIF1_ERI, 237),
122 INTC_IRQ(SCIF1_RXI, 238), INTC_IRQ(SCIF1_TXI, 239),
123 INTC_IRQ(SCIF2_BRI, 240), INTC_IRQ(SCIF2_ERI, 241),
124 INTC_IRQ(SCIF2_RXI, 242), INTC_IRQ(SCIF2_TXI, 243),
125 INTC_IRQ(SCIF3_BRI, 244), INTC_IRQ(SCIF3_ERI, 245),
126 INTC_IRQ(SCIF3_RXI, 246), INTC_IRQ(SCIF3_TXI, 247),
127 INTC_IRQ(SCIF4_BRI, 248), INTC_IRQ(SCIF4_ERI, 249),
128 INTC_IRQ(SCIF4_RXI, 250), INTC_IRQ(SCIF4_TXI, 251),
129 INTC_IRQ(SCIF5_BRI, 252), INTC_IRQ(SCIF5_ERI, 253),
130 INTC_IRQ(SCIF5_RXI, 254), INTC_IRQ(SCIF5_TXI, 255),
131 INTC_IRQ(SCIF6_BRI, 256), INTC_IRQ(SCIF6_ERI, 257),
132 INTC_IRQ(SCIF6_RXI, 258), INTC_IRQ(SCIF6_TXI, 259),
133 INTC_IRQ(SCIF7_BRI, 260), INTC_IRQ(SCIF7_ERI, 261),
134 INTC_IRQ(SCIF7_RXI, 262), INTC_IRQ(SCIF7_TXI, 263),
135
136 INTC_IRQ(SIO_FIFO, 264),
137
138 INTC_IRQ(RSPIC0, 265), INTC_IRQ(RSPIC0, 266),
139 INTC_IRQ(RSPIC0, 267),
140 INTC_IRQ(RSPIC1, 268), INTC_IRQ(RSPIC1, 269),
141 INTC_IRQ(RSPIC1, 270),
142
143 INTC_IRQ(RCAN0, 271), INTC_IRQ(RCAN0, 272),
144 INTC_IRQ(RCAN0, 273), INTC_IRQ(RCAN0, 274),
145 INTC_IRQ(RCAN0, 275),
146 INTC_IRQ(RCAN1, 276), INTC_IRQ(RCAN1, 277),
147 INTC_IRQ(RCAN1, 278), INTC_IRQ(RCAN1, 279),
148 INTC_IRQ(RCAN1, 280),
149
150 INTC_IRQ(IEBC, 281),
151
152 INTC_IRQ(CD_ROMD, 282), INTC_IRQ(CD_ROMD, 283),
153 INTC_IRQ(CD_ROMD, 284), INTC_IRQ(CD_ROMD, 285),
154 INTC_IRQ(CD_ROMD, 286), INTC_IRQ(CD_ROMD, 287),
155
156 INTC_IRQ(NFMC, 288), INTC_IRQ(NFMC, 289),
157 INTC_IRQ(NFMC, 290), INTC_IRQ(NFMC, 291),
158
159 INTC_IRQ(SDHI, 292), INTC_IRQ(SDHI, 293),
160 INTC_IRQ(SDHI, 294),
161
162 INTC_IRQ(RTC, 296), INTC_IRQ(RTC, 297),
163 INTC_IRQ(RTC, 298),
164
165 INTC_IRQ(SRCC0, 299), INTC_IRQ(SRCC0, 300),
166 INTC_IRQ(SRCC0, 301), INTC_IRQ(SRCC0, 302),
167 INTC_IRQ(SRCC0, 303),
168 INTC_IRQ(SRCC1, 304), INTC_IRQ(SRCC1, 305),
169 INTC_IRQ(SRCC1, 306), INTC_IRQ(SRCC1, 307),
170 INTC_IRQ(SRCC1, 308),
171
172 INTC_IRQ(DCOMU, 310), INTC_IRQ(DCOMU, 311),
173 INTC_IRQ(DCOMU, 312),
174 };
175
176 static struct intc_group groups[] __initdata = {
177 INTC_GROUP(PINT, PINT0, PINT1, PINT2, PINT3,
178 PINT4, PINT5, PINT6, PINT7),
179 INTC_GROUP(SCIF0, SCIF0_BRI, SCIF0_ERI, SCIF0_RXI, SCIF0_TXI),
180 INTC_GROUP(SCIF1, SCIF1_BRI, SCIF1_ERI, SCIF1_RXI, SCIF1_TXI),
181 INTC_GROUP(SCIF2, SCIF2_BRI, SCIF2_ERI, SCIF2_RXI, SCIF2_TXI),
182 INTC_GROUP(SCIF3, SCIF3_BRI, SCIF3_ERI, SCIF3_RXI, SCIF3_TXI),
183 INTC_GROUP(SCIF4, SCIF4_BRI, SCIF4_ERI, SCIF4_RXI, SCIF4_TXI),
184 INTC_GROUP(SCIF5, SCIF5_BRI, SCIF5_ERI, SCIF5_RXI, SCIF5_TXI),
185 INTC_GROUP(SCIF6, SCIF6_BRI, SCIF6_ERI, SCIF6_RXI, SCIF6_TXI),
186 INTC_GROUP(SCIF7, SCIF7_BRI, SCIF7_ERI, SCIF7_RXI, SCIF7_TXI),
187 };
188
189 static struct intc_prio_reg prio_registers[] __initdata = {
190 { 0xfffe0818, 0, 16, 4, { IRQ0, IRQ1, IRQ2, IRQ3 } },
191 { 0xfffe081a, 0, 16, 4, { IRQ4, IRQ5, IRQ6, IRQ7 } },
192 { 0xfffe0820, 0, 16, 4, { PINT, 0, 0, 0 } },
193 { 0xfffe0c00, 0, 16, 4, { DMAC0, DMAC1, DMAC2, DMAC3 } },
194 { 0xfffe0c02, 0, 16, 4, { DMAC4, DMAC5, DMAC6, DMAC7 } },
195 { 0xfffe0c04, 0, 16, 4, { DMAC8, DMAC9,
196 DMAC10, DMAC11 } },
197 { 0xfffe0c06, 0, 16, 4, { DMAC12, DMAC13,
198 DMAC14, DMAC15 } },
199 { 0xfffe0c08, 0, 16, 4, { USB, VDC3, CMT0, CMT1 } },
200 { 0xfffe0c0a, 0, 16, 4, { BSC, WDT, MTU0_ABCD, MTU0_VEF } },
201 { 0xfffe0c0c, 0, 16, 4, { MTU1_AB, MTU1_VU,
202 MTU2_AB, MTU2_VU } },
203 { 0xfffe0c0e, 0, 16, 4, { MTU3_ABCD, MTU3_TCI3V,
204 MTU4_ABCD, MTU4_TCI4V } },
205 { 0xfffe0c10, 0, 16, 4, { PWMT1, PWMT2, ADC_ADI, 0 } },
206 { 0xfffe0c12, 0, 16, 4, { SSIF0, SSII1, SSII2, SSII3 } },
207 { 0xfffe0c14, 0, 16, 4, { RSPDIF, IIC30, IIC31, IIC32 } },
208 { 0xfffe0c16, 0, 16, 4, { SCIF0, SCIF1, SCIF2, SCIF3 } },
209 { 0xfffe0c18, 0, 16, 4, { SCIF4, SCIF5, SCIF6, SCIF7 } },
210 { 0xfffe0c1a, 0, 16, 4, { SIO_FIFO, 0, RSPIC0, RSPIC1, } },
211 { 0xfffe0c1c, 0, 16, 4, { RCAN0, RCAN1, IEBC, CD_ROMD } },
212 { 0xfffe0c1e, 0, 16, 4, { NFMC, SDHI, RTC, 0 } },
213 { 0xfffe0c20, 0, 16, 4, { SRCC0, SRCC1, 0, DCOMU } },
214 };
215
216 static struct intc_mask_reg mask_registers[] __initdata = {
217 { 0xfffe0808, 0, 16,
218 { 0, 0, 0, 0, 0, 0, 0, 0,
219 PINT7, PINT6, PINT5, PINT4, PINT3, PINT2, PINT1, PINT0 } },
220 };
221
222 static DECLARE_INTC_DESC(intc_desc, "sh7264", vectors, groups,
223 mask_registers, prio_registers, NULL);
224
225 static struct plat_sci_port scif0_platform_data = {
226 .scscr = SCSCR_REIE,
227 .type = PORT_SCIF,
228 .regtype = SCIx_SH2_SCIF_FIFODATA_REGTYPE,
229 };
230
231 static struct resource scif0_resources[] = {
232 DEFINE_RES_MEM(0xfffe8000, 0x100),
233 DEFINE_RES_IRQ(233),
234 DEFINE_RES_IRQ(234),
235 DEFINE_RES_IRQ(235),
236 DEFINE_RES_IRQ(232),
237 };
238
239 static struct platform_device scif0_device = {
240 .name = "sh-sci",
241 .id = 0,
242 .resource = scif0_resources,
243 .num_resources = ARRAY_SIZE(scif0_resources),
244 .dev = {
245 .platform_data = &scif0_platform_data,
246 },
247 };
248
249 static struct plat_sci_port scif1_platform_data = {
250 .scscr = SCSCR_REIE,
251 .type = PORT_SCIF,
252 .regtype = SCIx_SH2_SCIF_FIFODATA_REGTYPE,
253 };
254
255 static struct resource scif1_resources[] = {
256 DEFINE_RES_MEM(0xfffe8800, 0x100),
257 DEFINE_RES_IRQ(237),
258 DEFINE_RES_IRQ(238),
259 DEFINE_RES_IRQ(239),
260 DEFINE_RES_IRQ(236),
261 };
262
263 static struct platform_device scif1_device = {
264 .name = "sh-sci",
265 .id = 1,
266 .resource = scif1_resources,
267 .num_resources = ARRAY_SIZE(scif1_resources),
268 .dev = {
269 .platform_data = &scif1_platform_data,
270 },
271 };
272
273 static struct plat_sci_port scif2_platform_data = {
274 .scscr = SCSCR_REIE,
275 .type = PORT_SCIF,
276 .regtype = SCIx_SH2_SCIF_FIFODATA_REGTYPE,
277 };
278
279 static struct resource scif2_resources[] = {
280 DEFINE_RES_MEM(0xfffe9000, 0x100),
281 DEFINE_RES_IRQ(241),
282 DEFINE_RES_IRQ(242),
283 DEFINE_RES_IRQ(243),
284 DEFINE_RES_IRQ(240),
285 };
286
287 static struct platform_device scif2_device = {
288 .name = "sh-sci",
289 .id = 2,
290 .resource = scif2_resources,
291 .num_resources = ARRAY_SIZE(scif2_resources),
292 .dev = {
293 .platform_data = &scif2_platform_data,
294 },
295 };
296
297 static struct plat_sci_port scif3_platform_data = {
298 .scscr = SCSCR_REIE,
299 .type = PORT_SCIF,
300 .regtype = SCIx_SH2_SCIF_FIFODATA_REGTYPE,
301 };
302
303 static struct resource scif3_resources[] = {
304 DEFINE_RES_MEM(0xfffe9800, 0x100),
305 DEFINE_RES_IRQ(245),
306 DEFINE_RES_IRQ(246),
307 DEFINE_RES_IRQ(247),
308 DEFINE_RES_IRQ(244),
309 };
310
311 static struct platform_device scif3_device = {
312 .name = "sh-sci",
313 .id = 3,
314 .resource = scif3_resources,
315 .num_resources = ARRAY_SIZE(scif3_resources),
316 .dev = {
317 .platform_data = &scif3_platform_data,
318 },
319 };
320
321 static struct plat_sci_port scif4_platform_data = {
322 .scscr = SCSCR_REIE,
323 .type = PORT_SCIF,
324 .regtype = SCIx_SH2_SCIF_FIFODATA_REGTYPE,
325 };
326
327 static struct resource scif4_resources[] = {
328 DEFINE_RES_MEM(0xfffea000, 0x100),
329 DEFINE_RES_IRQ(249),
330 DEFINE_RES_IRQ(250),
331 DEFINE_RES_IRQ(251),
332 DEFINE_RES_IRQ(248),
333 };
334
335 static struct platform_device scif4_device = {
336 .name = "sh-sci",
337 .id = 4,
338 .resource = scif4_resources,
339 .num_resources = ARRAY_SIZE(scif4_resources),
340 .dev = {
341 .platform_data = &scif4_platform_data,
342 },
343 };
344
345 static struct plat_sci_port scif5_platform_data = {
346 .scscr = SCSCR_REIE,
347 .type = PORT_SCIF,
348 .regtype = SCIx_SH2_SCIF_FIFODATA_REGTYPE,
349 };
350
351 static struct resource scif5_resources[] = {
352 DEFINE_RES_MEM(0xfffea800, 0x100),
353 DEFINE_RES_IRQ(253),
354 DEFINE_RES_IRQ(254),
355 DEFINE_RES_IRQ(255),
356 DEFINE_RES_IRQ(252),
357 };
358
359 static struct platform_device scif5_device = {
360 .name = "sh-sci",
361 .id = 5,
362 .resource = scif5_resources,
363 .num_resources = ARRAY_SIZE(scif5_resources),
364 .dev = {
365 .platform_data = &scif5_platform_data,
366 },
367 };
368
369 static struct plat_sci_port scif6_platform_data = {
370 .scscr = SCSCR_REIE,
371 .type = PORT_SCIF,
372 .regtype = SCIx_SH2_SCIF_FIFODATA_REGTYPE,
373 };
374
375 static struct resource scif6_resources[] = {
376 DEFINE_RES_MEM(0xfffeb000, 0x100),
377 DEFINE_RES_IRQ(257),
378 DEFINE_RES_IRQ(258),
379 DEFINE_RES_IRQ(259),
380 DEFINE_RES_IRQ(256),
381 };
382
383 static struct platform_device scif6_device = {
384 .name = "sh-sci",
385 .id = 6,
386 .resource = scif6_resources,
387 .num_resources = ARRAY_SIZE(scif6_resources),
388 .dev = {
389 .platform_data = &scif6_platform_data,
390 },
391 };
392
393 static struct plat_sci_port scif7_platform_data = {
394 .scscr = SCSCR_REIE,
395 .type = PORT_SCIF,
396 .regtype = SCIx_SH2_SCIF_FIFODATA_REGTYPE,
397 };
398
399 static struct resource scif7_resources[] = {
400 DEFINE_RES_MEM(0xfffeb800, 0x100),
401 DEFINE_RES_IRQ(261),
402 DEFINE_RES_IRQ(262),
403 DEFINE_RES_IRQ(263),
404 DEFINE_RES_IRQ(260),
405 };
406
407 static struct platform_device scif7_device = {
408 .name = "sh-sci",
409 .id = 7,
410 .resource = scif7_resources,
411 .num_resources = ARRAY_SIZE(scif7_resources),
412 .dev = {
413 .platform_data = &scif7_platform_data,
414 },
415 };
416
417 static struct sh_timer_config cmt_platform_data = {
418 .channels_mask = 3,
419 };
420
421 static struct resource cmt_resources[] = {
422 DEFINE_RES_MEM(0xfffec000, 0x10),
423 DEFINE_RES_IRQ(175),
424 DEFINE_RES_IRQ(176),
425 };
426
427 static struct platform_device cmt_device = {
428 .name = "sh-cmt-16",
429 .id = 0,
430 .dev = {
431 .platform_data = &cmt_platform_data,
432 },
433 .resource = cmt_resources,
434 .num_resources = ARRAY_SIZE(cmt_resources),
435 };
436
437 static struct resource mtu2_resources[] = {
438 DEFINE_RES_MEM(0xfffe4000, 0x400),
439 DEFINE_RES_IRQ_NAMED(179, "tgi0a"),
440 DEFINE_RES_IRQ_NAMED(186, "tgi1a"),
441 };
442
443 static struct platform_device mtu2_device = {
444 .name = "sh-mtu2",
445 .id = -1,
446 .resource = mtu2_resources,
447 .num_resources = ARRAY_SIZE(mtu2_resources),
448 };
449
450 static struct resource rtc_resources[] = {
451 [0] = {
452 .start = 0xfffe6000,
453 .end = 0xfffe6000 + 0x30 - 1,
454 .flags = IORESOURCE_IO,
455 },
456 [1] = {
457
458 .start = 296,
459 .flags = IORESOURCE_IRQ,
460 },
461 };
462
463 static struct platform_device rtc_device = {
464 .name = "sh-rtc",
465 .id = -1,
466 .num_resources = ARRAY_SIZE(rtc_resources),
467 .resource = rtc_resources,
468 };
469
470
471 static void usb_port_power(int port, int power)
472 {
473 __raw_writew(0x200 , 0xffffc0c2) ;
474 }
475
476 static struct r8a66597_platdata r8a66597_data = {
477 .on_chip = 1,
478 .endian = 1,
479 .port_power = usb_port_power,
480 };
481
482 static struct resource r8a66597_usb_host_resources[] = {
483 [0] = {
484 .start = 0xffffc000,
485 .end = 0xffffc0e4,
486 .flags = IORESOURCE_MEM,
487 },
488 [1] = {
489 .start = 170,
490 .end = 170,
491 .flags = IORESOURCE_IRQ | IRQF_TRIGGER_LOW,
492 },
493 };
494
495 static struct platform_device r8a66597_usb_host_device = {
496 .name = "r8a66597_hcd",
497 .id = 0,
498 .dev = {
499 .dma_mask = NULL,
500 .coherent_dma_mask = 0xffffffff,
501 .platform_data = &r8a66597_data,
502 },
503 .num_resources = ARRAY_SIZE(r8a66597_usb_host_resources),
504 .resource = r8a66597_usb_host_resources,
505 };
506
507 static struct platform_device *sh7264_devices[] __initdata = {
508 &scif0_device,
509 &scif1_device,
510 &scif2_device,
511 &scif3_device,
512 &scif4_device,
513 &scif5_device,
514 &scif6_device,
515 &scif7_device,
516 &cmt_device,
517 &mtu2_device,
518 &rtc_device,
519 &r8a66597_usb_host_device,
520 };
521
522 static int __init sh7264_devices_setup(void)
523 {
524 return platform_add_devices(sh7264_devices,
525 ARRAY_SIZE(sh7264_devices));
526 }
527 arch_initcall(sh7264_devices_setup);
528
529 void __init plat_irq_setup(void)
530 {
531 register_intc_controller(&intc_desc);
532 }
533
534 static struct platform_device *sh7264_early_devices[] __initdata = {
535 &scif0_device,
536 &scif1_device,
537 &scif2_device,
538 &scif3_device,
539 &scif4_device,
540 &scif5_device,
541 &scif6_device,
542 &scif7_device,
543 &cmt_device,
544 &mtu2_device,
545 };
546
547 void __init plat_early_device_setup(void)
548 {
549 early_platform_add_devices(sh7264_early_devices,
550 ARRAY_SIZE(sh7264_early_devices));
551 }