This source file includes following definitions.
- mxg_devices_setup
- plat_irq_setup
- plat_early_device_setup
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6
7 #include <linux/platform_device.h>
8 #include <linux/init.h>
9 #include <linux/serial.h>
10 #include <linux/serial_sci.h>
11 #include <linux/sh_timer.h>
12
13 enum {
14 UNUSED = 0,
15
16
17 IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7,
18 IRQ8, IRQ9, IRQ10, IRQ11, IRQ12, IRQ13, IRQ14, IRQ15,
19
20 PINT0, PINT1, PINT2, PINT3, PINT4, PINT5, PINT6, PINT7,
21 SINT8, SINT7, SINT6, SINT5, SINT4, SINT3, SINT2, SINT1,
22
23 SCIF0, SCIF1,
24
25 MTU2_GROUP1, MTU2_GROUP2, MTU2_GROUP3, MTU2_GROUP4, MTU2_GROUP5,
26 MTU2_TGI3B, MTU2_TGI3C,
27
28
29 PINT,
30 };
31
32 static struct intc_vect vectors[] __initdata = {
33 INTC_IRQ(IRQ0, 64), INTC_IRQ(IRQ1, 65),
34 INTC_IRQ(IRQ2, 66), INTC_IRQ(IRQ3, 67),
35 INTC_IRQ(IRQ4, 68), INTC_IRQ(IRQ5, 69),
36 INTC_IRQ(IRQ6, 70), INTC_IRQ(IRQ7, 71),
37 INTC_IRQ(IRQ8, 72), INTC_IRQ(IRQ9, 73),
38 INTC_IRQ(IRQ10, 74), INTC_IRQ(IRQ11, 75),
39 INTC_IRQ(IRQ12, 76), INTC_IRQ(IRQ13, 77),
40 INTC_IRQ(IRQ14, 78), INTC_IRQ(IRQ15, 79),
41
42 INTC_IRQ(PINT0, 80), INTC_IRQ(PINT1, 81),
43 INTC_IRQ(PINT2, 82), INTC_IRQ(PINT3, 83),
44 INTC_IRQ(PINT4, 84), INTC_IRQ(PINT5, 85),
45 INTC_IRQ(PINT6, 86), INTC_IRQ(PINT7, 87),
46
47 INTC_IRQ(SINT8, 94), INTC_IRQ(SINT7, 95),
48 INTC_IRQ(SINT6, 96), INTC_IRQ(SINT5, 97),
49 INTC_IRQ(SINT4, 98), INTC_IRQ(SINT3, 99),
50 INTC_IRQ(SINT2, 100), INTC_IRQ(SINT1, 101),
51
52 INTC_IRQ(SCIF0, 220), INTC_IRQ(SCIF0, 221),
53 INTC_IRQ(SCIF0, 222), INTC_IRQ(SCIF0, 223),
54 INTC_IRQ(SCIF1, 224), INTC_IRQ(SCIF1, 225),
55 INTC_IRQ(SCIF1, 226), INTC_IRQ(SCIF1, 227),
56
57 INTC_IRQ(MTU2_GROUP1, 228), INTC_IRQ(MTU2_GROUP1, 229),
58 INTC_IRQ(MTU2_GROUP1, 230), INTC_IRQ(MTU2_GROUP1, 231),
59 INTC_IRQ(MTU2_GROUP1, 232), INTC_IRQ(MTU2_GROUP1, 233),
60
61 INTC_IRQ(MTU2_GROUP2, 234), INTC_IRQ(MTU2_GROUP2, 235),
62 INTC_IRQ(MTU2_GROUP2, 236), INTC_IRQ(MTU2_GROUP2, 237),
63 INTC_IRQ(MTU2_GROUP2, 238), INTC_IRQ(MTU2_GROUP2, 239),
64
65 INTC_IRQ(MTU2_GROUP3, 240), INTC_IRQ(MTU2_GROUP3, 241),
66 INTC_IRQ(MTU2_GROUP3, 242), INTC_IRQ(MTU2_GROUP3, 243),
67
68 INTC_IRQ(MTU2_TGI3B, 244),
69 INTC_IRQ(MTU2_TGI3C, 245),
70
71 INTC_IRQ(MTU2_GROUP4, 246), INTC_IRQ(MTU2_GROUP4, 247),
72 INTC_IRQ(MTU2_GROUP4, 248), INTC_IRQ(MTU2_GROUP4, 249),
73 INTC_IRQ(MTU2_GROUP4, 250), INTC_IRQ(MTU2_GROUP4, 251),
74
75 INTC_IRQ(MTU2_GROUP5, 252), INTC_IRQ(MTU2_GROUP5, 253),
76 INTC_IRQ(MTU2_GROUP5, 254), INTC_IRQ(MTU2_GROUP5, 255),
77 };
78
79 static struct intc_group groups[] __initdata = {
80 INTC_GROUP(PINT, PINT0, PINT1, PINT2, PINT3,
81 PINT4, PINT5, PINT6, PINT7),
82 };
83
84 static struct intc_prio_reg prio_registers[] __initdata = {
85 { 0xfffd9418, 0, 16, 4, { IRQ0, IRQ1, IRQ2, IRQ3 } },
86 { 0xfffd941a, 0, 16, 4, { IRQ4, IRQ5, IRQ6, IRQ7 } },
87 { 0xfffd941c, 0, 16, 4, { IRQ8, IRQ9, IRQ10, IRQ11 } },
88 { 0xfffd941e, 0, 16, 4, { IRQ12, IRQ13, IRQ14, IRQ15 } },
89 { 0xfffd9420, 0, 16, 4, { PINT, 0, 0, 0 } },
90 { 0xfffd9800, 0, 16, 4, { } },
91 { 0xfffd9802, 0, 16, 4, { } },
92 { 0xfffd9804, 0, 16, 4, { } },
93 { 0xfffd9806, 0, 16, 4, { } },
94 { 0xfffd9808, 0, 16, 4, { } },
95 { 0xfffd980a, 0, 16, 4, { } },
96 { 0xfffd980c, 0, 16, 4, { } },
97 { 0xfffd980e, 0, 16, 4, { } },
98 { 0xfffd9810, 0, 16, 4, { 0, 0, 0, SCIF0 } },
99 { 0xfffd9812, 0, 16, 4,
100 { SCIF1, MTU2_GROUP1, MTU2_GROUP2, MTU2_GROUP3 } },
101 { 0xfffd9814, 0, 16, 4,
102 { MTU2_TGI3B, MTU2_TGI3C, MTU2_GROUP4, MTU2_GROUP5 } },
103 };
104
105 static struct intc_mask_reg mask_registers[] __initdata = {
106 { 0xfffd9408, 0, 16,
107 { 0, 0, 0, 0, 0, 0, 0, 0,
108 PINT7, PINT6, PINT5, PINT4, PINT3, PINT2, PINT1, PINT0 } },
109 };
110
111 static DECLARE_INTC_DESC(intc_desc, "mxg", vectors, groups,
112 mask_registers, prio_registers, NULL);
113
114 static struct resource mtu2_resources[] = {
115 DEFINE_RES_MEM(0xff801000, 0x400),
116 DEFINE_RES_IRQ_NAMED(228, "tgi0a"),
117 DEFINE_RES_IRQ_NAMED(234, "tgi1a"),
118 DEFINE_RES_IRQ_NAMED(240, "tgi2a"),
119 };
120
121 static struct platform_device mtu2_device = {
122 .name = "sh-mtu2",
123 .id = -1,
124 .resource = mtu2_resources,
125 .num_resources = ARRAY_SIZE(mtu2_resources),
126 };
127
128 static struct plat_sci_port scif0_platform_data = {
129 .scscr = SCSCR_REIE,
130 .type = PORT_SCIF,
131 };
132
133 static struct resource scif0_resources[] = {
134 DEFINE_RES_MEM(0xff804000, 0x100),
135 DEFINE_RES_IRQ(220),
136 };
137
138 static struct platform_device scif0_device = {
139 .name = "sh-sci",
140 .id = 0,
141 .resource = scif0_resources,
142 .num_resources = ARRAY_SIZE(scif0_resources),
143 .dev = {
144 .platform_data = &scif0_platform_data,
145 },
146 };
147
148 static struct platform_device *mxg_devices[] __initdata = {
149 &scif0_device,
150 &mtu2_device,
151 };
152
153 static int __init mxg_devices_setup(void)
154 {
155 return platform_add_devices(mxg_devices,
156 ARRAY_SIZE(mxg_devices));
157 }
158 arch_initcall(mxg_devices_setup);
159
160 void __init plat_irq_setup(void)
161 {
162 register_intc_controller(&intc_desc);
163 }
164
165 static struct platform_device *mxg_early_devices[] __initdata = {
166 &scif0_device,
167 &mtu2_device,
168 };
169
170 void __init plat_early_device_setup(void)
171 {
172 early_platform_add_devices(mxg_early_devices,
173 ARRAY_SIZE(mxg_early_devices));
174 }