This source file includes following definitions.
- sh7201_devices_setup
- plat_irq_setup
- plat_early_device_setup
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8 #include <linux/platform_device.h>
9 #include <linux/init.h>
10 #include <linux/serial.h>
11 #include <linux/serial_sci.h>
12 #include <linux/sh_timer.h>
13 #include <linux/io.h>
14
15 enum {
16 UNUSED = 0,
17
18
19 IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7,
20 PINT0, PINT1, PINT2, PINT3, PINT4, PINT5, PINT6, PINT7,
21
22 ADC_ADI,
23
24 MTU20_ABCD, MTU20_VEF, MTU21_AB, MTU21_VU, MTU22_AB, MTU22_VU,
25 MTU23_ABCD, MTU24_ABCD, MTU25_UVW, MTU2_TCI3V, MTU2_TCI4V,
26
27 RTC, WDT,
28
29 IIC30, IIC31, IIC32,
30
31 DMAC0_DMINT0, DMAC1_DMINT1,
32 DMAC2_DMINT2, DMAC3_DMINT3,
33
34 SCIF0, SCIF1, SCIF2, SCIF3, SCIF4, SCIF5, SCIF6, SCIF7,
35
36 DMAC0_DMINTA, DMAC4_DMINT4, DMAC5_DMINT5, DMAC6_DMINT6,
37 DMAC7_DMINT7,
38
39 RCAN0, RCAN1,
40
41 SSI0_SSII, SSI1_SSII,
42
43 TMR0, TMR1,
44
45
46 PINT,
47 };
48
49 static struct intc_vect vectors[] __initdata = {
50 INTC_IRQ(IRQ0, 64), INTC_IRQ(IRQ1, 65),
51 INTC_IRQ(IRQ2, 66), INTC_IRQ(IRQ3, 67),
52 INTC_IRQ(IRQ4, 68), INTC_IRQ(IRQ5, 69),
53 INTC_IRQ(IRQ6, 70), INTC_IRQ(IRQ7, 71),
54
55 INTC_IRQ(PINT0, 80), INTC_IRQ(PINT1, 81),
56 INTC_IRQ(PINT2, 82), INTC_IRQ(PINT3, 83),
57 INTC_IRQ(PINT4, 84), INTC_IRQ(PINT5, 85),
58 INTC_IRQ(PINT6, 86), INTC_IRQ(PINT7, 87),
59
60 INTC_IRQ(ADC_ADI, 92),
61
62 INTC_IRQ(MTU20_ABCD, 108), INTC_IRQ(MTU20_ABCD, 109),
63 INTC_IRQ(MTU20_ABCD, 110), INTC_IRQ(MTU20_ABCD, 111),
64
65 INTC_IRQ(MTU20_VEF, 112), INTC_IRQ(MTU20_VEF, 113),
66 INTC_IRQ(MTU20_VEF, 114),
67
68 INTC_IRQ(MTU21_AB, 116), INTC_IRQ(MTU21_AB, 117),
69 INTC_IRQ(MTU21_VU, 120), INTC_IRQ(MTU21_VU, 121),
70
71 INTC_IRQ(MTU22_AB, 124), INTC_IRQ(MTU22_AB, 125),
72 INTC_IRQ(MTU22_VU, 128), INTC_IRQ(MTU22_VU, 129),
73
74 INTC_IRQ(MTU23_ABCD, 132), INTC_IRQ(MTU23_ABCD, 133),
75 INTC_IRQ(MTU23_ABCD, 134), INTC_IRQ(MTU23_ABCD, 135),
76
77 INTC_IRQ(MTU2_TCI3V, 136),
78
79 INTC_IRQ(MTU24_ABCD, 140), INTC_IRQ(MTU24_ABCD, 141),
80 INTC_IRQ(MTU24_ABCD, 142), INTC_IRQ(MTU24_ABCD, 143),
81
82 INTC_IRQ(MTU2_TCI4V, 144),
83
84 INTC_IRQ(MTU25_UVW, 148), INTC_IRQ(MTU25_UVW, 149),
85 INTC_IRQ(MTU25_UVW, 150),
86
87 INTC_IRQ(RTC, 152), INTC_IRQ(RTC, 153),
88 INTC_IRQ(RTC, 154),
89
90 INTC_IRQ(WDT, 156),
91
92 INTC_IRQ(IIC30, 157), INTC_IRQ(IIC30, 158),
93 INTC_IRQ(IIC30, 159), INTC_IRQ(IIC30, 160),
94 INTC_IRQ(IIC30, 161),
95
96 INTC_IRQ(IIC31, 164), INTC_IRQ(IIC31, 165),
97 INTC_IRQ(IIC31, 166), INTC_IRQ(IIC31, 167),
98 INTC_IRQ(IIC31, 168),
99
100 INTC_IRQ(IIC32, 170), INTC_IRQ(IIC32, 171),
101 INTC_IRQ(IIC32, 172), INTC_IRQ(IIC32, 173),
102 INTC_IRQ(IIC32, 174),
103
104 INTC_IRQ(DMAC0_DMINT0, 176), INTC_IRQ(DMAC1_DMINT1, 177),
105 INTC_IRQ(DMAC2_DMINT2, 178), INTC_IRQ(DMAC3_DMINT3, 179),
106
107 INTC_IRQ(SCIF0, 180), INTC_IRQ(SCIF0, 181),
108 INTC_IRQ(SCIF0, 182), INTC_IRQ(SCIF0, 183),
109 INTC_IRQ(SCIF1, 184), INTC_IRQ(SCIF1, 185),
110 INTC_IRQ(SCIF1, 186), INTC_IRQ(SCIF1, 187),
111 INTC_IRQ(SCIF2, 188), INTC_IRQ(SCIF2, 189),
112 INTC_IRQ(SCIF2, 190), INTC_IRQ(SCIF2, 191),
113 INTC_IRQ(SCIF3, 192), INTC_IRQ(SCIF3, 193),
114 INTC_IRQ(SCIF3, 194), INTC_IRQ(SCIF3, 195),
115 INTC_IRQ(SCIF4, 196), INTC_IRQ(SCIF4, 197),
116 INTC_IRQ(SCIF4, 198), INTC_IRQ(SCIF4, 199),
117 INTC_IRQ(SCIF5, 200), INTC_IRQ(SCIF5, 201),
118 INTC_IRQ(SCIF5, 202), INTC_IRQ(SCIF5, 203),
119 INTC_IRQ(SCIF6, 204), INTC_IRQ(SCIF6, 205),
120 INTC_IRQ(SCIF6, 206), INTC_IRQ(SCIF6, 207),
121 INTC_IRQ(SCIF7, 208), INTC_IRQ(SCIF7, 209),
122 INTC_IRQ(SCIF7, 210), INTC_IRQ(SCIF7, 211),
123
124 INTC_IRQ(DMAC0_DMINTA, 212), INTC_IRQ(DMAC4_DMINT4, 216),
125 INTC_IRQ(DMAC5_DMINT5, 217), INTC_IRQ(DMAC6_DMINT6, 218),
126 INTC_IRQ(DMAC7_DMINT7, 219),
127
128 INTC_IRQ(RCAN0, 228), INTC_IRQ(RCAN0, 229),
129 INTC_IRQ(RCAN0, 230),
130 INTC_IRQ(RCAN0, 231), INTC_IRQ(RCAN0, 232),
131
132 INTC_IRQ(RCAN1, 234), INTC_IRQ(RCAN1, 235),
133 INTC_IRQ(RCAN1, 236),
134 INTC_IRQ(RCAN1, 237), INTC_IRQ(RCAN1, 238),
135
136 INTC_IRQ(SSI0_SSII, 244), INTC_IRQ(SSI1_SSII, 245),
137
138 INTC_IRQ(TMR0, 246), INTC_IRQ(TMR0, 247),
139 INTC_IRQ(TMR0, 248),
140
141 INTC_IRQ(TMR1, 252), INTC_IRQ(TMR1, 253),
142 INTC_IRQ(TMR1, 254),
143 };
144
145 static struct intc_group groups[] __initdata = {
146 INTC_GROUP(PINT, PINT0, PINT1, PINT2, PINT3,
147 PINT4, PINT5, PINT6, PINT7),
148 };
149
150 static struct intc_prio_reg prio_registers[] __initdata = {
151 { 0xfffe9418, 0, 16, 4, { IRQ0, IRQ1, IRQ2, IRQ3 } },
152 { 0xfffe941a, 0, 16, 4, { IRQ4, IRQ5, IRQ6, IRQ7 } },
153 { 0xfffe9420, 0, 16, 4, { PINT, 0, ADC_ADI, 0 } },
154 { 0xfffe9800, 0, 16, 4, { 0, MTU20_ABCD, MTU20_VEF, MTU21_AB } },
155 { 0xfffe9802, 0, 16, 4, { MTU21_VU, MTU22_AB, MTU22_VU, MTU23_ABCD } },
156 { 0xfffe9804, 0, 16, 4, { MTU2_TCI3V, MTU24_ABCD, MTU2_TCI4V, MTU25_UVW } },
157
158 { 0xfffe9806, 0, 16, 4, { RTC, WDT, IIC30, 0 } },
159 { 0xfffe9808, 0, 16, 4, { IIC31, IIC32, DMAC0_DMINT0, DMAC1_DMINT1 } },
160 { 0xfffe980a, 0, 16, 4, { DMAC2_DMINT2, DMAC3_DMINT3, SCIF0, SCIF1 } },
161 { 0xfffe980c, 0, 16, 4, { SCIF2, SCIF3, SCIF4, SCIF5 } },
162 { 0xfffe980e, 0, 16, 4, { SCIF6, SCIF7, DMAC0_DMINTA, DMAC4_DMINT4 } },
163 { 0xfffe9810, 0, 16, 4, { DMAC5_DMINT5, DMAC6_DMINT6, DMAC7_DMINT7, 0 } },
164 { 0xfffe9812, 0, 16, 4, { 0, RCAN0, RCAN1, 0 } },
165 { 0xfffe9814, 0, 16, 4, { SSI0_SSII, SSI1_SSII, TMR0, TMR1 } },
166 };
167
168 static struct intc_mask_reg mask_registers[] __initdata = {
169 { 0xfffe9408, 0, 16,
170 { 0, 0, 0, 0, 0, 0, 0, 0,
171 PINT7, PINT6, PINT5, PINT4, PINT3, PINT2, PINT1, PINT0 } },
172 };
173
174 static DECLARE_INTC_DESC(intc_desc, "sh7201", vectors, groups,
175 mask_registers, prio_registers, NULL);
176
177 static struct plat_sci_port scif0_platform_data = {
178 .scscr = SCSCR_REIE,
179 .type = PORT_SCIF,
180 };
181
182 static struct resource scif0_resources[] = {
183 DEFINE_RES_MEM(0xfffe8000, 0x100),
184 DEFINE_RES_IRQ(180),
185 };
186
187 static struct platform_device scif0_device = {
188 .name = "sh-sci",
189 .id = 0,
190 .resource = scif0_resources,
191 .num_resources = ARRAY_SIZE(scif0_resources),
192 .dev = {
193 .platform_data = &scif0_platform_data,
194 },
195 };
196
197 static struct plat_sci_port scif1_platform_data = {
198 .scscr = SCSCR_REIE,
199 .type = PORT_SCIF,
200 };
201
202 static struct resource scif1_resources[] = {
203 DEFINE_RES_MEM(0xfffe8800, 0x100),
204 DEFINE_RES_IRQ(184),
205 };
206
207 static struct platform_device scif1_device = {
208 .name = "sh-sci",
209 .id = 1,
210 .resource = scif1_resources,
211 .num_resources = ARRAY_SIZE(scif1_resources),
212 .dev = {
213 .platform_data = &scif1_platform_data,
214 },
215 };
216
217 static struct plat_sci_port scif2_platform_data = {
218 .scscr = SCSCR_REIE,
219 .type = PORT_SCIF,
220 };
221
222 static struct resource scif2_resources[] = {
223 DEFINE_RES_MEM(0xfffe9000, 0x100),
224 DEFINE_RES_IRQ(188),
225 };
226
227 static struct platform_device scif2_device = {
228 .name = "sh-sci",
229 .id = 2,
230 .resource = scif2_resources,
231 .num_resources = ARRAY_SIZE(scif2_resources),
232 .dev = {
233 .platform_data = &scif2_platform_data,
234 },
235 };
236
237 static struct plat_sci_port scif3_platform_data = {
238 .scscr = SCSCR_REIE,
239 .type = PORT_SCIF,
240 };
241
242 static struct resource scif3_resources[] = {
243 DEFINE_RES_MEM(0xfffe9800, 0x100),
244 DEFINE_RES_IRQ(192),
245 };
246
247 static struct platform_device scif3_device = {
248 .name = "sh-sci",
249 .id = 3,
250 .resource = scif3_resources,
251 .num_resources = ARRAY_SIZE(scif3_resources),
252 .dev = {
253 .platform_data = &scif3_platform_data,
254 },
255 };
256
257 static struct plat_sci_port scif4_platform_data = {
258 .scscr = SCSCR_REIE,
259 .type = PORT_SCIF,
260 };
261
262 static struct resource scif4_resources[] = {
263 DEFINE_RES_MEM(0xfffea000, 0x100),
264 DEFINE_RES_IRQ(196),
265 };
266
267 static struct platform_device scif4_device = {
268 .name = "sh-sci",
269 .id = 4,
270 .resource = scif4_resources,
271 .num_resources = ARRAY_SIZE(scif4_resources),
272 .dev = {
273 .platform_data = &scif4_platform_data,
274 },
275 };
276
277 static struct plat_sci_port scif5_platform_data = {
278 .scscr = SCSCR_REIE,
279 .type = PORT_SCIF,
280 };
281
282 static struct resource scif5_resources[] = {
283 DEFINE_RES_MEM(0xfffea800, 0x100),
284 DEFINE_RES_IRQ(200),
285 };
286
287 static struct platform_device scif5_device = {
288 .name = "sh-sci",
289 .id = 5,
290 .resource = scif5_resources,
291 .num_resources = ARRAY_SIZE(scif5_resources),
292 .dev = {
293 .platform_data = &scif5_platform_data,
294 },
295 };
296
297 static struct plat_sci_port scif6_platform_data = {
298 .scscr = SCSCR_REIE,
299 .type = PORT_SCIF,
300 };
301
302 static struct resource scif6_resources[] = {
303 DEFINE_RES_MEM(0xfffeb000, 0x100),
304 DEFINE_RES_IRQ(204),
305 };
306
307 static struct platform_device scif6_device = {
308 .name = "sh-sci",
309 .id = 6,
310 .resource = scif6_resources,
311 .num_resources = ARRAY_SIZE(scif6_resources),
312 .dev = {
313 .platform_data = &scif6_platform_data,
314 },
315 };
316
317 static struct plat_sci_port scif7_platform_data = {
318 .scscr = SCSCR_REIE,
319 .type = PORT_SCIF,
320 };
321
322 static struct resource scif7_resources[] = {
323 DEFINE_RES_MEM(0xfffeb800, 0x100),
324 DEFINE_RES_IRQ(208),
325 };
326
327 static struct platform_device scif7_device = {
328 .name = "sh-sci",
329 .id = 7,
330 .resource = scif7_resources,
331 .num_resources = ARRAY_SIZE(scif7_resources),
332 .dev = {
333 .platform_data = &scif7_platform_data,
334 },
335 };
336
337 static struct resource rtc_resources[] = {
338 [0] = {
339 .start = 0xffff0800,
340 .end = 0xffff2000 + 0x58 - 1,
341 .flags = IORESOURCE_IO,
342 },
343 [1] = {
344
345 .start = 152,
346 .flags = IORESOURCE_IRQ,
347 },
348 };
349
350 static struct platform_device rtc_device = {
351 .name = "sh-rtc",
352 .id = -1,
353 .num_resources = ARRAY_SIZE(rtc_resources),
354 .resource = rtc_resources,
355 };
356
357 static struct resource mtu2_resources[] = {
358 DEFINE_RES_MEM(0xfffe4000, 0x400),
359 DEFINE_RES_IRQ_NAMED(108, "tgi0a"),
360 DEFINE_RES_IRQ_NAMED(116, "tgi1a"),
361 DEFINE_RES_IRQ_NAMED(124, "tgi1b"),
362 };
363
364 static struct platform_device mtu2_device = {
365 .name = "sh-mtu2",
366 .id = -1,
367 .resource = mtu2_resources,
368 .num_resources = ARRAY_SIZE(mtu2_resources),
369 };
370
371 static struct platform_device *sh7201_devices[] __initdata = {
372 &scif0_device,
373 &scif1_device,
374 &scif2_device,
375 &scif3_device,
376 &scif4_device,
377 &scif5_device,
378 &scif6_device,
379 &scif7_device,
380 &rtc_device,
381 &mtu2_device,
382 };
383
384 static int __init sh7201_devices_setup(void)
385 {
386 return platform_add_devices(sh7201_devices,
387 ARRAY_SIZE(sh7201_devices));
388 }
389 arch_initcall(sh7201_devices_setup);
390
391 void __init plat_irq_setup(void)
392 {
393 register_intc_controller(&intc_desc);
394 }
395
396 static struct platform_device *sh7201_early_devices[] __initdata = {
397 &scif0_device,
398 &scif1_device,
399 &scif2_device,
400 &scif3_device,
401 &scif4_device,
402 &scif5_device,
403 &scif6_device,
404 &scif7_device,
405 &mtu2_device,
406 };
407
408 #define STBCR3 0xfffe0408
409
410 void __init plat_early_device_setup(void)
411 {
412
413 __raw_writeb(__raw_readb(STBCR3) & ~0x20, STBCR3);
414
415 early_platform_add_devices(sh7201_early_devices,
416 ARRAY_SIZE(sh7201_early_devices));
417 }