root/arch/sh/kernel/cpu/sh2a/probe.c

DEFINITIONS

1. cpu_probe

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * arch/sh/kernel/cpu/sh2a/probe.c
   4  *
   5  * CPU Subtype Probing for SH-2A.
   6  *
   7  * Copyright (C) 2004 - 2007  Paul Mundt
   8  */
   9 #include <linux/init.h>
  10 #include <asm/processor.h>
  11 #include <asm/cache.h>
  12 
  13 void cpu_probe(void)
  14 {
  15         boot_cpu_data.family                    = CPU_FAMILY_SH2A;
  16 
  17         /* All SH-2A CPUs have support for 16 and 32-bit opcodes.. */
  18         boot_cpu_data.flags                     |= CPU_HAS_OP32;
  19 
  20 #if defined(CONFIG_CPU_SUBTYPE_SH7201)
  21         boot_cpu_data.type                      = CPU_SH7201;
  22         boot_cpu_data.flags                     |= CPU_HAS_FPU;
  23 #elif defined(CONFIG_CPU_SUBTYPE_SH7203)
  24         boot_cpu_data.type                      = CPU_SH7203;
  25         boot_cpu_data.flags                     |= CPU_HAS_FPU;
  26 #elif defined(CONFIG_CPU_SUBTYPE_SH7263)
  27         boot_cpu_data.type                      = CPU_SH7263;
  28         boot_cpu_data.flags                     |= CPU_HAS_FPU;
  29 #elif defined(CONFIG_CPU_SUBTYPE_SH7264)
  30         boot_cpu_data.type                      = CPU_SH7264;
  31         boot_cpu_data.flags                     |= CPU_HAS_FPU;
  32 #elif defined(CONFIG_CPU_SUBTYPE_SH7269)
  33         boot_cpu_data.type                      = CPU_SH7269;
  34         boot_cpu_data.flags                     |= CPU_HAS_FPU;
  35 #elif defined(CONFIG_CPU_SUBTYPE_SH7206)
  36         boot_cpu_data.type                      = CPU_SH7206;
  37         boot_cpu_data.flags                     |= CPU_HAS_DSP;
  38 #elif defined(CONFIG_CPU_SUBTYPE_MXG)
  39         boot_cpu_data.type                      = CPU_MXG;
  40         boot_cpu_data.flags                     |= CPU_HAS_DSP;
  41 #endif
  42 
  43         boot_cpu_data.dcache.ways               = 4;
  44         boot_cpu_data.dcache.way_incr           = (1 << 11);
  45         boot_cpu_data.dcache.sets               = 128;
  46         boot_cpu_data.dcache.entry_shift        = 4;
  47         boot_cpu_data.dcache.linesz             = L1_CACHE_BYTES;
  48         boot_cpu_data.dcache.flags              = 0;
  49 
  50         /*
  51          * The icache is the same as the dcache as far as this setup is
  52          * concerned. The only real difference in hardware is that the icache
  53          * lacks the U bit that the dcache has, none of this has any bearing
  54          * on the cache info.
  55          */
  56         boot_cpu_data.icache            = boot_cpu_data.dcache;
  57 }