This source file includes following definitions.
- master_clk_init
- module_clk_recalc
- bus_clk_recalc
- cpu_clk_recalc
- arch_init_clk_ops
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16 #include <linux/init.h>
17 #include <linux/kernel.h>
18 #include <asm/clock.h>
19 #include <asm/freq.h>
20 #include <asm/io.h>
21
22 static int md_table[] = { 1, 2, 3, 4, 6, 8, 12 };
23
24 static void master_clk_init(struct clk *clk)
25 {
26 clk->rate *= md_table[__raw_readw(FRQCR) & 0x0007];
27 }
28
29 static struct sh_clk_ops sh7710_master_clk_ops = {
30 .init = master_clk_init,
31 };
32
33 static unsigned long module_clk_recalc(struct clk *clk)
34 {
35 int idx = (__raw_readw(FRQCR) & 0x0007);
36 return clk->parent->rate / md_table[idx];
37 }
38
39 static struct sh_clk_ops sh7710_module_clk_ops = {
40 .recalc = module_clk_recalc,
41 };
42
43 static unsigned long bus_clk_recalc(struct clk *clk)
44 {
45 int idx = (__raw_readw(FRQCR) & 0x0700) >> 8;
46 return clk->parent->rate / md_table[idx];
47 }
48
49 static struct sh_clk_ops sh7710_bus_clk_ops = {
50 .recalc = bus_clk_recalc,
51 };
52
53 static unsigned long cpu_clk_recalc(struct clk *clk)
54 {
55 int idx = (__raw_readw(FRQCR) & 0x0070) >> 4;
56 return clk->parent->rate / md_table[idx];
57 }
58
59 static struct sh_clk_ops sh7710_cpu_clk_ops = {
60 .recalc = cpu_clk_recalc,
61 };
62
63 static struct sh_clk_ops *sh7710_clk_ops[] = {
64 &sh7710_master_clk_ops,
65 &sh7710_module_clk_ops,
66 &sh7710_bus_clk_ops,
67 &sh7710_cpu_clk_ops,
68 };
69
70 void __init arch_init_clk_ops(struct sh_clk_ops **ops, int idx)
71 {
72 if (idx < ARRAY_SIZE(sh7710_clk_ops))
73 *ops = sh7710_clk_ops[idx];
74 }
75