1 /* SPDX-License-Identifier: GPL-2.0 */
2 /*
3 * Contains register definitions for the Freescale Embedded Performance
4 * Monitor.
5 */
6 #ifdef __KERNEL__
7 #ifndef __ASM_POWERPC_REG_FSL_EMB_H__
8 #define __ASM_POWERPC_REG_FSL_EMB_H__
9
10 #include <linux/stringify.h>
11
12 #ifndef __ASSEMBLY__
13 /* Performance Monitor Registers */
14 #define mfpmr(rn) ({unsigned int rval; \
15 asm volatile("mfpmr %0," __stringify(rn) \
16 : "=r" (rval)); rval;})
17 #define mtpmr(rn, v) asm volatile("mtpmr " __stringify(rn) ",%0" : : "r" (v))
18 #endif /* __ASSEMBLY__ */
19
20 /* Freescale Book E Performance Monitor APU Registers */
21 #define PMRN_PMC0 0x010 /* Performance Monitor Counter 0 */
22 #define PMRN_PMC1 0x011 /* Performance Monitor Counter 1 */
23 #define PMRN_PMC2 0x012 /* Performance Monitor Counter 2 */
24 #define PMRN_PMC3 0x013 /* Performance Monitor Counter 3 */
25 #define PMRN_PMC4 0x014 /* Performance Monitor Counter 4 */
26 #define PMRN_PMC5 0x015 /* Performance Monitor Counter 5 */
27 #define PMRN_PMLCA0 0x090 /* PM Local Control A0 */
28 #define PMRN_PMLCA1 0x091 /* PM Local Control A1 */
29 #define PMRN_PMLCA2 0x092 /* PM Local Control A2 */
30 #define PMRN_PMLCA3 0x093 /* PM Local Control A3 */
31 #define PMRN_PMLCA4 0x094 /* PM Local Control A4 */
32 #define PMRN_PMLCA5 0x095 /* PM Local Control A5 */
33
34 #define PMLCA_FC 0x80000000 /* Freeze Counter */
35 #define PMLCA_FCS 0x40000000 /* Freeze in Supervisor */
36 #define PMLCA_FCU 0x20000000 /* Freeze in User */
37 #define PMLCA_FCM1 0x10000000 /* Freeze when PMM==1 */
38 #define PMLCA_FCM0 0x08000000 /* Freeze when PMM==0 */
39 #define PMLCA_CE 0x04000000 /* Condition Enable */
40 #define PMLCA_FGCS1 0x00000002 /* Freeze in guest state */
41 #define PMLCA_FGCS0 0x00000001 /* Freeze in hypervisor state */
42
43 #define PMLCA_EVENT_MASK 0x01ff0000 /* Event field */
44 #define PMLCA_EVENT_SHIFT 16
45
46 #define PMRN_PMLCB0 0x110 /* PM Local Control B0 */
47 #define PMRN_PMLCB1 0x111 /* PM Local Control B1 */
48 #define PMRN_PMLCB2 0x112 /* PM Local Control B2 */
49 #define PMRN_PMLCB3 0x113 /* PM Local Control B3 */
50 #define PMRN_PMLCB4 0x114 /* PM Local Control B4 */
51 #define PMRN_PMLCB5 0x115 /* PM Local Control B5 */
52
53 #define PMLCB_THRESHMUL_MASK 0x0700 /* Threshold Multiple Field */
54 #define PMLCB_THRESHMUL_SHIFT 8
55
56 #define PMLCB_THRESHOLD_MASK 0x003f /* Threshold Field */
57 #define PMLCB_THRESHOLD_SHIFT 0
58
59 #define PMRN_PMGC0 0x190 /* PM Global Control 0 */
60
61 #define PMGC0_FAC 0x80000000 /* Freeze all Counters */
62 #define PMGC0_PMIE 0x40000000 /* Interrupt Enable */
63 #define PMGC0_FCECE 0x20000000 /* Freeze countes on
64 Enabled Condition or
65 Event */
66
67 #define PMRN_UPMC0 0x000 /* User Performance Monitor Counter 0 */
68 #define PMRN_UPMC1 0x001 /* User Performance Monitor Counter 1 */
69 #define PMRN_UPMC2 0x002 /* User Performance Monitor Counter 2 */
70 #define PMRN_UPMC3 0x003 /* User Performance Monitor Counter 3 */
71 #define PMRN_UPMC4 0x004 /* User Performance Monitor Counter 4 */
72 #define PMRN_UPMC5 0x005 /* User Performance Monitor Counter 5 */
73 #define PMRN_UPMLCA0 0x080 /* User PM Local Control A0 */
74 #define PMRN_UPMLCA1 0x081 /* User PM Local Control A1 */
75 #define PMRN_UPMLCA2 0x082 /* User PM Local Control A2 */
76 #define PMRN_UPMLCA3 0x083 /* User PM Local Control A3 */
77 #define PMRN_UPMLCA4 0x084 /* User PM Local Control A4 */
78 #define PMRN_UPMLCA5 0x085 /* User PM Local Control A5 */
79 #define PMRN_UPMLCB0 0x100 /* User PM Local Control B0 */
80 #define PMRN_UPMLCB1 0x101 /* User PM Local Control B1 */
81 #define PMRN_UPMLCB2 0x102 /* User PM Local Control B2 */
82 #define PMRN_UPMLCB3 0x103 /* User PM Local Control B3 */
83 #define PMRN_UPMLCB4 0x104 /* User PM Local Control B4 */
84 #define PMRN_UPMLCB5 0x105 /* User PM Local Control B5 */
85 #define PMRN_UPMGC0 0x180 /* User PM Global Control 0 */
86
87
88 #endif /* __ASM_POWERPC_REG_FSL_EMB_H__ */
89 #endif /* __KERNEL__ */