root/arch/powerpc/include/asm/spu.h

/* [<][>][^][v][top][bottom][index][help] */

INCLUDED FROM

   1 /* SPDX-License-Identifier: GPL-2.0-or-later */
   2 /*
   3  * SPU core / file system interface and HW structures
   4  *
   5  * (C) Copyright IBM Deutschland Entwicklung GmbH 2005
   6  *
   7  * Author: Arnd Bergmann <arndb@de.ibm.com>
   8  */
   9 
  10 #ifndef _SPU_H
  11 #define _SPU_H
  12 #ifdef __KERNEL__
  13 
  14 #include <linux/workqueue.h>
  15 #include <linux/device.h>
  16 #include <linux/mutex.h>
  17 #include <asm/reg.h>
  18 #include <asm/copro.h>
  19 
  20 #define LS_SIZE (256 * 1024)
  21 #define LS_ADDR_MASK (LS_SIZE - 1)
  22 
  23 #define MFC_PUT_CMD             0x20
  24 #define MFC_PUTS_CMD            0x28
  25 #define MFC_PUTR_CMD            0x30
  26 #define MFC_PUTF_CMD            0x22
  27 #define MFC_PUTB_CMD            0x21
  28 #define MFC_PUTFS_CMD           0x2A
  29 #define MFC_PUTBS_CMD           0x29
  30 #define MFC_PUTRF_CMD           0x32
  31 #define MFC_PUTRB_CMD           0x31
  32 #define MFC_PUTL_CMD            0x24
  33 #define MFC_PUTRL_CMD           0x34
  34 #define MFC_PUTLF_CMD           0x26
  35 #define MFC_PUTLB_CMD           0x25
  36 #define MFC_PUTRLF_CMD          0x36
  37 #define MFC_PUTRLB_CMD          0x35
  38 
  39 #define MFC_GET_CMD             0x40
  40 #define MFC_GETS_CMD            0x48
  41 #define MFC_GETF_CMD            0x42
  42 #define MFC_GETB_CMD            0x41
  43 #define MFC_GETFS_CMD           0x4A
  44 #define MFC_GETBS_CMD           0x49
  45 #define MFC_GETL_CMD            0x44
  46 #define MFC_GETLF_CMD           0x46
  47 #define MFC_GETLB_CMD           0x45
  48 
  49 #define MFC_SDCRT_CMD           0x80
  50 #define MFC_SDCRTST_CMD         0x81
  51 #define MFC_SDCRZ_CMD           0x89
  52 #define MFC_SDCRS_CMD           0x8D
  53 #define MFC_SDCRF_CMD           0x8F
  54 
  55 #define MFC_GETLLAR_CMD         0xD0
  56 #define MFC_PUTLLC_CMD          0xB4
  57 #define MFC_PUTLLUC_CMD         0xB0
  58 #define MFC_PUTQLLUC_CMD        0xB8
  59 #define MFC_SNDSIG_CMD          0xA0
  60 #define MFC_SNDSIGB_CMD         0xA1
  61 #define MFC_SNDSIGF_CMD         0xA2
  62 #define MFC_BARRIER_CMD         0xC0
  63 #define MFC_EIEIO_CMD           0xC8
  64 #define MFC_SYNC_CMD            0xCC
  65 
  66 #define MFC_MIN_DMA_SIZE_SHIFT  4       /* 16 bytes */
  67 #define MFC_MAX_DMA_SIZE_SHIFT  14      /* 16384 bytes */
  68 #define MFC_MIN_DMA_SIZE        (1 << MFC_MIN_DMA_SIZE_SHIFT)
  69 #define MFC_MAX_DMA_SIZE        (1 << MFC_MAX_DMA_SIZE_SHIFT)
  70 #define MFC_MIN_DMA_SIZE_MASK   (MFC_MIN_DMA_SIZE - 1)
  71 #define MFC_MAX_DMA_SIZE_MASK   (MFC_MAX_DMA_SIZE - 1)
  72 #define MFC_MIN_DMA_LIST_SIZE   0x0008  /*   8 bytes */
  73 #define MFC_MAX_DMA_LIST_SIZE   0x4000  /* 16K bytes */
  74 
  75 #define MFC_TAGID_TO_TAGMASK(tag_id)  (1 << (tag_id & 0x1F))
  76 
  77 /* Events for Channels 0-2 */
  78 #define MFC_DMA_TAG_STATUS_UPDATE_EVENT     0x00000001
  79 #define MFC_DMA_TAG_CMD_STALL_NOTIFY_EVENT  0x00000002
  80 #define MFC_DMA_QUEUE_AVAILABLE_EVENT       0x00000008
  81 #define MFC_SPU_MAILBOX_WRITTEN_EVENT       0x00000010
  82 #define MFC_DECREMENTER_EVENT               0x00000020
  83 #define MFC_PU_INT_MAILBOX_AVAILABLE_EVENT  0x00000040
  84 #define MFC_PU_MAILBOX_AVAILABLE_EVENT      0x00000080
  85 #define MFC_SIGNAL_2_EVENT                  0x00000100
  86 #define MFC_SIGNAL_1_EVENT                  0x00000200
  87 #define MFC_LLR_LOST_EVENT                  0x00000400
  88 #define MFC_PRIV_ATTN_EVENT                 0x00000800
  89 #define MFC_MULTI_SRC_EVENT                 0x00001000
  90 
  91 /* Flag indicating progress during context switch. */
  92 #define SPU_CONTEXT_SWITCH_PENDING      0UL
  93 #define SPU_CONTEXT_FAULT_PENDING       1UL
  94 
  95 struct spu_context;
  96 struct spu_runqueue;
  97 struct spu_lscsa;
  98 struct device_node;
  99 
 100 enum spu_utilization_state {
 101         SPU_UTIL_USER,
 102         SPU_UTIL_SYSTEM,
 103         SPU_UTIL_IOWAIT,
 104         SPU_UTIL_IDLE_LOADED,
 105         SPU_UTIL_MAX
 106 };
 107 
 108 struct spu {
 109         const char *name;
 110         unsigned long local_store_phys;
 111         u8 *local_store;
 112         unsigned long problem_phys;
 113         struct spu_problem __iomem *problem;
 114         struct spu_priv2 __iomem *priv2;
 115         struct list_head cbe_list;
 116         struct list_head full_list;
 117         enum { SPU_FREE, SPU_USED } alloc_state;
 118         int number;
 119         unsigned int irqs[3];
 120         u32 node;
 121         unsigned long flags;
 122         u64 class_0_pending;
 123         u64 class_0_dar;
 124         u64 class_1_dar;
 125         u64 class_1_dsisr;
 126         size_t ls_size;
 127         unsigned int slb_replace;
 128         struct mm_struct *mm;
 129         struct spu_context *ctx;
 130         struct spu_runqueue *rq;
 131         unsigned long long timestamp;
 132         pid_t pid;
 133         pid_t tgid;
 134         spinlock_t register_lock;
 135 
 136         void (* wbox_callback)(struct spu *spu);
 137         void (* ibox_callback)(struct spu *spu);
 138         void (* stop_callback)(struct spu *spu, int irq);
 139         void (* mfc_callback)(struct spu *spu);
 140 
 141         char irq_c0[8];
 142         char irq_c1[8];
 143         char irq_c2[8];
 144 
 145         u64 spe_id;
 146 
 147         void* pdata; /* platform private data */
 148 
 149         /* of based platforms only */
 150         struct device_node *devnode;
 151 
 152         /* native only */
 153         struct spu_priv1 __iomem *priv1;
 154 
 155         /* beat only */
 156         u64 shadow_int_mask_RW[3];
 157 
 158         struct device dev;
 159 
 160         int has_mem_affinity;
 161         struct list_head aff_list;
 162 
 163         struct {
 164                 /* protected by interrupt reentrancy */
 165                 enum spu_utilization_state util_state;
 166                 unsigned long long tstamp;
 167                 unsigned long long times[SPU_UTIL_MAX];
 168                 unsigned long long vol_ctx_switch;
 169                 unsigned long long invol_ctx_switch;
 170                 unsigned long long min_flt;
 171                 unsigned long long maj_flt;
 172                 unsigned long long hash_flt;
 173                 unsigned long long slb_flt;
 174                 unsigned long long class2_intr;
 175                 unsigned long long libassist;
 176         } stats;
 177 };
 178 
 179 struct cbe_spu_info {
 180         struct mutex list_mutex;
 181         struct list_head spus;
 182         int n_spus;
 183         int nr_active;
 184         atomic_t busy_spus;
 185         atomic_t reserved_spus;
 186 };
 187 
 188 extern struct cbe_spu_info cbe_spu_info[];
 189 
 190 void spu_init_channels(struct spu *spu);
 191 void spu_irq_setaffinity(struct spu *spu, int cpu);
 192 
 193 void spu_setup_kernel_slbs(struct spu *spu, struct spu_lscsa *lscsa,
 194                 void *code, int code_size);
 195 
 196 extern void spu_invalidate_slbs(struct spu *spu);
 197 extern void spu_associate_mm(struct spu *spu, struct mm_struct *mm);
 198 int spu_64k_pages_available(void);
 199 
 200 /* Calls from the memory management to the SPU */
 201 struct mm_struct;
 202 extern void spu_flush_all_slbs(struct mm_struct *mm);
 203 
 204 /* This interface allows a profiler (e.g., OProfile) to store a ref
 205  * to spu context information that it creates.  This caching technique
 206  * avoids the need to recreate this information after a save/restore operation.
 207  *
 208  * Assumes the caller has already incremented the ref count to
 209  * profile_info; then spu_context_destroy must call kref_put
 210  * on prof_info_kref.
 211  */
 212 void spu_set_profile_private_kref(struct spu_context *ctx,
 213                                   struct kref *prof_info_kref,
 214                                   void ( * prof_info_release) (struct kref *kref));
 215 
 216 void *spu_get_profile_private_kref(struct spu_context *ctx);
 217 
 218 /* system callbacks from the SPU */
 219 struct spu_syscall_block {
 220         u64 nr_ret;
 221         u64 parm[6];
 222 };
 223 extern long spu_sys_callback(struct spu_syscall_block *s);
 224 
 225 /* syscalls implemented in spufs */
 226 struct file;
 227 struct coredump_params;
 228 struct spufs_calls {
 229         long (*create_thread)(const char __user *name,
 230                                         unsigned int flags, umode_t mode,
 231                                         struct file *neighbor);
 232         long (*spu_run)(struct file *filp, __u32 __user *unpc,
 233                                                 __u32 __user *ustatus);
 234         int (*coredump_extra_notes_size)(void);
 235         int (*coredump_extra_notes_write)(struct coredump_params *cprm);
 236         void (*notify_spus_active)(void);
 237         struct module *owner;
 238 };
 239 
 240 /* return status from spu_run, same as in libspe */
 241 #define SPE_EVENT_DMA_ALIGNMENT         0x0008  /*A DMA alignment error */
 242 #define SPE_EVENT_SPE_ERROR             0x0010  /*An illegal instruction error*/
 243 #define SPE_EVENT_SPE_DATA_SEGMENT      0x0020  /*A DMA segmentation error    */
 244 #define SPE_EVENT_SPE_DATA_STORAGE      0x0040  /*A DMA storage error */
 245 #define SPE_EVENT_INVALID_DMA           0x0800  /* Invalid MFC DMA */
 246 
 247 /*
 248  * Flags for sys_spu_create.
 249  */
 250 #define SPU_CREATE_EVENTS_ENABLED       0x0001
 251 #define SPU_CREATE_GANG                 0x0002
 252 #define SPU_CREATE_NOSCHED              0x0004
 253 #define SPU_CREATE_ISOLATE              0x0008
 254 #define SPU_CREATE_AFFINITY_SPU         0x0010
 255 #define SPU_CREATE_AFFINITY_MEM         0x0020
 256 
 257 #define SPU_CREATE_FLAG_ALL             0x003f /* mask of all valid flags */
 258 
 259 
 260 int register_spu_syscalls(struct spufs_calls *calls);
 261 void unregister_spu_syscalls(struct spufs_calls *calls);
 262 
 263 int spu_add_dev_attr(struct device_attribute *attr);
 264 void spu_remove_dev_attr(struct device_attribute *attr);
 265 
 266 int spu_add_dev_attr_group(struct attribute_group *attrs);
 267 void spu_remove_dev_attr_group(struct attribute_group *attrs);
 268 
 269 /*
 270  * Notifier blocks:
 271  *
 272  * oprofile can get notified when a context switch is performed
 273  * on an spe. The notifer function that gets called is passed
 274  * a pointer to the SPU structure as well as the object-id that
 275  * identifies the binary running on that SPU now.
 276  *
 277  * For a context save, the object-id that is passed is zero,
 278  * identifying that the kernel will run from that moment on.
 279  *
 280  * For a context restore, the object-id is the value written
 281  * to object-id spufs file from user space and the notifer
 282  * function can assume that spu->ctx is valid.
 283  */
 284 struct notifier_block;
 285 int spu_switch_event_register(struct notifier_block * n);
 286 int spu_switch_event_unregister(struct notifier_block * n);
 287 
 288 extern void notify_spus_active(void);
 289 extern void do_notify_spus_active(void);
 290 
 291 /*
 292  * This defines the Local Store, Problem Area and Privilege Area of an SPU.
 293  */
 294 
 295 union mfc_tag_size_class_cmd {
 296         struct {
 297                 u16 mfc_size;
 298                 u16 mfc_tag;
 299                 u8  pad;
 300                 u8  mfc_rclassid;
 301                 u16 mfc_cmd;
 302         } u;
 303         struct {
 304                 u32 mfc_size_tag32;
 305                 u32 mfc_class_cmd32;
 306         } by32;
 307         u64 all64;
 308 };
 309 
 310 struct mfc_cq_sr {
 311         u64 mfc_cq_data0_RW;
 312         u64 mfc_cq_data1_RW;
 313         u64 mfc_cq_data2_RW;
 314         u64 mfc_cq_data3_RW;
 315 };
 316 
 317 struct spu_problem {
 318 #define MS_SYNC_PENDING         1L
 319         u64 spc_mssync_RW;                                      /* 0x0000 */
 320         u8  pad_0x0008_0x3000[0x3000 - 0x0008];
 321 
 322         /* DMA Area */
 323         u8  pad_0x3000_0x3004[0x4];                             /* 0x3000 */
 324         u32 mfc_lsa_W;                                          /* 0x3004 */
 325         u64 mfc_ea_W;                                           /* 0x3008 */
 326         union mfc_tag_size_class_cmd mfc_union_W;                       /* 0x3010 */
 327         u8  pad_0x3018_0x3104[0xec];                            /* 0x3018 */
 328         u32 dma_qstatus_R;                                      /* 0x3104 */
 329         u8  pad_0x3108_0x3204[0xfc];                            /* 0x3108 */
 330         u32 dma_querytype_RW;                                   /* 0x3204 */
 331         u8  pad_0x3208_0x321c[0x14];                            /* 0x3208 */
 332         u32 dma_querymask_RW;                                   /* 0x321c */
 333         u8  pad_0x3220_0x322c[0xc];                             /* 0x3220 */
 334         u32 dma_tagstatus_R;                                    /* 0x322c */
 335 #define DMA_TAGSTATUS_INTR_ANY  1u
 336 #define DMA_TAGSTATUS_INTR_ALL  2u
 337         u8  pad_0x3230_0x4000[0x4000 - 0x3230];                 /* 0x3230 */
 338 
 339         /* SPU Control Area */
 340         u8  pad_0x4000_0x4004[0x4];                             /* 0x4000 */
 341         u32 pu_mb_R;                                            /* 0x4004 */
 342         u8  pad_0x4008_0x400c[0x4];                             /* 0x4008 */
 343         u32 spu_mb_W;                                           /* 0x400c */
 344         u8  pad_0x4010_0x4014[0x4];                             /* 0x4010 */
 345         u32 mb_stat_R;                                          /* 0x4014 */
 346         u8  pad_0x4018_0x401c[0x4];                             /* 0x4018 */
 347         u32 spu_runcntl_RW;                                     /* 0x401c */
 348 #define SPU_RUNCNTL_STOP        0L
 349 #define SPU_RUNCNTL_RUNNABLE    1L
 350 #define SPU_RUNCNTL_ISOLATE     2L
 351         u8  pad_0x4020_0x4024[0x4];                             /* 0x4020 */
 352         u32 spu_status_R;                                       /* 0x4024 */
 353 #define SPU_STOP_STATUS_SHIFT           16
 354 #define SPU_STATUS_STOPPED              0x0
 355 #define SPU_STATUS_RUNNING              0x1
 356 #define SPU_STATUS_STOPPED_BY_STOP      0x2
 357 #define SPU_STATUS_STOPPED_BY_HALT      0x4
 358 #define SPU_STATUS_WAITING_FOR_CHANNEL  0x8
 359 #define SPU_STATUS_SINGLE_STEP          0x10
 360 #define SPU_STATUS_INVALID_INSTR        0x20
 361 #define SPU_STATUS_INVALID_CH           0x40
 362 #define SPU_STATUS_ISOLATED_STATE       0x80
 363 #define SPU_STATUS_ISOLATED_LOAD_STATUS 0x200
 364 #define SPU_STATUS_ISOLATED_EXIT_STATUS 0x400
 365         u8  pad_0x4028_0x402c[0x4];                             /* 0x4028 */
 366         u32 spu_spe_R;                                          /* 0x402c */
 367         u8  pad_0x4030_0x4034[0x4];                             /* 0x4030 */
 368         u32 spu_npc_RW;                                         /* 0x4034 */
 369         u8  pad_0x4038_0x14000[0x14000 - 0x4038];               /* 0x4038 */
 370 
 371         /* Signal Notification Area */
 372         u8  pad_0x14000_0x1400c[0xc];                           /* 0x14000 */
 373         u32 signal_notify1;                                     /* 0x1400c */
 374         u8  pad_0x14010_0x1c00c[0x7ffc];                        /* 0x14010 */
 375         u32 signal_notify2;                                     /* 0x1c00c */
 376 } __attribute__ ((aligned(0x20000)));
 377 
 378 /* SPU Privilege 2 State Area */
 379 struct spu_priv2 {
 380         /* MFC Registers */
 381         u8  pad_0x0000_0x1100[0x1100 - 0x0000];                 /* 0x0000 */
 382 
 383         /* SLB Management Registers */
 384         u8  pad_0x1100_0x1108[0x8];                             /* 0x1100 */
 385         u64 slb_index_W;                                        /* 0x1108 */
 386 #define SLB_INDEX_MASK                          0x7L
 387         u64 slb_esid_RW;                                        /* 0x1110 */
 388         u64 slb_vsid_RW;                                        /* 0x1118 */
 389 #define SLB_VSID_SUPERVISOR_STATE       (0x1ull << 11)
 390 #define SLB_VSID_SUPERVISOR_STATE_MASK  (0x1ull << 11)
 391 #define SLB_VSID_PROBLEM_STATE          (0x1ull << 10)
 392 #define SLB_VSID_PROBLEM_STATE_MASK     (0x1ull << 10)
 393 #define SLB_VSID_EXECUTE_SEGMENT        (0x1ull << 9)
 394 #define SLB_VSID_NO_EXECUTE_SEGMENT     (0x1ull << 9)
 395 #define SLB_VSID_EXECUTE_SEGMENT_MASK   (0x1ull << 9)
 396 #define SLB_VSID_4K_PAGE                (0x0 << 8)
 397 #define SLB_VSID_LARGE_PAGE             (0x1ull << 8)
 398 #define SLB_VSID_PAGE_SIZE_MASK         (0x1ull << 8)
 399 #define SLB_VSID_CLASS_MASK             (0x1ull << 7)
 400 #define SLB_VSID_VIRTUAL_PAGE_SIZE_MASK (0x1ull << 6)
 401         u64 slb_invalidate_entry_W;                             /* 0x1120 */
 402         u64 slb_invalidate_all_W;                               /* 0x1128 */
 403         u8  pad_0x1130_0x2000[0x2000 - 0x1130];                 /* 0x1130 */
 404 
 405         /* Context Save / Restore Area */
 406         struct mfc_cq_sr spuq[16];                              /* 0x2000 */
 407         struct mfc_cq_sr puq[8];                                /* 0x2200 */
 408         u8  pad_0x2300_0x3000[0x3000 - 0x2300];                 /* 0x2300 */
 409 
 410         /* MFC Control */
 411         u64 mfc_control_RW;                                     /* 0x3000 */
 412 #define MFC_CNTL_RESUME_DMA_QUEUE               (0ull << 0)
 413 #define MFC_CNTL_SUSPEND_DMA_QUEUE              (1ull << 0)
 414 #define MFC_CNTL_SUSPEND_DMA_QUEUE_MASK         (1ull << 0)
 415 #define MFC_CNTL_SUSPEND_MASK                   (1ull << 4)
 416 #define MFC_CNTL_NORMAL_DMA_QUEUE_OPERATION     (0ull << 8)
 417 #define MFC_CNTL_SUSPEND_IN_PROGRESS            (1ull << 8)
 418 #define MFC_CNTL_SUSPEND_COMPLETE               (3ull << 8)
 419 #define MFC_CNTL_SUSPEND_DMA_STATUS_MASK        (3ull << 8)
 420 #define MFC_CNTL_DMA_QUEUES_EMPTY               (1ull << 14)
 421 #define MFC_CNTL_DMA_QUEUES_EMPTY_MASK          (1ull << 14)
 422 #define MFC_CNTL_PURGE_DMA_REQUEST              (1ull << 15)
 423 #define MFC_CNTL_PURGE_DMA_IN_PROGRESS          (1ull << 24)
 424 #define MFC_CNTL_PURGE_DMA_COMPLETE             (3ull << 24)
 425 #define MFC_CNTL_PURGE_DMA_STATUS_MASK          (3ull << 24)
 426 #define MFC_CNTL_RESTART_DMA_COMMAND            (1ull << 32)
 427 #define MFC_CNTL_DMA_COMMAND_REISSUE_PENDING    (1ull << 32)
 428 #define MFC_CNTL_DMA_COMMAND_REISSUE_STATUS_MASK (1ull << 32)
 429 #define MFC_CNTL_MFC_PRIVILEGE_STATE            (2ull << 33)
 430 #define MFC_CNTL_MFC_PROBLEM_STATE              (3ull << 33)
 431 #define MFC_CNTL_MFC_KEY_PROTECTION_STATE_MASK  (3ull << 33)
 432 #define MFC_CNTL_DECREMENTER_HALTED             (1ull << 35)
 433 #define MFC_CNTL_DECREMENTER_RUNNING            (1ull << 40)
 434 #define MFC_CNTL_DECREMENTER_STATUS_MASK        (1ull << 40)
 435         u8  pad_0x3008_0x4000[0x4000 - 0x3008];                 /* 0x3008 */
 436 
 437         /* Interrupt Mailbox */
 438         u64 puint_mb_R;                                         /* 0x4000 */
 439         u8  pad_0x4008_0x4040[0x4040 - 0x4008];                 /* 0x4008 */
 440 
 441         /* SPU Control */
 442         u64 spu_privcntl_RW;                                    /* 0x4040 */
 443 #define SPU_PRIVCNTL_MODE_NORMAL                (0x0ull << 0)
 444 #define SPU_PRIVCNTL_MODE_SINGLE_STEP           (0x1ull << 0)
 445 #define SPU_PRIVCNTL_MODE_MASK                  (0x1ull << 0)
 446 #define SPU_PRIVCNTL_NO_ATTENTION_EVENT         (0x0ull << 1)
 447 #define SPU_PRIVCNTL_ATTENTION_EVENT            (0x1ull << 1)
 448 #define SPU_PRIVCNTL_ATTENTION_EVENT_MASK       (0x1ull << 1)
 449 #define SPU_PRIVCNT_LOAD_REQUEST_NORMAL         (0x0ull << 2)
 450 #define SPU_PRIVCNT_LOAD_REQUEST_ENABLE_MASK    (0x1ull << 2)
 451         u8  pad_0x4048_0x4058[0x10];                            /* 0x4048 */
 452         u64 spu_lslr_RW;                                        /* 0x4058 */
 453         u64 spu_chnlcntptr_RW;                                  /* 0x4060 */
 454         u64 spu_chnlcnt_RW;                                     /* 0x4068 */
 455         u64 spu_chnldata_RW;                                    /* 0x4070 */
 456         u64 spu_cfg_RW;                                         /* 0x4078 */
 457         u8  pad_0x4080_0x5000[0x5000 - 0x4080];                 /* 0x4080 */
 458 
 459         /* PV2_ImplRegs: Implementation-specific privileged-state 2 regs */
 460         u64 spu_pm_trace_tag_status_RW;                         /* 0x5000 */
 461         u64 spu_tag_status_query_RW;                            /* 0x5008 */
 462 #define TAG_STATUS_QUERY_CONDITION_BITS (0x3ull << 32)
 463 #define TAG_STATUS_QUERY_MASK_BITS (0xffffffffull)
 464         u64 spu_cmd_buf1_RW;                                    /* 0x5010 */
 465 #define SPU_COMMAND_BUFFER_1_LSA_BITS (0x7ffffull << 32)
 466 #define SPU_COMMAND_BUFFER_1_EAH_BITS (0xffffffffull)
 467         u64 spu_cmd_buf2_RW;                                    /* 0x5018 */
 468 #define SPU_COMMAND_BUFFER_2_EAL_BITS ((0xffffffffull) << 32)
 469 #define SPU_COMMAND_BUFFER_2_TS_BITS (0xffffull << 16)
 470 #define SPU_COMMAND_BUFFER_2_TAG_BITS (0x3full)
 471         u64 spu_atomic_status_RW;                               /* 0x5020 */
 472 } __attribute__ ((aligned(0x20000)));
 473 
 474 /* SPU Privilege 1 State Area */
 475 struct spu_priv1 {
 476         /* Control and Configuration Area */
 477         u64 mfc_sr1_RW;                                         /* 0x000 */
 478 #define MFC_STATE1_LOCAL_STORAGE_DECODE_MASK    0x01ull
 479 #define MFC_STATE1_BUS_TLBIE_MASK               0x02ull
 480 #define MFC_STATE1_REAL_MODE_OFFSET_ENABLE_MASK 0x04ull
 481 #define MFC_STATE1_PROBLEM_STATE_MASK           0x08ull
 482 #define MFC_STATE1_RELOCATE_MASK                0x10ull
 483 #define MFC_STATE1_MASTER_RUN_CONTROL_MASK      0x20ull
 484 #define MFC_STATE1_TABLE_SEARCH_MASK            0x40ull
 485         u64 mfc_lpid_RW;                                        /* 0x008 */
 486         u64 spu_idr_RW;                                         /* 0x010 */
 487         u64 mfc_vr_RO;                                          /* 0x018 */
 488 #define MFC_VERSION_BITS                (0xffff << 16)
 489 #define MFC_REVISION_BITS               (0xffff)
 490 #define MFC_GET_VERSION_BITS(vr)        (((vr) & MFC_VERSION_BITS) >> 16)
 491 #define MFC_GET_REVISION_BITS(vr)       ((vr) & MFC_REVISION_BITS)
 492         u64 spu_vr_RO;                                          /* 0x020 */
 493 #define SPU_VERSION_BITS                (0xffff << 16)
 494 #define SPU_REVISION_BITS               (0xffff)
 495 #define SPU_GET_VERSION_BITS(vr)        (vr & SPU_VERSION_BITS) >> 16
 496 #define SPU_GET_REVISION_BITS(vr)       (vr & SPU_REVISION_BITS)
 497         u8  pad_0x28_0x100[0x100 - 0x28];                       /* 0x28 */
 498 
 499         /* Interrupt Area */
 500         u64 int_mask_RW[3];                                     /* 0x100 */
 501 #define CLASS0_ENABLE_DMA_ALIGNMENT_INTR                0x1L
 502 #define CLASS0_ENABLE_INVALID_DMA_COMMAND_INTR          0x2L
 503 #define CLASS0_ENABLE_SPU_ERROR_INTR                    0x4L
 504 #define CLASS0_ENABLE_MFC_FIR_INTR                      0x8L
 505 #define CLASS1_ENABLE_SEGMENT_FAULT_INTR                0x1L
 506 #define CLASS1_ENABLE_STORAGE_FAULT_INTR                0x2L
 507 #define CLASS1_ENABLE_LS_COMPARE_SUSPEND_ON_GET_INTR    0x4L
 508 #define CLASS1_ENABLE_LS_COMPARE_SUSPEND_ON_PUT_INTR    0x8L
 509 #define CLASS2_ENABLE_MAILBOX_INTR                      0x1L
 510 #define CLASS2_ENABLE_SPU_STOP_INTR                     0x2L
 511 #define CLASS2_ENABLE_SPU_HALT_INTR                     0x4L
 512 #define CLASS2_ENABLE_SPU_DMA_TAG_GROUP_COMPLETE_INTR   0x8L
 513 #define CLASS2_ENABLE_MAILBOX_THRESHOLD_INTR            0x10L
 514         u8  pad_0x118_0x140[0x28];                              /* 0x118 */
 515         u64 int_stat_RW[3];                                     /* 0x140 */
 516 #define CLASS0_DMA_ALIGNMENT_INTR                       0x1L
 517 #define CLASS0_INVALID_DMA_COMMAND_INTR                 0x2L
 518 #define CLASS0_SPU_ERROR_INTR                           0x4L
 519 #define CLASS0_INTR_MASK                                0x7L
 520 #define CLASS1_SEGMENT_FAULT_INTR                       0x1L
 521 #define CLASS1_STORAGE_FAULT_INTR                       0x2L
 522 #define CLASS1_LS_COMPARE_SUSPEND_ON_GET_INTR           0x4L
 523 #define CLASS1_LS_COMPARE_SUSPEND_ON_PUT_INTR           0x8L
 524 #define CLASS1_INTR_MASK                                0xfL
 525 #define CLASS2_MAILBOX_INTR                             0x1L
 526 #define CLASS2_SPU_STOP_INTR                            0x2L
 527 #define CLASS2_SPU_HALT_INTR                            0x4L
 528 #define CLASS2_SPU_DMA_TAG_GROUP_COMPLETE_INTR          0x8L
 529 #define CLASS2_MAILBOX_THRESHOLD_INTR                   0x10L
 530 #define CLASS2_INTR_MASK                                0x1fL
 531         u8  pad_0x158_0x180[0x28];                              /* 0x158 */
 532         u64 int_route_RW;                                       /* 0x180 */
 533 
 534         /* Interrupt Routing */
 535         u8  pad_0x188_0x200[0x200 - 0x188];                     /* 0x188 */
 536 
 537         /* Atomic Unit Control Area */
 538         u64 mfc_atomic_flush_RW;                                /* 0x200 */
 539 #define mfc_atomic_flush_enable                 0x1L
 540         u8  pad_0x208_0x280[0x78];                              /* 0x208 */
 541         u64 resource_allocation_groupID_RW;                     /* 0x280 */
 542         u64 resource_allocation_enable_RW;                      /* 0x288 */
 543         u8  pad_0x290_0x3c8[0x3c8 - 0x290];                     /* 0x290 */
 544 
 545         /* SPU_Cache_ImplRegs: Implementation-dependent cache registers */
 546 
 547         u64 smf_sbi_signal_sel;                                 /* 0x3c8 */
 548 #define smf_sbi_mask_lsb        56
 549 #define smf_sbi_shift           (63 - smf_sbi_mask_lsb)
 550 #define smf_sbi_mask            (0x301LL << smf_sbi_shift)
 551 #define smf_sbi_bus0_bits       (0x001LL << smf_sbi_shift)
 552 #define smf_sbi_bus2_bits       (0x100LL << smf_sbi_shift)
 553 #define smf_sbi2_bus0_bits      (0x201LL << smf_sbi_shift)
 554 #define smf_sbi2_bus2_bits      (0x300LL << smf_sbi_shift)
 555         u64 smf_ato_signal_sel;                                 /* 0x3d0 */
 556 #define smf_ato_mask_lsb        35
 557 #define smf_ato_shift           (63 - smf_ato_mask_lsb)
 558 #define smf_ato_mask            (0x3LL << smf_ato_shift)
 559 #define smf_ato_bus0_bits       (0x2LL << smf_ato_shift)
 560 #define smf_ato_bus2_bits       (0x1LL << smf_ato_shift)
 561         u8  pad_0x3d8_0x400[0x400 - 0x3d8];                     /* 0x3d8 */
 562 
 563         /* TLB Management Registers */
 564         u64 mfc_sdr_RW;                                         /* 0x400 */
 565         u8  pad_0x408_0x500[0xf8];                              /* 0x408 */
 566         u64 tlb_index_hint_RO;                                  /* 0x500 */
 567         u64 tlb_index_W;                                        /* 0x508 */
 568         u64 tlb_vpn_RW;                                         /* 0x510 */
 569         u64 tlb_rpn_RW;                                         /* 0x518 */
 570         u8  pad_0x520_0x540[0x20];                              /* 0x520 */
 571         u64 tlb_invalidate_entry_W;                             /* 0x540 */
 572         u64 tlb_invalidate_all_W;                               /* 0x548 */
 573         u8  pad_0x550_0x580[0x580 - 0x550];                     /* 0x550 */
 574 
 575         /* SPU_MMU_ImplRegs: Implementation-dependent MMU registers */
 576         u64 smm_hid;                                            /* 0x580 */
 577 #define PAGE_SIZE_MASK          0xf000000000000000ull
 578 #define PAGE_SIZE_16MB_64KB     0x2000000000000000ull
 579         u8  pad_0x588_0x600[0x600 - 0x588];                     /* 0x588 */
 580 
 581         /* MFC Status/Control Area */
 582         u64 mfc_accr_RW;                                        /* 0x600 */
 583 #define MFC_ACCR_EA_ACCESS_GET          (1 << 0)
 584 #define MFC_ACCR_EA_ACCESS_PUT          (1 << 1)
 585 #define MFC_ACCR_LS_ACCESS_GET          (1 << 3)
 586 #define MFC_ACCR_LS_ACCESS_PUT          (1 << 4)
 587         u8  pad_0x608_0x610[0x8];                               /* 0x608 */
 588         u64 mfc_dsisr_RW;                                       /* 0x610 */
 589 #define MFC_DSISR_PTE_NOT_FOUND         (1 << 30)
 590 #define MFC_DSISR_ACCESS_DENIED         (1 << 27)
 591 #define MFC_DSISR_ATOMIC                (1 << 26)
 592 #define MFC_DSISR_ACCESS_PUT            (1 << 25)
 593 #define MFC_DSISR_ADDR_MATCH            (1 << 22)
 594 #define MFC_DSISR_LS                    (1 << 17)
 595 #define MFC_DSISR_L                     (1 << 16)
 596 #define MFC_DSISR_ADDRESS_OVERFLOW      (1 << 0)
 597         u8  pad_0x618_0x620[0x8];                               /* 0x618 */
 598         u64 mfc_dar_RW;                                         /* 0x620 */
 599         u8  pad_0x628_0x700[0x700 - 0x628];                     /* 0x628 */
 600 
 601         /* Replacement Management Table (RMT) Area */
 602         u64 rmt_index_RW;                                       /* 0x700 */
 603         u8  pad_0x708_0x710[0x8];                               /* 0x708 */
 604         u64 rmt_data1_RW;                                       /* 0x710 */
 605         u8  pad_0x718_0x800[0x800 - 0x718];                     /* 0x718 */
 606 
 607         /* Control/Configuration Registers */
 608         u64 mfc_dsir_R;                                         /* 0x800 */
 609 #define MFC_DSIR_Q                      (1 << 31)
 610 #define MFC_DSIR_SPU_QUEUE              MFC_DSIR_Q
 611         u64 mfc_lsacr_RW;                                       /* 0x808 */
 612 #define MFC_LSACR_COMPARE_MASK          ((~0ull) << 32)
 613 #define MFC_LSACR_COMPARE_ADDR          ((~0ull) >> 32)
 614         u64 mfc_lscrr_R;                                        /* 0x810 */
 615 #define MFC_LSCRR_Q                     (1 << 31)
 616 #define MFC_LSCRR_SPU_QUEUE             MFC_LSCRR_Q
 617 #define MFC_LSCRR_QI_SHIFT              32
 618 #define MFC_LSCRR_QI_MASK               ((~0ull) << MFC_LSCRR_QI_SHIFT)
 619         u8  pad_0x818_0x820[0x8];                               /* 0x818 */
 620         u64 mfc_tclass_id_RW;                                   /* 0x820 */
 621 #define MFC_TCLASS_ID_ENABLE            (1L << 0L)
 622 #define MFC_TCLASS_SLOT2_ENABLE         (1L << 5L)
 623 #define MFC_TCLASS_SLOT1_ENABLE         (1L << 6L)
 624 #define MFC_TCLASS_SLOT0_ENABLE         (1L << 7L)
 625 #define MFC_TCLASS_QUOTA_2_SHIFT        8L
 626 #define MFC_TCLASS_QUOTA_1_SHIFT        16L
 627 #define MFC_TCLASS_QUOTA_0_SHIFT        24L
 628 #define MFC_TCLASS_QUOTA_2_MASK         (0x1FL << MFC_TCLASS_QUOTA_2_SHIFT)
 629 #define MFC_TCLASS_QUOTA_1_MASK         (0x1FL << MFC_TCLASS_QUOTA_1_SHIFT)
 630 #define MFC_TCLASS_QUOTA_0_MASK         (0x1FL << MFC_TCLASS_QUOTA_0_SHIFT)
 631         u8  pad_0x828_0x900[0x900 - 0x828];                     /* 0x828 */
 632 
 633         /* Real Mode Support Registers */
 634         u64 mfc_rm_boundary;                                    /* 0x900 */
 635         u8  pad_0x908_0x938[0x30];                              /* 0x908 */
 636         u64 smf_dma_signal_sel;                                 /* 0x938 */
 637 #define mfc_dma1_mask_lsb       41
 638 #define mfc_dma1_shift          (63 - mfc_dma1_mask_lsb)
 639 #define mfc_dma1_mask           (0x3LL << mfc_dma1_shift)
 640 #define mfc_dma1_bits           (0x1LL << mfc_dma1_shift)
 641 #define mfc_dma2_mask_lsb       43
 642 #define mfc_dma2_shift          (63 - mfc_dma2_mask_lsb)
 643 #define mfc_dma2_mask           (0x3LL << mfc_dma2_shift)
 644 #define mfc_dma2_bits           (0x1LL << mfc_dma2_shift)
 645         u8  pad_0x940_0xa38[0xf8];                              /* 0x940 */
 646         u64 smm_signal_sel;                                     /* 0xa38 */
 647 #define smm_sig_mask_lsb        12
 648 #define smm_sig_shift           (63 - smm_sig_mask_lsb)
 649 #define smm_sig_mask            (0x3LL << smm_sig_shift)
 650 #define smm_sig_bus0_bits       (0x2LL << smm_sig_shift)
 651 #define smm_sig_bus2_bits       (0x1LL << smm_sig_shift)
 652         u8  pad_0xa40_0xc00[0xc00 - 0xa40];                     /* 0xa40 */
 653 
 654         /* DMA Command Error Area */
 655         u64 mfc_cer_R;                                          /* 0xc00 */
 656 #define MFC_CER_Q               (1 << 31)
 657 #define MFC_CER_SPU_QUEUE       MFC_CER_Q
 658         u8  pad_0xc08_0x1000[0x1000 - 0xc08];                   /* 0xc08 */
 659 
 660         /* PV1_ImplRegs: Implementation-dependent privileged-state 1 regs */
 661         /* DMA Command Error Area */
 662         u64 spu_ecc_cntl_RW;                                    /* 0x1000 */
 663 #define SPU_ECC_CNTL_E                  (1ull << 0ull)
 664 #define SPU_ECC_CNTL_ENABLE             SPU_ECC_CNTL_E
 665 #define SPU_ECC_CNTL_DISABLE            (~SPU_ECC_CNTL_E & 1L)
 666 #define SPU_ECC_CNTL_S                  (1ull << 1ull)
 667 #define SPU_ECC_STOP_AFTER_ERROR        SPU_ECC_CNTL_S
 668 #define SPU_ECC_CONTINUE_AFTER_ERROR    (~SPU_ECC_CNTL_S & 2L)
 669 #define SPU_ECC_CNTL_B                  (1ull << 2ull)
 670 #define SPU_ECC_BACKGROUND_ENABLE       SPU_ECC_CNTL_B
 671 #define SPU_ECC_BACKGROUND_DISABLE      (~SPU_ECC_CNTL_B & 4L)
 672 #define SPU_ECC_CNTL_I_SHIFT            3ull
 673 #define SPU_ECC_CNTL_I_MASK             (3ull << SPU_ECC_CNTL_I_SHIFT)
 674 #define SPU_ECC_WRITE_ALWAYS            (~SPU_ECC_CNTL_I & 12L)
 675 #define SPU_ECC_WRITE_CORRECTABLE       (1ull << SPU_ECC_CNTL_I_SHIFT)
 676 #define SPU_ECC_WRITE_UNCORRECTABLE     (3ull << SPU_ECC_CNTL_I_SHIFT)
 677 #define SPU_ECC_CNTL_D                  (1ull << 5ull)
 678 #define SPU_ECC_DETECTION_ENABLE        SPU_ECC_CNTL_D
 679 #define SPU_ECC_DETECTION_DISABLE       (~SPU_ECC_CNTL_D & 32L)
 680         u64 spu_ecc_stat_RW;                                    /* 0x1008 */
 681 #define SPU_ECC_CORRECTED_ERROR         (1ull << 0ul)
 682 #define SPU_ECC_UNCORRECTED_ERROR       (1ull << 1ul)
 683 #define SPU_ECC_SCRUB_COMPLETE          (1ull << 2ul)
 684 #define SPU_ECC_SCRUB_IN_PROGRESS       (1ull << 3ul)
 685 #define SPU_ECC_INSTRUCTION_ERROR       (1ull << 4ul)
 686 #define SPU_ECC_DATA_ERROR              (1ull << 5ul)
 687 #define SPU_ECC_DMA_ERROR               (1ull << 6ul)
 688 #define SPU_ECC_STATUS_CNT_MASK         (256ull << 8)
 689         u64 spu_ecc_addr_RW;                                    /* 0x1010 */
 690         u64 spu_err_mask_RW;                                    /* 0x1018 */
 691 #define SPU_ERR_ILLEGAL_INSTR           (1ull << 0ul)
 692 #define SPU_ERR_ILLEGAL_CHANNEL         (1ull << 1ul)
 693         u8  pad_0x1020_0x1028[0x1028 - 0x1020];                 /* 0x1020 */
 694 
 695         /* SPU Debug-Trace Bus (DTB) Selection Registers */
 696         u64 spu_trig0_sel;                                      /* 0x1028 */
 697         u64 spu_trig1_sel;                                      /* 0x1030 */
 698         u64 spu_trig2_sel;                                      /* 0x1038 */
 699         u64 spu_trig3_sel;                                      /* 0x1040 */
 700         u64 spu_trace_sel;                                      /* 0x1048 */
 701 #define spu_trace_sel_mask              0x1f1fLL
 702 #define spu_trace_sel_bus0_bits         0x1000LL
 703 #define spu_trace_sel_bus2_bits         0x0010LL
 704         u64 spu_event0_sel;                                     /* 0x1050 */
 705         u64 spu_event1_sel;                                     /* 0x1058 */
 706         u64 spu_event2_sel;                                     /* 0x1060 */
 707         u64 spu_event3_sel;                                     /* 0x1068 */
 708         u64 spu_trace_cntl;                                     /* 0x1070 */
 709 } __attribute__ ((aligned(0x2000)));
 710 
 711 #endif /* __KERNEL__ */
 712 #endif
/* [<][>][^][v][top][bottom][index][help] */