1 /* SPDX-License-Identifier: GPL-2.0-or-later */
2 /*
3 * IPIC external definitions and structure.
4 *
5 * Maintainer: Kumar Gala <galak@kernel.crashing.org>
6 *
7 * Copyright 2005 Freescale Semiconductor, Inc
8 */
9 #ifdef __KERNEL__
10 #ifndef __ASM_IPIC_H__
11 #define __ASM_IPIC_H__
12
13 #include <linux/irq.h>
14
15 /* Flags when we init the IPIC */
16 #define IPIC_SPREADMODE_GRP_A 0x00000001
17 #define IPIC_SPREADMODE_GRP_B 0x00000002
18 #define IPIC_SPREADMODE_GRP_C 0x00000004
19 #define IPIC_SPREADMODE_GRP_D 0x00000008
20 #define IPIC_SPREADMODE_MIX_A 0x00000010
21 #define IPIC_SPREADMODE_MIX_B 0x00000020
22 #define IPIC_DISABLE_MCP_OUT 0x00000040
23 #define IPIC_IRQ0_MCP 0x00000080
24
25 /* IPIC registers offsets */
26 #define IPIC_SICFR 0x00 /* System Global Interrupt Configuration Register */
27 #define IPIC_SIVCR 0x04 /* System Global Interrupt Vector Register */
28 #define IPIC_SIPNR_H 0x08 /* System Internal Interrupt Pending Register (HIGH) */
29 #define IPIC_SIPNR_L 0x0C /* System Internal Interrupt Pending Register (LOW) */
30 #define IPIC_SIPRR_A 0x10 /* System Internal Interrupt group A Priority Register */
31 #define IPIC_SIPRR_B 0x14 /* System Internal Interrupt group B Priority Register */
32 #define IPIC_SIPRR_C 0x18 /* System Internal Interrupt group C Priority Register */
33 #define IPIC_SIPRR_D 0x1C /* System Internal Interrupt group D Priority Register */
34 #define IPIC_SIMSR_H 0x20 /* System Internal Interrupt Mask Register (HIGH) */
35 #define IPIC_SIMSR_L 0x24 /* System Internal Interrupt Mask Register (LOW) */
36 #define IPIC_SICNR 0x28 /* System Internal Interrupt Control Register */
37 #define IPIC_SEPNR 0x2C /* System External Interrupt Pending Register */
38 #define IPIC_SMPRR_A 0x30 /* System Mixed Interrupt group A Priority Register */
39 #define IPIC_SMPRR_B 0x34 /* System Mixed Interrupt group B Priority Register */
40 #define IPIC_SEMSR 0x38 /* System External Interrupt Mask Register */
41 #define IPIC_SECNR 0x3C /* System External Interrupt Control Register */
42 #define IPIC_SERSR 0x40 /* System Error Status Register */
43 #define IPIC_SERMR 0x44 /* System Error Mask Register */
44 #define IPIC_SERCR 0x48 /* System Error Control Register */
45 #define IPIC_SIFCR_H 0x50 /* System Internal Interrupt Force Register (HIGH) */
46 #define IPIC_SIFCR_L 0x54 /* System Internal Interrupt Force Register (LOW) */
47 #define IPIC_SEFCR 0x58 /* System External Interrupt Force Register */
48 #define IPIC_SERFR 0x5C /* System Error Force Register */
49 #define IPIC_SCVCR 0x60 /* System Critical Interrupt Vector Register */
50 #define IPIC_SMVCR 0x64 /* System Management Interrupt Vector Register */
51
52 enum ipic_prio_grp {
53 IPIC_INT_GRP_A = IPIC_SIPRR_A,
54 IPIC_INT_GRP_D = IPIC_SIPRR_D,
55 IPIC_MIX_GRP_A = IPIC_SMPRR_A,
56 IPIC_MIX_GRP_B = IPIC_SMPRR_B,
57 };
58
59 enum ipic_mcp_irq {
60 IPIC_MCP_IRQ0 = 0,
61 IPIC_MCP_WDT = 1,
62 IPIC_MCP_SBA = 2,
63 IPIC_MCP_PCI1 = 5,
64 IPIC_MCP_PCI2 = 6,
65 IPIC_MCP_MU = 7,
66 };
67
68 extern void ipic_set_default_priority(void);
69 extern u32 ipic_get_mcp_status(void);
70 extern void ipic_clear_mcp_status(u32 mask);
71
72 extern struct ipic * ipic_init(struct device_node *node, unsigned int flags);
73 extern unsigned int ipic_get_irq(void);
74
75 #endif /* __ASM_IPIC_H__ */
76 #endif /* __KERNEL__ */