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11 #ifdef __KERNEL__
12 #ifndef __ASM_POWERPC_REG_BOOKE_H__
13 #define __ASM_POWERPC_REG_BOOKE_H__
14
15 #include <asm/ppc-opcode.h>
16
17
18 #define MSR_GS_LG 28
19 #define MSR_UCLE_LG 26
20 #define MSR_SPE_LG 25
21 #define MSR_DWE_LG 10
22 #define MSR_UBLE_LG 10
23 #define MSR_IS_LG MSR_IR_LG
24 #define MSR_DS_LG MSR_DR_LG
25 #define MSR_PMM_LG 2
26 #define MSR_CM_LG 31
27
28 #define MSR_GS __MASK(MSR_GS_LG)
29 #define MSR_UCLE __MASK(MSR_UCLE_LG)
30 #define MSR_SPE __MASK(MSR_SPE_LG)
31 #define MSR_DWE __MASK(MSR_DWE_LG)
32 #define MSR_UBLE __MASK(MSR_UBLE_LG)
33 #define MSR_IS __MASK(MSR_IS_LG)
34 #define MSR_DS __MASK(MSR_DS_LG)
35 #define MSR_PMM __MASK(MSR_PMM_LG)
36 #define MSR_CM __MASK(MSR_CM_LG)
37
38 #if defined(CONFIG_PPC_BOOK3E_64)
39 #define MSR_64BIT MSR_CM
40
41 #define MSR_ (MSR_ME | MSR_RI | MSR_CE)
42 #define MSR_KERNEL (MSR_ | MSR_64BIT)
43 #define MSR_USER32 (MSR_ | MSR_PR | MSR_EE)
44 #define MSR_USER64 (MSR_USER32 | MSR_64BIT)
45 #elif defined (CONFIG_40x)
46 #define MSR_KERNEL (MSR_ME|MSR_RI|MSR_IR|MSR_DR|MSR_CE)
47 #define MSR_USER (MSR_KERNEL|MSR_PR|MSR_EE)
48 #else
49 #define MSR_KERNEL (MSR_ME|MSR_RI|MSR_CE)
50 #define MSR_USER (MSR_KERNEL|MSR_PR|MSR_EE)
51 #endif
52
53
54 #define SPRN_DECAR 0x036
55 #define SPRN_IVPR 0x03F
56 #define SPRN_USPRG0 0x100
57 #define SPRN_SPRG3R 0x103
58 #define SPRN_SPRG4R 0x104
59 #define SPRN_SPRG5R 0x105
60 #define SPRN_SPRG6R 0x106
61 #define SPRN_SPRG7R 0x107
62 #define SPRN_SPRG4W 0x114
63 #define SPRN_SPRG5W 0x115
64 #define SPRN_SPRG6W 0x116
65 #define SPRN_SPRG7W 0x117
66 #define SPRN_EPCR 0x133
67 #define SPRN_DBCR2 0x136
68 #define SPRN_DBCR4 0x233
69 #define SPRN_MSRP 0x137
70 #define SPRN_IAC3 0x13A
71 #define SPRN_IAC4 0x13B
72 #define SPRN_DVC1 0x13E
73 #define SPRN_DVC2 0x13F
74 #define SPRN_LPID 0x152
75 #define SPRN_MAS8 0x155
76 #define SPRN_TLB0PS 0x158
77 #define SPRN_TLB1PS 0x159
78 #define SPRN_MAS5_MAS6 0x15c
79 #define SPRN_MAS8_MAS1 0x15d
80 #define SPRN_EPTCFG 0x15e
81 #define SPRN_GSPRG0 0x170
82 #define SPRN_GSPRG1 0x171
83 #define SPRN_GSPRG2 0x172
84 #define SPRN_GSPRG3 0x173
85 #define SPRN_MAS7_MAS3 0x174
86 #define SPRN_MAS0_MAS1 0x175
87 #define SPRN_GSRR0 0x17A
88 #define SPRN_GSRR1 0x17B
89 #define SPRN_GEPR 0x17C
90 #define SPRN_GDEAR 0x17D
91 #define SPRN_GPIR 0x17E
92 #define SPRN_GESR 0x17F
93 #define SPRN_IVOR0 0x190
94 #define SPRN_IVOR1 0x191
95 #define SPRN_IVOR2 0x192
96 #define SPRN_IVOR3 0x193
97 #define SPRN_IVOR4 0x194
98 #define SPRN_IVOR5 0x195
99 #define SPRN_IVOR6 0x196
100 #define SPRN_IVOR7 0x197
101 #define SPRN_IVOR8 0x198
102 #define SPRN_IVOR9 0x199
103 #define SPRN_IVOR10 0x19A
104 #define SPRN_IVOR11 0x19B
105 #define SPRN_IVOR12 0x19C
106 #define SPRN_IVOR13 0x19D
107 #define SPRN_IVOR14 0x19E
108 #define SPRN_IVOR15 0x19F
109 #define SPRN_IVOR38 0x1B0
110 #define SPRN_IVOR39 0x1B1
111 #define SPRN_IVOR40 0x1B2
112 #define SPRN_IVOR41 0x1B3
113 #define SPRN_IVOR42 0x1B4
114 #define SPRN_GIVOR2 0x1B8
115 #define SPRN_GIVOR3 0x1B9
116 #define SPRN_GIVOR4 0x1BA
117 #define SPRN_GIVOR8 0x1BB
118 #define SPRN_GIVOR13 0x1BC
119 #define SPRN_GIVOR14 0x1BD
120 #define SPRN_GIVPR 0x1BF
121 #define SPRN_SPEFSCR 0x200
122 #define SPRN_BBEAR 0x201
123 #define SPRN_BBTAR 0x202
124 #define SPRN_L1CFG0 0x203
125 #define SPRN_L1CFG1 0x204
126 #define SPRN_ATB 0x20E
127 #define SPRN_ATBL 0x20E
128 #define SPRN_ATBU 0x20F
129 #define SPRN_IVOR32 0x210
130 #define SPRN_IVOR33 0x211
131 #define SPRN_IVOR34 0x212
132 #define SPRN_IVOR35 0x213
133 #define SPRN_IVOR36 0x214
134 #define SPRN_IVOR37 0x215
135 #define SPRN_MCARU 0x239
136 #define SPRN_MCSRR0 0x23A
137 #define SPRN_MCSRR1 0x23B
138 #define SPRN_MCSR 0x23C
139 #define SPRN_MCAR 0x23D
140 #define SPRN_DSRR0 0x23E
141 #define SPRN_DSRR1 0x23F
142 #define SPRN_SPRG8 0x25C
143 #define SPRN_SPRG9 0x25D
144 #define SPRN_L1CSR2 0x25E
145 #define SPRN_MAS0 0x270
146 #define SPRN_MAS1 0x271
147 #define SPRN_MAS2 0x272
148 #define SPRN_MAS3 0x273
149 #define SPRN_MAS4 0x274
150 #define SPRN_MAS5 0x153
151 #define SPRN_MAS6 0x276
152 #define SPRN_PID1 0x279
153 #define SPRN_PID2 0x27A
154 #define SPRN_TLB0CFG 0x2B0
155 #define SPRN_TLB1CFG 0x2B1
156 #define SPRN_TLB2CFG 0x2B2
157 #define SPRN_TLB3CFG 0x2B3
158 #define SPRN_EPR 0x2BE
159 #define SPRN_CCR1 0x378
160 #define SPRN_ZPR 0x3B0
161 #define SPRN_MAS7 0x3B0
162 #define SPRN_MMUCR 0x3B2
163 #define SPRN_CCR0 0x3B3
164 #define SPRN_EPLC 0x3B3
165 #define SPRN_EPSC 0x3B4
166 #define SPRN_SGR 0x3B9
167 #define SPRN_DCWR 0x3BA
168 #define SPRN_SLER 0x3BB
169 #define SPRN_SU0R 0x3BC
170 #define SPRN_DCMP 0x3D1
171 #define SPRN_ICDBDR 0x3D3
172 #define SPRN_EVPR 0x3D6
173 #define SPRN_L1CSR0 0x3F2
174 #define SPRN_L1CSR1 0x3F3
175 #define SPRN_MMUCSR0 0x3F4
176 #define SPRN_MMUCFG 0x3F7
177 #define SPRN_PIT 0x3DB
178 #define SPRN_BUCSR 0x3F5
179 #define SPRN_L2CSR0 0x3F9
180 #define SPRN_L2CSR1 0x3FA
181 #define SPRN_DCCR 0x3FA
182 #define SPRN_ICCR 0x3FB
183 #define SPRN_PWRMGTCR0 0x3FB
184 #define SPRN_SVR 0x3FF
185
186
187
188
189
190 #ifdef CONFIG_BOOKE
191 #define SPRN_CSRR0 0x03A
192 #define SPRN_CSRR1 0x03B
193 #define SPRN_DEAR 0x03D
194 #define SPRN_ESR 0x03E
195 #define SPRN_PIR 0x11E
196 #define SPRN_DBSR 0x130
197 #define SPRN_DBCR0 0x134
198 #define SPRN_DBCR1 0x135
199 #define SPRN_IAC1 0x138
200 #define SPRN_IAC2 0x139
201 #define SPRN_DAC1 0x13C
202 #define SPRN_DAC2 0x13D
203 #define SPRN_TSR 0x150
204 #define SPRN_TCR 0x154
205 #endif
206 #ifdef CONFIG_40x
207 #define SPRN_DBCR1 0x3BD
208 #define SPRN_ESR 0x3D4
209 #define SPRN_DEAR 0x3D5
210 #define SPRN_TSR 0x3D8
211 #define SPRN_TCR 0x3DA
212 #define SPRN_SRR2 0x3DE
213 #define SPRN_SRR3 0x3DF
214 #define SPRN_DBSR 0x3F0
215 #define SPRN_DBCR0 0x3F2
216 #define SPRN_DAC1 0x3F6
217 #define SPRN_DAC2 0x3F7
218 #define SPRN_CSRR0 SPRN_SRR2
219 #define SPRN_CSRR1 SPRN_SRR3
220 #endif
221 #define SPRN_HACOP 0x15F
222
223
224 #define CCR1_DPC 0x00000100
225 #define CCR1_TCS 0x00000080
226
227
228 #define PWRMGTCR0_PW20_WAIT (1 << 14)
229 #define PWRMGTCR0_PW20_ENT_SHIFT 8
230 #define PWRMGTCR0_PW20_ENT 0x3F00
231 #define PWRMGTCR0_AV_IDLE_PD_EN (1 << 22)
232 #define PWRMGTCR0_AV_IDLE_CNT_SHIFT 16
233 #define PWRMGTCR0_AV_IDLE_CNT 0x3F0000
234
235
236 #define MCSR_MCS 0x80000000
237 #define MCSR_IB 0x40000000
238 #define MCSR_DRB 0x20000000
239 #define MCSR_DWB 0x10000000
240 #define MCSR_TLBP 0x08000000
241 #define MCSR_ICP 0x04000000
242 #define MCSR_DCSP 0x02000000
243 #define MCSR_DCFP 0x01000000
244 #define MCSR_IMPE 0x00800000
245
246 #define PPC47x_MCSR_GPR 0x01000000
247 #define PPC47x_MCSR_FPR 0x00800000
248 #define PPC47x_MCSR_IPR 0x00400000
249
250 #ifdef CONFIG_E500
251
252 #define MCSR_MCP 0x80000000UL
253 #define MCSR_ICPERR 0x40000000UL
254
255
256 #define MCSR_DCP_PERR 0x20000000UL
257 #define MCSR_DCPERR 0x10000000UL
258 #define MCSR_BUS_IAERR 0x00000080UL
259 #define MCSR_BUS_RAERR 0x00000040UL
260 #define MCSR_BUS_WAERR 0x00000020UL
261 #define MCSR_BUS_IBERR 0x00000010UL
262 #define MCSR_BUS_RBERR 0x00000008UL
263 #define MCSR_BUS_WBERR 0x00000004UL
264 #define MCSR_BUS_IPERR 0x00000002UL
265 #define MCSR_BUS_RPERR 0x00000001UL
266
267
268 #define MCSR_DCPERR_MC 0x20000000UL
269 #define MCSR_L2MMU_MHIT 0x08000000UL
270 #define MCSR_NMI 0x00100000UL
271 #define MCSR_MAV 0x00080000UL
272 #define MCSR_MEA 0x00040000UL
273 #define MCSR_IF 0x00010000UL
274 #define MCSR_LD 0x00008000UL
275 #define MCSR_ST 0x00004000UL
276 #define MCSR_LDG 0x00002000UL
277 #define MCSR_TLBSYNC 0x00000002UL
278 #define MCSR_BSL2_ERR 0x00000001UL
279
280 #define MSRP_UCLEP 0x04000000
281 #define MSRP_DEP 0x00000200
282 #define MSRP_PMMP 0x00000004
283 #endif
284
285 #ifdef CONFIG_E200
286 #define MCSR_MCP 0x80000000UL
287 #define MCSR_CP_PERR 0x20000000UL
288 #define MCSR_CPERR 0x10000000UL
289 #define MCSR_EXCP_ERR 0x08000000UL
290
291 #define MCSR_BUS_IRERR 0x00000010UL
292 #define MCSR_BUS_DRERR 0x00000008UL
293 #define MCSR_BUS_WRERR 0x00000004UL
294
295 #endif
296
297
298 #ifdef CONFIG_E500
299
300 #define HID1_PLL_CFG_MASK 0xfc000000
301 #define HID1_RFXE 0x00020000
302 #define HID1_R1DPE 0x00008000
303 #define HID1_R2DPE 0x00004000
304 #define HID1_ASTME 0x00002000
305 #define HID1_ABE 0x00001000
306 #define HID1_MPXTT 0x00000400
307 #define HID1_ATS 0x00000080
308 #define HID1_MID_MASK 0x0000000f
309 #endif
310
311
312
313
314
315 #ifdef CONFIG_BOOKE
316 #define DBSR_IDE 0x80000000
317 #define DBSR_MRR 0x30000000
318 #define DBSR_IC 0x08000000
319 #define DBSR_BT 0x04000000
320 #define DBSR_IRPT 0x02000000
321 #define DBSR_TIE 0x01000000
322 #define DBSR_IAC1 0x00800000
323 #define DBSR_IAC2 0x00400000
324 #define DBSR_IAC3 0x00200000
325 #define DBSR_IAC4 0x00100000
326 #define DBSR_DAC1R 0x00080000
327 #define DBSR_DAC1W 0x00040000
328 #define DBSR_DAC2R 0x00020000
329 #define DBSR_DAC2W 0x00010000
330 #define DBSR_RET 0x00008000
331 #define DBSR_CIRPT 0x00000040
332 #define DBSR_CRET 0x00000020
333 #define DBSR_IAC12ATS 0x00000002
334 #define DBSR_IAC34ATS 0x00000001
335 #endif
336 #ifdef CONFIG_40x
337 #define DBSR_IC 0x80000000
338 #define DBSR_BT 0x40000000
339 #define DBSR_IRPT 0x20000000
340 #define DBSR_TIE 0x10000000
341 #define DBSR_IAC1 0x04000000
342 #define DBSR_IAC2 0x02000000
343 #define DBSR_IAC3 0x00080000
344 #define DBSR_IAC4 0x00040000
345 #define DBSR_DAC1R 0x01000000
346 #define DBSR_DAC1W 0x00800000
347 #define DBSR_DAC2R 0x00400000
348 #define DBSR_DAC2W 0x00200000
349 #endif
350
351
352 #define ESR_MCI 0x80000000
353 #define ESR_IMCP 0x80000000
354 #define ESR_IMCN 0x40000000
355 #define ESR_IMCB 0x20000000
356 #define ESR_IMCT 0x10000000
357 #define ESR_PIL 0x08000000
358 #define ESR_PPR 0x04000000
359 #define ESR_PTR 0x02000000
360 #define ESR_FP 0x01000000
361 #define ESR_DST 0x00800000
362 #define ESR_DIZ 0x00400000
363 #define ESR_ST 0x00800000
364 #define ESR_DLK 0x00200000
365 #define ESR_ILK 0x00100000
366 #define ESR_PUO 0x00040000
367 #define ESR_BO 0x00020000
368 #define ESR_SPV 0x00000080
369
370
371 #if defined(CONFIG_40x)
372 #define DBCR0_EDM 0x80000000
373 #define DBCR0_IDM 0x40000000
374 #define DBCR0_RST 0x30000000
375 #define DBCR0_RST_SYSTEM 0x30000000
376 #define DBCR0_RST_CHIP 0x20000000
377 #define DBCR0_RST_CORE 0x10000000
378 #define DBCR0_RST_NONE 0x00000000
379 #define DBCR0_IC 0x08000000
380 #define DBCR0_ICMP DBCR0_IC
381 #define DBCR0_BT 0x04000000
382 #define DBCR0_BRT DBCR0_BT
383 #define DBCR0_EDE 0x02000000
384 #define DBCR0_IRPT DBCR0_EDE
385 #define DBCR0_TDE 0x01000000
386 #define DBCR0_IA1 0x00800000
387 #define DBCR0_IAC1 DBCR0_IA1
388 #define DBCR0_IA2 0x00400000
389 #define DBCR0_IAC2 DBCR0_IA2
390 #define DBCR0_IA12 0x00200000
391 #define DBCR0_IA12X 0x00100000
392 #define DBCR0_IA3 0x00080000
393 #define DBCR0_IAC3 DBCR0_IA3
394 #define DBCR0_IA4 0x00040000
395 #define DBCR0_IAC4 DBCR0_IA4
396 #define DBCR0_IA34 0x00020000
397 #define DBCR0_IA34X 0x00010000
398 #define DBCR0_IA12T 0x00008000
399 #define DBCR0_IA34T 0x00004000
400 #define DBCR0_FT 0x00000001
401
402 #define dbcr_iac_range(task) ((task)->thread.debug.dbcr0)
403 #define DBCR_IAC12I DBCR0_IA12
404 #define DBCR_IAC12X (DBCR0_IA12 | DBCR0_IA12X)
405 #define DBCR_IAC12MODE (DBCR0_IA12 | DBCR0_IA12X)
406 #define DBCR_IAC34I DBCR0_IA34
407 #define DBCR_IAC34X (DBCR0_IA34 | DBCR0_IA34X)
408 #define DBCR_IAC34MODE (DBCR0_IA34 | DBCR0_IA34X)
409
410
411 #define DBCR1_DAC1R 0x80000000
412 #define DBCR1_DAC2R 0x40000000
413 #define DBCR1_DAC1W 0x20000000
414 #define DBCR1_DAC2W 0x10000000
415
416 #define dbcr_dac(task) ((task)->thread.debug.dbcr1)
417 #define DBCR_DAC1R DBCR1_DAC1R
418 #define DBCR_DAC1W DBCR1_DAC1W
419 #define DBCR_DAC2R DBCR1_DAC2R
420 #define DBCR_DAC2W DBCR1_DAC2W
421
422
423
424
425
426 #define DBCR0_ACTIVE_EVENTS (DBCR0_ICMP | DBCR0_IAC1 | DBCR0_IAC2 | \
427 DBCR0_IAC3 | DBCR0_IAC4)
428 #define DBCR1_ACTIVE_EVENTS (DBCR1_DAC1R | DBCR1_DAC2R | \
429 DBCR1_DAC1W | DBCR1_DAC2W)
430 #define DBCR_ACTIVE_EVENTS(dbcr0, dbcr1) (((dbcr0) & DBCR0_ACTIVE_EVENTS) || \
431 ((dbcr1) & DBCR1_ACTIVE_EVENTS))
432
433 #elif defined(CONFIG_BOOKE)
434 #define DBCR0_EDM 0x80000000
435 #define DBCR0_IDM 0x40000000
436 #define DBCR0_RST 0x30000000
437
438 #define DBCR0_RST_SYSTEM 0x30000000
439 #define DBCR0_RST_CHIP 0x20000000
440 #define DBCR0_RST_CORE 0x10000000
441 #define DBCR0_RST_NONE 0x00000000
442 #define DBCR0_ICMP 0x08000000
443 #define DBCR0_IC DBCR0_ICMP
444 #define DBCR0_BRT 0x04000000
445 #define DBCR0_BT DBCR0_BRT
446 #define DBCR0_IRPT 0x02000000
447 #define DBCR0_TDE 0x01000000
448 #define DBCR0_TIE DBCR0_TDE
449 #define DBCR0_IAC1 0x00800000
450 #define DBCR0_IAC2 0x00400000
451 #define DBCR0_IAC3 0x00200000
452 #define DBCR0_IAC4 0x00100000
453 #define DBCR0_DAC1R 0x00080000
454 #define DBCR0_DAC1W 0x00040000
455 #define DBCR0_DAC2R 0x00020000
456 #define DBCR0_DAC2W 0x00010000
457 #define DBCR0_RET 0x00008000
458 #define DBCR0_CIRPT 0x00000040
459 #define DBCR0_CRET 0x00000020
460 #define DBCR0_FT 0x00000001
461
462 #define dbcr_dac(task) ((task)->thread.debug.dbcr0)
463 #define DBCR_DAC1R DBCR0_DAC1R
464 #define DBCR_DAC1W DBCR0_DAC1W
465 #define DBCR_DAC2R DBCR0_DAC2R
466 #define DBCR_DAC2W DBCR0_DAC2W
467
468
469 #define DBCR1_IAC1US 0xC0000000
470 #define DBCR1_IAC1ER 0x30000000
471 #define DBCR1_IAC1ER_01 0x10000000
472 #define DBCR1_IAC1ER_10 0x20000000
473 #define DBCR1_IAC1ER_11 0x30000000
474 #define DBCR1_IAC2US 0x0C000000
475 #define DBCR1_IAC2ER 0x03000000
476 #define DBCR1_IAC2ER_01 0x01000000
477 #define DBCR1_IAC2ER_10 0x02000000
478 #define DBCR1_IAC2ER_11 0x03000000
479 #define DBCR1_IAC12M 0x00800000
480 #define DBCR1_IAC12MX 0x00C00000
481 #define DBCR1_IAC12AT 0x00010000
482 #define DBCR1_IAC3US 0x0000C000
483 #define DBCR1_IAC3ER 0x00003000
484 #define DBCR1_IAC3ER_01 0x00001000
485 #define DBCR1_IAC3ER_10 0x00002000
486 #define DBCR1_IAC3ER_11 0x00003000
487 #define DBCR1_IAC4US 0x00000C00
488 #define DBCR1_IAC4ER 0x00000300
489 #define DBCR1_IAC4ER_01 0x00000100
490 #define DBCR1_IAC4ER_10 0x00000200
491 #define DBCR1_IAC4ER_11 0x00000300
492 #define DBCR1_IAC34M 0x00000080
493 #define DBCR1_IAC34MX 0x000000C0
494 #define DBCR1_IAC34AT 0x00000001
495
496 #define dbcr_iac_range(task) ((task)->thread.debug.dbcr1)
497 #define DBCR_IAC12I DBCR1_IAC12M
498 #define DBCR_IAC12X DBCR1_IAC12MX
499 #define DBCR_IAC12MODE DBCR1_IAC12MX
500 #define DBCR_IAC34I DBCR1_IAC34M
501 #define DBCR_IAC34X DBCR1_IAC34MX
502 #define DBCR_IAC34MODE DBCR1_IAC34MX
503
504
505 #define DBCR2_DAC1US 0xC0000000
506 #define DBCR2_DAC1ER 0x30000000
507 #define DBCR2_DAC2US 0x0C000000
508 #define DBCR2_DAC2ER 0x03000000
509 #define DBCR2_DAC12M 0x00800000
510 #define DBCR2_DAC12MM 0x00400000
511 #define DBCR2_DAC12MX 0x00C00000
512 #define DBCR2_DAC12MODE 0x00C00000
513 #define DBCR2_DAC12A 0x00200000
514 #define DBCR2_DVC1M 0x000C0000
515 #define DBCR2_DVC1M_SHIFT 18
516 #define DBCR2_DVC2M 0x00030000
517 #define DBCR2_DVC2M_SHIFT 16
518 #define DBCR2_DVC1BE 0x00000F00
519 #define DBCR2_DVC1BE_SHIFT 8
520 #define DBCR2_DVC2BE 0x0000000F
521 #define DBCR2_DVC2BE_SHIFT 0
522
523
524
525
526
527 #define DBCR0_ACTIVE_EVENTS (DBCR0_ICMP | DBCR0_IAC1 | DBCR0_IAC2 | \
528 DBCR0_IAC3 | DBCR0_IAC4 | DBCR0_DAC1R | \
529 DBCR0_DAC1W | DBCR0_DAC2R | DBCR0_DAC2W)
530 #define DBCR1_ACTIVE_EVENTS 0
531
532 #define DBCR_ACTIVE_EVENTS(dbcr0, dbcr1) (((dbcr0) & DBCR0_ACTIVE_EVENTS) || \
533 ((dbcr1) & DBCR1_ACTIVE_EVENTS))
534 #endif
535
536
537 #define TCR_WP(x) (((x)&0x3)<<30)
538 #define TCR_WP_MASK TCR_WP(3)
539 #define WP_2_17 0
540 #define WP_2_21 1
541 #define WP_2_25 2
542 #define WP_2_29 3
543 #define TCR_WRC(x) (((x)&0x3)<<28)
544 #define TCR_WRC_MASK TCR_WRC(3)
545 #define WRC_NONE 0
546 #define WRC_CORE 1
547 #define WRC_CHIP 2
548 #define WRC_SYSTEM 3
549 #define TCR_WIE 0x08000000
550 #define TCR_PIE 0x04000000
551 #define TCR_DIE TCR_PIE
552 #define TCR_FP(x) (((x)&0x3)<<24)
553 #define TCR_FP_MASK TCR_FP(3)
554 #define FP_2_9 0
555 #define FP_2_13 1
556 #define FP_2_17 2
557 #define FP_2_21 3
558 #define TCR_FIE 0x00800000
559 #define TCR_ARE 0x00400000
560
561 #ifdef CONFIG_E500
562 #define TCR_GET_WP(tcr) ((((tcr) & 0xC0000000) >> 30) | \
563 (((tcr) & 0x1E0000) >> 15))
564 #else
565 #define TCR_GET_WP(tcr) (((tcr) & 0xC0000000) >> 30)
566 #endif
567
568
569 #define TSR_ENW 0x80000000
570 #define TSR_WIS 0x40000000
571 #define TSR_WRS(x) (((x)&0x3)<<28)
572 #define WRS_NONE 0
573 #define WRS_CORE 1
574 #define WRS_CHIP 2
575 #define WRS_SYSTEM 3
576 #define TSR_PIS 0x08000000
577 #define TSR_DIS TSR_PIS
578 #define TSR_FIS 0x04000000
579
580
581 #define DCCR_NOCACHE 0
582 #define DCCR_CACHE 1
583
584
585 #define DCWR_COPY 0
586 #define DCWR_WRITE 1
587
588
589 #define ICCR_NOCACHE 0
590 #define ICCR_CACHE 1
591
592
593 #define L1CSR0_CPE 0x00010000
594 #define L1CSR0_CUL 0x00000400
595 #define L1CSR0_CLFC 0x00000100
596 #define L1CSR0_DCFI 0x00000002
597 #define L1CSR0_CFI 0x00000002
598 #define L1CSR0_DCE 0x00000001
599
600
601 #define L1CSR1_CPE 0x00010000
602 #define L1CSR1_ICLFR 0x00000100
603 #define L1CSR1_ICFI 0x00000002
604 #define L1CSR1_ICE 0x00000001
605
606
607 #define L1CSR2_DCWS 0x40000000
608
609
610 #define BUCSR_STAC_EN 0x01000000
611 #define BUCSR_LS_EN 0x00400000
612 #define BUCSR_BBFI 0x00000200
613 #define BUCSR_BPEN 0x00000001
614 #define BUCSR_INIT (BUCSR_STAC_EN | BUCSR_LS_EN | BUCSR_BBFI | BUCSR_BPEN)
615
616
617 #define L2CSR0_L2E 0x80000000
618 #define L2CSR0_L2PE 0x40000000
619 #define L2CSR0_L2WP 0x1c000000
620 #define L2CSR0_L2CM 0x03000000
621 #define L2CSR0_L2FI 0x00200000
622 #define L2CSR0_L2IO 0x00100000
623 #define L2CSR0_L2DO 0x00010000
624 #define L2CSR0_L2REP 0x00003000
625 #define L2CSR0_L2FL 0x00000800
626 #define L2CSR0_L2LFC 0x00000400
627 #define L2CSR0_L2LOA 0x00000080
628 #define L2CSR0_L2LO 0x00000020
629
630
631 #define SGR_NORMAL 0
632 #define SGR_GUARDED 1
633
634
635 #define SPRN_EPCR_EXTGS 0x80000000
636
637 #define SPRN_EPCR_DTLBGS 0x40000000
638
639 #define SPRN_EPCR_ITLBGS 0x20000000
640
641 #define SPRN_EPCR_DSIGS 0x10000000
642
643 #define SPRN_EPCR_ISIGS 0x08000000
644
645 #define SPRN_EPCR_DUVD 0x04000000
646 #define SPRN_EPCR_ICM 0x02000000
647
648 #define SPRN_EPCR_GICM 0x01000000
649 #define SPRN_EPCR_DGTMI 0x00800000
650
651 #define SPRN_EPCR_DMIUH 0x00400000
652
653
654
655 #define EPC_EPR 0x80000000
656 #define EPC_EPR_SHIFT 31
657 #define EPC_EAS 0x40000000
658 #define EPC_EAS_SHIFT 30
659 #define EPC_EGS 0x20000000
660 #define EPC_EGS_SHIFT 29
661 #define EPC_ELPID 0x00ff0000
662 #define EPC_ELPID_SHIFT 16
663 #define EPC_EPID 0x00003fff
664 #define EPC_EPID_SHIFT 0
665
666
667
668
669
670
671 #ifdef CONFIG_403GCX
672
673 #define SPRN_TBHU 0x3CC
674 #define SPRN_TBLU 0x3CD
675 #define SPRN_CDBCR 0x3D7
676 #define SPRN_TBHI 0x3DC
677 #define SPRN_TBLO 0x3DD
678 #define SPRN_DBCR 0x3F2
679 #define SPRN_PBL1 0x3FC
680 #define SPRN_PBL2 0x3FE
681 #define SPRN_PBU1 0x3FD
682 #define SPRN_PBU2 0x3FF
683
684
685
686 #define DBCR_EDM DBCR0_EDM
687 #define DBCR_IDM DBCR0_IDM
688 #define DBCR_RST(x) (((x) & 0x3) << 28)
689 #define DBCR_RST_NONE 0
690 #define DBCR_RST_CORE 1
691 #define DBCR_RST_CHIP 2
692 #define DBCR_RST_SYSTEM 3
693 #define DBCR_IC DBCR0_IC
694 #define DBCR_BT DBCR0_BT
695 #define DBCR_EDE DBCR0_EDE
696 #define DBCR_TDE DBCR0_TDE
697 #define DBCR_FER 0x00F80000
698 #define DBCR_FT 0x00040000
699 #define DBCR_IA1 0x00020000
700 #define DBCR_IA2 0x00010000
701 #define DBCR_D1R 0x00008000
702 #define DBCR_D1W 0x00004000
703 #define DBCR_D1S(x) (((x) & 0x3) << 12)
704 #define DAC_BYTE 0
705 #define DAC_HALF 1
706 #define DAC_WORD 2
707 #define DAC_QUAD 3
708 #define DBCR_D2R 0x00000800
709 #define DBCR_D2W 0x00000400
710 #define DBCR_D2S(x) (((x) & 0x3) << 8)
711 #define DBCR_SBT 0x00000040
712 #define DBCR_SED 0x00000020
713 #define DBCR_STD 0x00000010
714 #define DBCR_SIA 0x00000008
715 #define DBCR_SDA 0x00000004
716 #define DBCR_JOI 0x00000002
717 #define DBCR_JII 0x00000001
718 #endif
719
720
721 #define SPRN_SSPCR 830
722 #define SPRN_USPCR 831
723 #define SPRN_ISPCR 829
724 #define SPRN_MMUBE0 820
725 #define MMUBE0_IBE0_SHIFT 24
726 #define MMUBE0_IBE1_SHIFT 16
727 #define MMUBE0_IBE2_SHIFT 8
728 #define MMUBE0_VBE0 0x00000004
729 #define MMUBE0_VBE1 0x00000002
730 #define MMUBE0_VBE2 0x00000001
731 #define SPRN_MMUBE1 821
732 #define MMUBE1_IBE3_SHIFT 24
733 #define MMUBE1_IBE4_SHIFT 16
734 #define MMUBE1_IBE5_SHIFT 8
735 #define MMUBE1_VBE3 0x00000004
736 #define MMUBE1_VBE4 0x00000002
737 #define MMUBE1_VBE5 0x00000001
738
739 #define TMRN_TMCFG0 16
740 #define TMRN_TMCFG0_NPRIBITS 0x003f0000
741 #define TMRN_TMCFG0_NPRIBITS_SHIFT 16
742 #define TMRN_TMCFG0_NATHRD 0x00003f00
743 #define TMRN_TMCFG0_NATHRD_SHIFT 8
744 #define TMRN_TMCFG0_NTHRD 0x0000003f
745 #define TMRN_IMSR0 0x120
746 #define TMRN_IMSR1 0x121
747 #define TMRN_INIA0 0x140
748 #define TMRN_INIA1 0x141
749 #define SPRN_TENSR 0x1b5
750 #define SPRN_TENS 0x1b6
751 #define SPRN_TENC 0x1b7
752
753 #define TEN_THREAD(x) (1 << (x))
754
755 #ifndef __ASSEMBLY__
756 #define mftmr(rn) ({unsigned long rval; \
757 asm volatile(MFTMR(rn, %0) : "=r" (rval)); rval;})
758 #define mttmr(rn, v) asm volatile(MTTMR(rn, %0) : \
759 : "r" ((unsigned long)(v)) \
760 : "memory")
761 #endif
762
763 #endif
764 #endif