1
2
3
4
5
6
7
8 #ifndef __OPAL_API_H
9 #define __OPAL_API_H
10
11
12
13
14 #define OPAL_SUCCESS 0
15 #define OPAL_PARAMETER -1
16 #define OPAL_BUSY -2
17 #define OPAL_PARTIAL -3
18 #define OPAL_CONSTRAINED -4
19 #define OPAL_CLOSED -5
20 #define OPAL_HARDWARE -6
21 #define OPAL_UNSUPPORTED -7
22 #define OPAL_PERMISSION -8
23 #define OPAL_NO_MEM -9
24 #define OPAL_RESOURCE -10
25 #define OPAL_INTERNAL_ERROR -11
26 #define OPAL_BUSY_EVENT -12
27 #define OPAL_HARDWARE_FROZEN -13
28 #define OPAL_WRONG_STATE -14
29 #define OPAL_ASYNC_COMPLETION -15
30 #define OPAL_EMPTY -16
31 #define OPAL_I2C_TIMEOUT -17
32 #define OPAL_I2C_INVALID_CMD -18
33 #define OPAL_I2C_LBUS_PARITY -19
34 #define OPAL_I2C_BKEND_OVERRUN -20
35 #define OPAL_I2C_BKEND_ACCESS -21
36 #define OPAL_I2C_ARBT_LOST -22
37 #define OPAL_I2C_NACK_RCVD -23
38 #define OPAL_I2C_STOP_ERR -24
39 #define OPAL_XIVE_PROVISIONING -31
40 #define OPAL_XIVE_FREE_ACTIVE -32
41 #define OPAL_TIMEOUT -33
42
43
44 #define OPAL_INVALID_CALL -1
45 #define OPAL_TEST 0
46 #define OPAL_CONSOLE_WRITE 1
47 #define OPAL_CONSOLE_READ 2
48 #define OPAL_RTC_READ 3
49 #define OPAL_RTC_WRITE 4
50 #define OPAL_CEC_POWER_DOWN 5
51 #define OPAL_CEC_REBOOT 6
52 #define OPAL_READ_NVRAM 7
53 #define OPAL_WRITE_NVRAM 8
54 #define OPAL_HANDLE_INTERRUPT 9
55 #define OPAL_POLL_EVENTS 10
56 #define OPAL_PCI_SET_HUB_TCE_MEMORY 11
57 #define OPAL_PCI_SET_PHB_TCE_MEMORY 12
58 #define OPAL_PCI_CONFIG_READ_BYTE 13
59 #define OPAL_PCI_CONFIG_READ_HALF_WORD 14
60 #define OPAL_PCI_CONFIG_READ_WORD 15
61 #define OPAL_PCI_CONFIG_WRITE_BYTE 16
62 #define OPAL_PCI_CONFIG_WRITE_HALF_WORD 17
63 #define OPAL_PCI_CONFIG_WRITE_WORD 18
64 #define OPAL_SET_XIVE 19
65 #define OPAL_GET_XIVE 20
66 #define OPAL_GET_COMPLETION_TOKEN_STATUS 21
67 #define OPAL_REGISTER_OPAL_EXCEPTION_HANDLER 22
68 #define OPAL_PCI_EEH_FREEZE_STATUS 23
69 #define OPAL_PCI_SHPC 24
70 #define OPAL_CONSOLE_WRITE_BUFFER_SPACE 25
71 #define OPAL_PCI_EEH_FREEZE_CLEAR 26
72 #define OPAL_PCI_PHB_MMIO_ENABLE 27
73 #define OPAL_PCI_SET_PHB_MEM_WINDOW 28
74 #define OPAL_PCI_MAP_PE_MMIO_WINDOW 29
75 #define OPAL_PCI_SET_PHB_TABLE_MEMORY 30
76 #define OPAL_PCI_SET_PE 31
77 #define OPAL_PCI_SET_PELTV 32
78 #define OPAL_PCI_SET_MVE 33
79 #define OPAL_PCI_SET_MVE_ENABLE 34
80 #define OPAL_PCI_GET_XIVE_REISSUE 35
81 #define OPAL_PCI_SET_XIVE_REISSUE 36
82 #define OPAL_PCI_SET_XIVE_PE 37
83 #define OPAL_GET_XIVE_SOURCE 38
84 #define OPAL_GET_MSI_32 39
85 #define OPAL_GET_MSI_64 40
86 #define OPAL_START_CPU 41
87 #define OPAL_QUERY_CPU_STATUS 42
88 #define OPAL_WRITE_OPPANEL 43
89 #define OPAL_PCI_MAP_PE_DMA_WINDOW 44
90 #define OPAL_PCI_MAP_PE_DMA_WINDOW_REAL 45
91 #define OPAL_PCI_RESET 49
92 #define OPAL_PCI_GET_HUB_DIAG_DATA 50
93 #define OPAL_PCI_GET_PHB_DIAG_DATA 51
94 #define OPAL_PCI_FENCE_PHB 52
95 #define OPAL_PCI_REINIT 53
96 #define OPAL_PCI_MASK_PE_ERROR 54
97 #define OPAL_SET_SLOT_LED_STATUS 55
98 #define OPAL_GET_EPOW_STATUS 56
99 #define OPAL_SET_SYSTEM_ATTENTION_LED 57
100 #define OPAL_RESERVED1 58
101 #define OPAL_RESERVED2 59
102 #define OPAL_PCI_NEXT_ERROR 60
103 #define OPAL_PCI_EEH_FREEZE_STATUS2 61
104 #define OPAL_PCI_POLL 62
105 #define OPAL_PCI_MSI_EOI 63
106 #define OPAL_PCI_GET_PHB_DIAG_DATA2 64
107 #define OPAL_XSCOM_READ 65
108 #define OPAL_XSCOM_WRITE 66
109 #define OPAL_LPC_READ 67
110 #define OPAL_LPC_WRITE 68
111 #define OPAL_RETURN_CPU 69
112 #define OPAL_REINIT_CPUS 70
113 #define OPAL_ELOG_READ 71
114 #define OPAL_ELOG_WRITE 72
115 #define OPAL_ELOG_ACK 73
116 #define OPAL_ELOG_RESEND 74
117 #define OPAL_ELOG_SIZE 75
118 #define OPAL_FLASH_VALIDATE 76
119 #define OPAL_FLASH_MANAGE 77
120 #define OPAL_FLASH_UPDATE 78
121 #define OPAL_RESYNC_TIMEBASE 79
122 #define OPAL_CHECK_TOKEN 80
123 #define OPAL_DUMP_INIT 81
124 #define OPAL_DUMP_INFO 82
125 #define OPAL_DUMP_READ 83
126 #define OPAL_DUMP_ACK 84
127 #define OPAL_GET_MSG 85
128 #define OPAL_CHECK_ASYNC_COMPLETION 86
129 #define OPAL_SYNC_HOST_REBOOT 87
130 #define OPAL_SENSOR_READ 88
131 #define OPAL_GET_PARAM 89
132 #define OPAL_SET_PARAM 90
133 #define OPAL_DUMP_RESEND 91
134 #define OPAL_ELOG_SEND 92
135 #define OPAL_PCI_SET_PHB_CAPI_MODE 93
136 #define OPAL_DUMP_INFO2 94
137 #define OPAL_WRITE_OPPANEL_ASYNC 95
138 #define OPAL_PCI_ERR_INJECT 96
139 #define OPAL_PCI_EEH_FREEZE_SET 97
140 #define OPAL_HANDLE_HMI 98
141 #define OPAL_CONFIG_CPU_IDLE_STATE 99
142 #define OPAL_SLW_SET_REG 100
143 #define OPAL_REGISTER_DUMP_REGION 101
144 #define OPAL_UNREGISTER_DUMP_REGION 102
145 #define OPAL_WRITE_TPO 103
146 #define OPAL_READ_TPO 104
147 #define OPAL_GET_DPO_STATUS 105
148 #define OPAL_OLD_I2C_REQUEST 106
149 #define OPAL_IPMI_SEND 107
150 #define OPAL_IPMI_RECV 108
151 #define OPAL_I2C_REQUEST 109
152 #define OPAL_FLASH_READ 110
153 #define OPAL_FLASH_WRITE 111
154 #define OPAL_FLASH_ERASE 112
155 #define OPAL_PRD_MSG 113
156 #define OPAL_LEDS_GET_INDICATOR 114
157 #define OPAL_LEDS_SET_INDICATOR 115
158 #define OPAL_CEC_REBOOT2 116
159 #define OPAL_CONSOLE_FLUSH 117
160 #define OPAL_GET_DEVICE_TREE 118
161 #define OPAL_PCI_GET_PRESENCE_STATE 119
162 #define OPAL_PCI_GET_POWER_STATE 120
163 #define OPAL_PCI_SET_POWER_STATE 121
164 #define OPAL_INT_GET_XIRR 122
165 #define OPAL_INT_SET_CPPR 123
166 #define OPAL_INT_EOI 124
167 #define OPAL_INT_SET_MFRR 125
168 #define OPAL_PCI_TCE_KILL 126
169 #define OPAL_NMMU_SET_PTCR 127
170 #define OPAL_XIVE_RESET 128
171 #define OPAL_XIVE_GET_IRQ_INFO 129
172 #define OPAL_XIVE_GET_IRQ_CONFIG 130
173 #define OPAL_XIVE_SET_IRQ_CONFIG 131
174 #define OPAL_XIVE_GET_QUEUE_INFO 132
175 #define OPAL_XIVE_SET_QUEUE_INFO 133
176 #define OPAL_XIVE_DONATE_PAGE 134
177 #define OPAL_XIVE_ALLOCATE_VP_BLOCK 135
178 #define OPAL_XIVE_FREE_VP_BLOCK 136
179 #define OPAL_XIVE_GET_VP_INFO 137
180 #define OPAL_XIVE_SET_VP_INFO 138
181 #define OPAL_XIVE_ALLOCATE_IRQ 139
182 #define OPAL_XIVE_FREE_IRQ 140
183 #define OPAL_XIVE_SYNC 141
184 #define OPAL_XIVE_DUMP 142
185 #define OPAL_XIVE_GET_QUEUE_STATE 143
186 #define OPAL_XIVE_SET_QUEUE_STATE 144
187 #define OPAL_SIGNAL_SYSTEM_RESET 145
188 #define OPAL_NPU_INIT_CONTEXT 146
189 #define OPAL_NPU_DESTROY_CONTEXT 147
190 #define OPAL_NPU_MAP_LPAR 148
191 #define OPAL_IMC_COUNTERS_INIT 149
192 #define OPAL_IMC_COUNTERS_START 150
193 #define OPAL_IMC_COUNTERS_STOP 151
194 #define OPAL_GET_POWERCAP 152
195 #define OPAL_SET_POWERCAP 153
196 #define OPAL_GET_POWER_SHIFT_RATIO 154
197 #define OPAL_SET_POWER_SHIFT_RATIO 155
198 #define OPAL_SENSOR_GROUP_CLEAR 156
199 #define OPAL_PCI_SET_P2P 157
200 #define OPAL_QUIESCE 158
201 #define OPAL_NPU_SPA_SETUP 159
202 #define OPAL_NPU_SPA_CLEAR_CACHE 160
203 #define OPAL_NPU_TL_SET 161
204 #define OPAL_SENSOR_READ_U64 162
205 #define OPAL_SENSOR_GROUP_ENABLE 163
206 #define OPAL_PCI_GET_PBCQ_TUNNEL_BAR 164
207 #define OPAL_PCI_SET_PBCQ_TUNNEL_BAR 165
208 #define OPAL_HANDLE_HMI2 166
209 #define OPAL_NX_COPROC_INIT 167
210 #define OPAL_XIVE_GET_VP_STATE 170
211 #define OPAL_MPIPL_UPDATE 173
212 #define OPAL_MPIPL_REGISTER_TAG 174
213 #define OPAL_MPIPL_QUERY_TAG 175
214 #define OPAL_LAST 175
215
216 #define QUIESCE_HOLD 1
217 #define QUIESCE_REJECT 2
218 #define QUIESCE_LOCK_BREAK 3
219 #define QUIESCE_RESUME 4
220 #define QUIESCE_RESUME_FAST_REBOOT 5
221
222
223
224
225
226
227
228
229 #define OPAL_PM_TIMEBASE_STOP 0x00000002
230 #define OPAL_PM_LOSE_HYP_CONTEXT 0x00002000
231 #define OPAL_PM_LOSE_FULL_CONTEXT 0x00004000
232 #define OPAL_PM_NAP_ENABLED 0x00010000
233 #define OPAL_PM_SLEEP_ENABLED 0x00020000
234 #define OPAL_PM_WINKLE_ENABLED 0x00040000
235 #define OPAL_PM_SLEEP_ENABLED_ER1 0x00080000
236 #define OPAL_PM_STOP_INST_FAST 0x00100000
237 #define OPAL_PM_STOP_INST_DEEP 0x00200000
238
239
240
241
242 #define OPAL_CONFIG_IDLE_FASTSLEEP 1
243 #define OPAL_CONFIG_IDLE_UNDO 0
244 #define OPAL_CONFIG_IDLE_APPLY 1
245
246 #ifndef __ASSEMBLY__
247
248
249 enum OpalFreezeState {
250 OPAL_EEH_STOPPED_NOT_FROZEN = 0,
251 OPAL_EEH_STOPPED_MMIO_FREEZE = 1,
252 OPAL_EEH_STOPPED_DMA_FREEZE = 2,
253 OPAL_EEH_STOPPED_MMIO_DMA_FREEZE = 3,
254 OPAL_EEH_STOPPED_RESET = 4,
255 OPAL_EEH_STOPPED_TEMP_UNAVAIL = 5,
256 OPAL_EEH_STOPPED_PERM_UNAVAIL = 6
257 };
258
259 enum OpalEehFreezeActionToken {
260 OPAL_EEH_ACTION_CLEAR_FREEZE_MMIO = 1,
261 OPAL_EEH_ACTION_CLEAR_FREEZE_DMA = 2,
262 OPAL_EEH_ACTION_CLEAR_FREEZE_ALL = 3,
263
264 OPAL_EEH_ACTION_SET_FREEZE_MMIO = 1,
265 OPAL_EEH_ACTION_SET_FREEZE_DMA = 2,
266 OPAL_EEH_ACTION_SET_FREEZE_ALL = 3
267 };
268
269 enum OpalPciStatusToken {
270 OPAL_EEH_NO_ERROR = 0,
271 OPAL_EEH_IOC_ERROR = 1,
272 OPAL_EEH_PHB_ERROR = 2,
273 OPAL_EEH_PE_ERROR = 3,
274 OPAL_EEH_PE_MMIO_ERROR = 4,
275 OPAL_EEH_PE_DMA_ERROR = 5
276 };
277
278 enum OpalPciErrorSeverity {
279 OPAL_EEH_SEV_NO_ERROR = 0,
280 OPAL_EEH_SEV_IOC_DEAD = 1,
281 OPAL_EEH_SEV_PHB_DEAD = 2,
282 OPAL_EEH_SEV_PHB_FENCED = 3,
283 OPAL_EEH_SEV_PE_ER = 4,
284 OPAL_EEH_SEV_INF = 5
285 };
286
287 enum OpalErrinjectType {
288 OPAL_ERR_INJECT_TYPE_IOA_BUS_ERR = 0,
289 OPAL_ERR_INJECT_TYPE_IOA_BUS_ERR64 = 1,
290 };
291
292 enum OpalErrinjectFunc {
293
294 OPAL_ERR_INJECT_FUNC_IOA_LD_MEM_ADDR = 0,
295 OPAL_ERR_INJECT_FUNC_IOA_LD_MEM_DATA = 1,
296 OPAL_ERR_INJECT_FUNC_IOA_LD_IO_ADDR = 2,
297 OPAL_ERR_INJECT_FUNC_IOA_LD_IO_DATA = 3,
298 OPAL_ERR_INJECT_FUNC_IOA_LD_CFG_ADDR = 4,
299 OPAL_ERR_INJECT_FUNC_IOA_LD_CFG_DATA = 5,
300 OPAL_ERR_INJECT_FUNC_IOA_ST_MEM_ADDR = 6,
301 OPAL_ERR_INJECT_FUNC_IOA_ST_MEM_DATA = 7,
302 OPAL_ERR_INJECT_FUNC_IOA_ST_IO_ADDR = 8,
303 OPAL_ERR_INJECT_FUNC_IOA_ST_IO_DATA = 9,
304 OPAL_ERR_INJECT_FUNC_IOA_ST_CFG_ADDR = 10,
305 OPAL_ERR_INJECT_FUNC_IOA_ST_CFG_DATA = 11,
306 OPAL_ERR_INJECT_FUNC_IOA_DMA_RD_ADDR = 12,
307 OPAL_ERR_INJECT_FUNC_IOA_DMA_RD_DATA = 13,
308 OPAL_ERR_INJECT_FUNC_IOA_DMA_RD_MASTER = 14,
309 OPAL_ERR_INJECT_FUNC_IOA_DMA_RD_TARGET = 15,
310 OPAL_ERR_INJECT_FUNC_IOA_DMA_WR_ADDR = 16,
311 OPAL_ERR_INJECT_FUNC_IOA_DMA_WR_DATA = 17,
312 OPAL_ERR_INJECT_FUNC_IOA_DMA_WR_MASTER = 18,
313 OPAL_ERR_INJECT_FUNC_IOA_DMA_WR_TARGET = 19,
314 };
315
316 enum OpalMmioWindowType {
317 OPAL_M32_WINDOW_TYPE = 1,
318 OPAL_M64_WINDOW_TYPE = 2,
319 OPAL_IO_WINDOW_TYPE = 3
320 };
321
322 enum OpalExceptionHandler {
323 OPAL_MACHINE_CHECK_HANDLER = 1,
324 OPAL_HYPERVISOR_MAINTENANCE_HANDLER = 2,
325 OPAL_SOFTPATCH_HANDLER = 3
326 };
327
328 enum OpalPendingState {
329 OPAL_EVENT_OPAL_INTERNAL = 0x1,
330 OPAL_EVENT_NVRAM = 0x2,
331 OPAL_EVENT_RTC = 0x4,
332 OPAL_EVENT_CONSOLE_OUTPUT = 0x8,
333 OPAL_EVENT_CONSOLE_INPUT = 0x10,
334 OPAL_EVENT_ERROR_LOG_AVAIL = 0x20,
335 OPAL_EVENT_ERROR_LOG = 0x40,
336 OPAL_EVENT_EPOW = 0x80,
337 OPAL_EVENT_LED_STATUS = 0x100,
338 OPAL_EVENT_PCI_ERROR = 0x200,
339 OPAL_EVENT_DUMP_AVAIL = 0x400,
340 OPAL_EVENT_MSG_PENDING = 0x800,
341 };
342
343 enum OpalThreadStatus {
344 OPAL_THREAD_INACTIVE = 0x0,
345 OPAL_THREAD_STARTED = 0x1,
346 OPAL_THREAD_UNAVAILABLE = 0x2
347 };
348
349 enum OpalPciBusCompare {
350 OpalPciBusAny = 0,
351 OpalPciBus3Bits = 2,
352 OpalPciBus4Bits = 3,
353 OpalPciBus5Bits = 4,
354 OpalPciBus6Bits = 5,
355 OpalPciBus7Bits = 6,
356 OpalPciBusAll = 7,
357 };
358
359 enum OpalDeviceCompare {
360 OPAL_IGNORE_RID_DEVICE_NUMBER = 0,
361 OPAL_COMPARE_RID_DEVICE_NUMBER = 1
362 };
363
364 enum OpalFuncCompare {
365 OPAL_IGNORE_RID_FUNCTION_NUMBER = 0,
366 OPAL_COMPARE_RID_FUNCTION_NUMBER = 1
367 };
368
369 enum OpalPeAction {
370 OPAL_UNMAP_PE = 0,
371 OPAL_MAP_PE = 1
372 };
373
374 enum OpalPeltvAction {
375 OPAL_REMOVE_PE_FROM_DOMAIN = 0,
376 OPAL_ADD_PE_TO_DOMAIN = 1
377 };
378
379 enum OpalMveEnableAction {
380 OPAL_DISABLE_MVE = 0,
381 OPAL_ENABLE_MVE = 1
382 };
383
384 enum OpalM64Action {
385 OPAL_DISABLE_M64 = 0,
386 OPAL_ENABLE_M64_SPLIT = 1,
387 OPAL_ENABLE_M64_NON_SPLIT = 2
388 };
389
390 enum OpalPciResetScope {
391 OPAL_RESET_PHB_COMPLETE = 1,
392 OPAL_RESET_PCI_LINK = 2,
393 OPAL_RESET_PHB_ERROR = 3,
394 OPAL_RESET_PCI_HOT = 4,
395 OPAL_RESET_PCI_FUNDAMENTAL = 5,
396 OPAL_RESET_PCI_IODA_TABLE = 6
397 };
398
399 enum OpalPciReinitScope {
400
401
402
403
404
405 OPAL_REINIT_PCI_DEV = 1000
406 };
407
408 enum OpalPciResetState {
409 OPAL_DEASSERT_RESET = 0,
410 OPAL_ASSERT_RESET = 1
411 };
412
413 enum OpalPciSlotPresence {
414 OPAL_PCI_SLOT_EMPTY = 0,
415 OPAL_PCI_SLOT_PRESENT = 1
416 };
417
418 enum OpalPciSlotPower {
419 OPAL_PCI_SLOT_POWER_OFF = 0,
420 OPAL_PCI_SLOT_POWER_ON = 1,
421 OPAL_PCI_SLOT_OFFLINE = 2,
422 OPAL_PCI_SLOT_ONLINE = 3
423 };
424
425 enum OpalSlotLedType {
426 OPAL_SLOT_LED_TYPE_ID = 0,
427 OPAL_SLOT_LED_TYPE_FAULT = 1,
428 OPAL_SLOT_LED_TYPE_ATTN = 2,
429 OPAL_SLOT_LED_TYPE_MAX = 3
430 };
431
432 enum OpalSlotLedState {
433 OPAL_SLOT_LED_STATE_OFF = 0,
434 OPAL_SLOT_LED_STATE_ON = 1
435 };
436
437
438
439
440
441
442 enum OpalLPCAddressType {
443 OPAL_LPC_MEM = 0,
444 OPAL_LPC_IO = 1,
445 OPAL_LPC_FW = 2,
446 };
447
448 enum opal_msg_type {
449 OPAL_MSG_ASYNC_COMP = 0,
450
451
452 OPAL_MSG_MEM_ERR = 1,
453 OPAL_MSG_EPOW = 2,
454 OPAL_MSG_SHUTDOWN = 3,
455 OPAL_MSG_HMI_EVT = 4,
456 OPAL_MSG_DPO = 5,
457 OPAL_MSG_PRD = 6,
458 OPAL_MSG_OCC = 7,
459 OPAL_MSG_PRD2 = 8,
460 OPAL_MSG_TYPE_MAX,
461 };
462
463 struct opal_msg {
464 __be32 msg_type;
465 __be32 reserved;
466 __be64 params[8];
467 };
468
469
470 enum OpalSysparamPerm {
471 OPAL_SYSPARAM_READ = 0x1,
472 OPAL_SYSPARAM_WRITE = 0x2,
473 OPAL_SYSPARAM_RW = (OPAL_SYSPARAM_READ | OPAL_SYSPARAM_WRITE),
474 };
475
476 enum {
477 OPAL_IPMI_MSG_FORMAT_VERSION_1 = 1,
478 };
479
480 struct opal_ipmi_msg {
481 uint8_t version;
482 uint8_t netfn;
483 uint8_t cmd;
484 uint8_t data[];
485 };
486
487
488 enum OpalMemErr_Version {
489 OpalMemErr_V1 = 1,
490 };
491
492 enum OpalMemErrType {
493 OPAL_MEM_ERR_TYPE_RESILIENCE = 0,
494 OPAL_MEM_ERR_TYPE_DYN_DALLOC,
495 };
496
497
498 enum OpalMemErr_ResilErrType {
499 OPAL_MEM_RESILIENCE_CE = 0,
500 OPAL_MEM_RESILIENCE_UE,
501 OPAL_MEM_RESILIENCE_UE_SCRUB,
502 };
503
504
505 enum OpalMemErr_DynErrType {
506 OPAL_MEM_DYNAMIC_DEALLOC = 0,
507 };
508
509 struct OpalMemoryErrorData {
510 enum OpalMemErr_Version version:8;
511 enum OpalMemErrType type:8;
512 __be16 flags;
513 uint8_t reserved_1[4];
514
515 union {
516
517 struct {
518 enum OpalMemErr_ResilErrType resil_err_type:8;
519 uint8_t reserved_1[7];
520 __be64 physical_address_start;
521 __be64 physical_address_end;
522 } resilience;
523
524 struct {
525 enum OpalMemErr_DynErrType dyn_err_type:8;
526 uint8_t reserved_1[7];
527 __be64 physical_address_start;
528 __be64 physical_address_end;
529 } dyn_dealloc;
530 } u;
531 };
532
533
534 enum OpalHMI_Version {
535 OpalHMIEvt_V1 = 1,
536 OpalHMIEvt_V2 = 2,
537 };
538
539 enum OpalHMI_Severity {
540 OpalHMI_SEV_NO_ERROR = 0,
541 OpalHMI_SEV_WARNING = 1,
542 OpalHMI_SEV_ERROR_SYNC = 2,
543 OpalHMI_SEV_FATAL = 3,
544 };
545
546 enum OpalHMI_Disposition {
547 OpalHMI_DISPOSITION_RECOVERED = 0,
548 OpalHMI_DISPOSITION_NOT_RECOVERED = 1,
549 };
550
551 enum OpalHMI_ErrType {
552 OpalHMI_ERROR_MALFUNC_ALERT = 0,
553 OpalHMI_ERROR_PROC_RECOV_DONE,
554 OpalHMI_ERROR_PROC_RECOV_DONE_AGAIN,
555 OpalHMI_ERROR_PROC_RECOV_MASKED,
556 OpalHMI_ERROR_TFAC,
557 OpalHMI_ERROR_TFMR_PARITY,
558 OpalHMI_ERROR_HA_OVERFLOW_WARN,
559 OpalHMI_ERROR_XSCOM_FAIL,
560 OpalHMI_ERROR_XSCOM_DONE,
561 OpalHMI_ERROR_SCOM_FIR,
562 OpalHMI_ERROR_DEBUG_TRIG_FIR,
563 OpalHMI_ERROR_HYP_RESOURCE,
564 OpalHMI_ERROR_CAPP_RECOVERY,
565 };
566
567 enum OpalHMI_XstopType {
568 CHECKSTOP_TYPE_UNKNOWN = 0,
569 CHECKSTOP_TYPE_CORE = 1,
570 CHECKSTOP_TYPE_NX = 2,
571 CHECKSTOP_TYPE_NPU = 3
572 };
573
574 enum OpalHMI_CoreXstopReason {
575 CORE_CHECKSTOP_IFU_REGFILE = 0x00000001,
576 CORE_CHECKSTOP_IFU_LOGIC = 0x00000002,
577 CORE_CHECKSTOP_PC_DURING_RECOV = 0x00000004,
578 CORE_CHECKSTOP_ISU_REGFILE = 0x00000008,
579 CORE_CHECKSTOP_ISU_LOGIC = 0x00000010,
580 CORE_CHECKSTOP_FXU_LOGIC = 0x00000020,
581 CORE_CHECKSTOP_VSU_LOGIC = 0x00000040,
582 CORE_CHECKSTOP_PC_RECOV_IN_MAINT_MODE = 0x00000080,
583 CORE_CHECKSTOP_LSU_REGFILE = 0x00000100,
584 CORE_CHECKSTOP_PC_FWD_PROGRESS = 0x00000200,
585 CORE_CHECKSTOP_LSU_LOGIC = 0x00000400,
586 CORE_CHECKSTOP_PC_LOGIC = 0x00000800,
587 CORE_CHECKSTOP_PC_HYP_RESOURCE = 0x00001000,
588 CORE_CHECKSTOP_PC_HANG_RECOV_FAILED = 0x00002000,
589 CORE_CHECKSTOP_PC_AMBI_HANG_DETECTED = 0x00004000,
590 CORE_CHECKSTOP_PC_DEBUG_TRIG_ERR_INJ = 0x00008000,
591 CORE_CHECKSTOP_PC_SPRD_HYP_ERR_INJ = 0x00010000,
592 };
593
594 enum OpalHMI_NestAccelXstopReason {
595 NX_CHECKSTOP_SHM_INVAL_STATE_ERR = 0x00000001,
596 NX_CHECKSTOP_DMA_INVAL_STATE_ERR_1 = 0x00000002,
597 NX_CHECKSTOP_DMA_INVAL_STATE_ERR_2 = 0x00000004,
598 NX_CHECKSTOP_DMA_CH0_INVAL_STATE_ERR = 0x00000008,
599 NX_CHECKSTOP_DMA_CH1_INVAL_STATE_ERR = 0x00000010,
600 NX_CHECKSTOP_DMA_CH2_INVAL_STATE_ERR = 0x00000020,
601 NX_CHECKSTOP_DMA_CH3_INVAL_STATE_ERR = 0x00000040,
602 NX_CHECKSTOP_DMA_CH4_INVAL_STATE_ERR = 0x00000080,
603 NX_CHECKSTOP_DMA_CH5_INVAL_STATE_ERR = 0x00000100,
604 NX_CHECKSTOP_DMA_CH6_INVAL_STATE_ERR = 0x00000200,
605 NX_CHECKSTOP_DMA_CH7_INVAL_STATE_ERR = 0x00000400,
606 NX_CHECKSTOP_DMA_CRB_UE = 0x00000800,
607 NX_CHECKSTOP_DMA_CRB_SUE = 0x00001000,
608 NX_CHECKSTOP_PBI_ISN_UE = 0x00002000,
609 };
610
611 struct OpalHMIEvent {
612 uint8_t version;
613 uint8_t severity;
614 uint8_t type;
615 uint8_t disposition;
616 uint8_t reserved_1[4];
617
618 __be64 hmer;
619
620 __be64 tfmr;
621
622
623 union {
624
625
626
627
628 struct {
629 uint8_t xstop_type;
630 uint8_t reserved_1[3];
631 __be32 xstop_reason;
632 union {
633 __be32 pir;
634 __be32 chip_id;
635 } u;
636 } xstop_error;
637 } u;
638 };
639
640
641 enum {
642 OPAL_HMI_FLAGS_TB_RESYNC = (1ull << 0),
643 OPAL_HMI_FLAGS_DEC_LOST = (1ull << 1),
644 OPAL_HMI_FLAGS_HDEC_LOST = (1ull << 2),
645 OPAL_HMI_FLAGS_TOD_TB_FAIL = (1ull << 3),
646 OPAL_HMI_FLAGS_NEW_EVENT = (1ull << 63),
647 };
648
649 enum {
650 OPAL_P7IOC_DIAG_TYPE_NONE = 0,
651 OPAL_P7IOC_DIAG_TYPE_RGC = 1,
652 OPAL_P7IOC_DIAG_TYPE_BI = 2,
653 OPAL_P7IOC_DIAG_TYPE_CI = 3,
654 OPAL_P7IOC_DIAG_TYPE_MISC = 4,
655 OPAL_P7IOC_DIAG_TYPE_I2C = 5,
656 OPAL_P7IOC_DIAG_TYPE_LAST = 6
657 };
658
659 struct OpalIoP7IOCErrorData {
660 __be16 type;
661
662
663 __be64 gemXfir;
664 __be64 gemRfir;
665 __be64 gemRirqfir;
666 __be64 gemMask;
667 __be64 gemRwof;
668
669
670 __be64 lemFir;
671 __be64 lemErrMask;
672 __be64 lemAction0;
673 __be64 lemAction1;
674 __be64 lemWof;
675
676 union {
677 struct OpalIoP7IOCRgcErrorData {
678 __be64 rgcStatus;
679 __be64 rgcLdcp;
680 }rgc;
681 struct OpalIoP7IOCBiErrorData {
682 __be64 biLdcp0;
683 __be64 biLdcp1;
684 __be64 biLdcp2;
685 __be64 biFenceStatus;
686
687 uint8_t biDownbound;
688 }bi;
689 struct OpalIoP7IOCCiErrorData {
690 __be64 ciPortStatus;
691 __be64 ciPortLdcp;
692
693 uint8_t ciPort;
694 }ci;
695 };
696 };
697
698
699
700
701
702 enum {
703 OPAL_PHB_ERROR_DATA_VERSION_1 = 1,
704 };
705
706 enum {
707 OPAL_PHB_ERROR_DATA_TYPE_P7IOC = 1,
708 OPAL_PHB_ERROR_DATA_TYPE_PHB3 = 2,
709 OPAL_PHB_ERROR_DATA_TYPE_PHB4 = 3
710 };
711
712 enum {
713 OPAL_P7IOC_NUM_PEST_REGS = 128,
714 OPAL_PHB3_NUM_PEST_REGS = 256,
715 OPAL_PHB4_NUM_PEST_REGS = 512
716 };
717
718 struct OpalIoPhbErrorCommon {
719 __be32 version;
720 __be32 ioType;
721 __be32 len;
722 };
723
724 struct OpalIoP7IOCPhbErrorData {
725 struct OpalIoPhbErrorCommon common;
726
727 __be32 brdgCtl;
728
729
730 __be32 portStatusReg;
731 __be32 rootCmplxStatus;
732 __be32 busAgentStatus;
733
734
735 __be32 deviceStatus;
736 __be32 slotStatus;
737 __be32 linkStatus;
738 __be32 devCmdStatus;
739 __be32 devSecStatus;
740
741
742 __be32 rootErrorStatus;
743 __be32 uncorrErrorStatus;
744 __be32 corrErrorStatus;
745 __be32 tlpHdr1;
746 __be32 tlpHdr2;
747 __be32 tlpHdr3;
748 __be32 tlpHdr4;
749 __be32 sourceId;
750
751 __be32 rsv3;
752
753
754 __be64 errorClass;
755 __be64 correlator;
756
757
758 __be64 p7iocPlssr;
759 __be64 p7iocCsr;
760 __be64 lemFir;
761 __be64 lemErrorMask;
762 __be64 lemWOF;
763 __be64 phbErrorStatus;
764 __be64 phbFirstErrorStatus;
765 __be64 phbErrorLog0;
766 __be64 phbErrorLog1;
767 __be64 mmioErrorStatus;
768 __be64 mmioFirstErrorStatus;
769 __be64 mmioErrorLog0;
770 __be64 mmioErrorLog1;
771 __be64 dma0ErrorStatus;
772 __be64 dma0FirstErrorStatus;
773 __be64 dma0ErrorLog0;
774 __be64 dma0ErrorLog1;
775 __be64 dma1ErrorStatus;
776 __be64 dma1FirstErrorStatus;
777 __be64 dma1ErrorLog0;
778 __be64 dma1ErrorLog1;
779 __be64 pestA[OPAL_P7IOC_NUM_PEST_REGS];
780 __be64 pestB[OPAL_P7IOC_NUM_PEST_REGS];
781 };
782
783 struct OpalIoPhb3ErrorData {
784 struct OpalIoPhbErrorCommon common;
785
786 __be32 brdgCtl;
787
788
789 __be32 portStatusReg;
790 __be32 rootCmplxStatus;
791 __be32 busAgentStatus;
792
793
794 __be32 deviceStatus;
795 __be32 slotStatus;
796 __be32 linkStatus;
797 __be32 devCmdStatus;
798 __be32 devSecStatus;
799
800
801 __be32 rootErrorStatus;
802 __be32 uncorrErrorStatus;
803 __be32 corrErrorStatus;
804 __be32 tlpHdr1;
805 __be32 tlpHdr2;
806 __be32 tlpHdr3;
807 __be32 tlpHdr4;
808 __be32 sourceId;
809
810 __be32 rsv3;
811
812
813 __be64 errorClass;
814 __be64 correlator;
815
816
817 __be64 nFir;
818 __be64 nFirMask;
819 __be64 nFirWOF;
820 __be64 phbPlssr;
821 __be64 phbCsr;
822 __be64 lemFir;
823 __be64 lemErrorMask;
824 __be64 lemWOF;
825 __be64 phbErrorStatus;
826 __be64 phbFirstErrorStatus;
827 __be64 phbErrorLog0;
828 __be64 phbErrorLog1;
829 __be64 mmioErrorStatus;
830 __be64 mmioFirstErrorStatus;
831 __be64 mmioErrorLog0;
832 __be64 mmioErrorLog1;
833 __be64 dma0ErrorStatus;
834 __be64 dma0FirstErrorStatus;
835 __be64 dma0ErrorLog0;
836 __be64 dma0ErrorLog1;
837 __be64 dma1ErrorStatus;
838 __be64 dma1FirstErrorStatus;
839 __be64 dma1ErrorLog0;
840 __be64 dma1ErrorLog1;
841 __be64 pestA[OPAL_PHB3_NUM_PEST_REGS];
842 __be64 pestB[OPAL_PHB3_NUM_PEST_REGS];
843 };
844
845 struct OpalIoPhb4ErrorData {
846 struct OpalIoPhbErrorCommon common;
847
848 __be32 brdgCtl;
849
850
851 __be32 deviceStatus;
852 __be32 slotStatus;
853 __be32 linkStatus;
854 __be32 devCmdStatus;
855 __be32 devSecStatus;
856
857
858 __be32 rootErrorStatus;
859 __be32 uncorrErrorStatus;
860 __be32 corrErrorStatus;
861 __be32 tlpHdr1;
862 __be32 tlpHdr2;
863 __be32 tlpHdr3;
864 __be32 tlpHdr4;
865 __be32 sourceId;
866
867
868 __be64 nFir;
869 __be64 nFirMask;
870 __be64 nFirWOF;
871 __be64 phbPlssr;
872 __be64 phbCsr;
873 __be64 lemFir;
874 __be64 lemErrorMask;
875 __be64 lemWOF;
876 __be64 phbErrorStatus;
877 __be64 phbFirstErrorStatus;
878 __be64 phbErrorLog0;
879 __be64 phbErrorLog1;
880 __be64 phbTxeErrorStatus;
881 __be64 phbTxeFirstErrorStatus;
882 __be64 phbTxeErrorLog0;
883 __be64 phbTxeErrorLog1;
884 __be64 phbRxeArbErrorStatus;
885 __be64 phbRxeArbFirstErrorStatus;
886 __be64 phbRxeArbErrorLog0;
887 __be64 phbRxeArbErrorLog1;
888 __be64 phbRxeMrgErrorStatus;
889 __be64 phbRxeMrgFirstErrorStatus;
890 __be64 phbRxeMrgErrorLog0;
891 __be64 phbRxeMrgErrorLog1;
892 __be64 phbRxeTceErrorStatus;
893 __be64 phbRxeTceFirstErrorStatus;
894 __be64 phbRxeTceErrorLog0;
895 __be64 phbRxeTceErrorLog1;
896
897
898 __be64 phbPblErrorStatus;
899 __be64 phbPblFirstErrorStatus;
900 __be64 phbPblErrorLog0;
901 __be64 phbPblErrorLog1;
902 __be64 phbPcieDlpErrorLog1;
903 __be64 phbPcieDlpErrorLog2;
904 __be64 phbPcieDlpErrorStatus;
905 __be64 phbRegbErrorStatus;
906 __be64 phbRegbFirstErrorStatus;
907 __be64 phbRegbErrorLog0;
908 __be64 phbRegbErrorLog1;
909
910 __be64 pestA[OPAL_PHB4_NUM_PEST_REGS];
911 __be64 pestB[OPAL_PHB4_NUM_PEST_REGS];
912 };
913
914 enum {
915 OPAL_REINIT_CPUS_HILE_BE = (1 << 0),
916 OPAL_REINIT_CPUS_HILE_LE = (1 << 1),
917
918
919
920
921
922
923
924 OPAL_REINIT_CPUS_MMU_HASH = (1 << 2),
925 OPAL_REINIT_CPUS_MMU_RADIX = (1 << 3),
926
927 OPAL_REINIT_CPUS_TM_SUSPEND_DISABLED = (1 << 4),
928 };
929
930 typedef struct oppanel_line {
931 __be64 line;
932 __be64 line_len;
933 } oppanel_line_t;
934
935 enum opal_prd_msg_type {
936 OPAL_PRD_MSG_TYPE_INIT = 0,
937 OPAL_PRD_MSG_TYPE_FINI,
938 OPAL_PRD_MSG_TYPE_ATTN,
939 OPAL_PRD_MSG_TYPE_ATTN_ACK,
940 OPAL_PRD_MSG_TYPE_OCC_ERROR,
941 OPAL_PRD_MSG_TYPE_OCC_RESET,
942 };
943
944 struct opal_prd_msg_header {
945 uint8_t type;
946 uint8_t pad[1];
947 __be16 size;
948 };
949
950 struct opal_prd_msg;
951
952 #define OCC_RESET 0
953 #define OCC_LOAD 1
954 #define OCC_THROTTLE 2
955 #define OCC_MAX_THROTTLE_STATUS 5
956
957 struct opal_occ_msg {
958 __be64 type;
959 __be64 chip;
960 __be64 throttle_status;
961 };
962
963
964
965
966
967
968
969
970 struct opal_sg_entry {
971 __be64 data;
972 __be64 length;
973 };
974
975
976
977
978
979
980 struct opal_sg_list {
981 __be64 length;
982 __be64 next;
983 struct opal_sg_entry entry[];
984 };
985
986
987
988
989 #define OPAL_DUMP_REGION_HOST_START 0x80
990 #define OPAL_DUMP_REGION_LOG_BUF 0x80
991 #define OPAL_DUMP_REGION_HOST_END 0xFF
992
993
994 enum {
995 OPAL_PHB_CAPI_MODE_PCIE = 0,
996 OPAL_PHB_CAPI_MODE_CAPI = 1,
997 OPAL_PHB_CAPI_MODE_SNOOP_OFF = 2,
998 OPAL_PHB_CAPI_MODE_SNOOP_ON = 3,
999 OPAL_PHB_CAPI_MODE_DMA = 4,
1000 OPAL_PHB_CAPI_MODE_DMA_TVT1 = 5,
1001 };
1002
1003
1004 struct opal_i2c_request {
1005 uint8_t type;
1006 #define OPAL_I2C_RAW_READ 0
1007 #define OPAL_I2C_RAW_WRITE 1
1008 #define OPAL_I2C_SM_READ 2
1009 #define OPAL_I2C_SM_WRITE 3
1010 uint8_t flags;
1011 #define OPAL_I2C_ADDR_10 0x01
1012 uint8_t subaddr_sz;
1013 uint8_t reserved;
1014 __be16 addr;
1015 __be16 reserved2;
1016 __be32 subaddr;
1017 __be32 size;
1018 __be64 buffer_ra;
1019 };
1020
1021
1022
1023
1024
1025
1026
1027
1028
1029
1030
1031
1032
1033
1034 enum OpalSysEpow {
1035 OPAL_SYSEPOW_POWER = 0,
1036 OPAL_SYSEPOW_TEMP = 1,
1037 OPAL_SYSEPOW_COOLING = 2,
1038 OPAL_SYSEPOW_MAX = 3,
1039 };
1040
1041
1042 enum OpalSysPower {
1043 OPAL_SYSPOWER_UPS = 0x0001,
1044 OPAL_SYSPOWER_CHNG = 0x0002,
1045 OPAL_SYSPOWER_FAIL = 0x0004,
1046 OPAL_SYSPOWER_INCL = 0x0008,
1047 };
1048
1049
1050 enum OpalSysTemp {
1051 OPAL_SYSTEMP_AMB = 0x0001,
1052 OPAL_SYSTEMP_INT = 0x0002,
1053 OPAL_SYSTEMP_HMD = 0x0004,
1054 };
1055
1056
1057 enum OpalSysCooling {
1058 OPAL_SYSCOOL_INSF = 0x0001,
1059 };
1060
1061
1062 enum {
1063 OPAL_REBOOT_NORMAL = 0,
1064 OPAL_REBOOT_PLATFORM_ERROR = 1,
1065 OPAL_REBOOT_FULL_IPL = 2,
1066 OPAL_REBOOT_MPIPL = 3,
1067 };
1068
1069
1070 enum {
1071 OPAL_PCI_TCE_KILL_PAGES,
1072 OPAL_PCI_TCE_KILL_PE,
1073 OPAL_PCI_TCE_KILL_ALL,
1074 };
1075
1076
1077
1078
1079
1080 enum {
1081 OPAL_XIVE_MODE_EMU = 0,
1082 OPAL_XIVE_MODE_EXPL = 1,
1083 };
1084
1085
1086 enum {
1087 OPAL_XIVE_IRQ_TRIGGER_PAGE = 0x00000001,
1088 OPAL_XIVE_IRQ_STORE_EOI = 0x00000002,
1089 OPAL_XIVE_IRQ_LSI = 0x00000004,
1090 OPAL_XIVE_IRQ_SHIFT_BUG = 0x00000008,
1091 OPAL_XIVE_IRQ_MASK_VIA_FW = 0x00000010,
1092 OPAL_XIVE_IRQ_EOI_VIA_FW = 0x00000020,
1093 };
1094
1095
1096 enum {
1097 OPAL_XIVE_EQ_ENABLED = 0x00000001,
1098 OPAL_XIVE_EQ_ALWAYS_NOTIFY = 0x00000002,
1099 OPAL_XIVE_EQ_ESCALATE = 0x00000004,
1100 };
1101
1102
1103 enum {
1104 OPAL_XIVE_VP_ENABLED = 0x00000001,
1105 OPAL_XIVE_VP_SINGLE_ESCALATION = 0x00000002,
1106 };
1107
1108
1109 enum {
1110 OPAL_XIVE_ANY_CHIP = 0xffffffff,
1111 };
1112
1113
1114 enum {
1115
1116 XIVE_SYNC_EAS = 0x00000001,
1117 XIVE_SYNC_QUEUE = 0x00000002,
1118 };
1119
1120
1121 enum {
1122 XIVE_DUMP_TM_HYP = 0,
1123 XIVE_DUMP_TM_POOL = 1,
1124 XIVE_DUMP_TM_OS = 2,
1125 XIVE_DUMP_TM_USER = 3,
1126 XIVE_DUMP_VP = 4,
1127 XIVE_DUMP_EMU_STATE = 5,
1128 };
1129
1130
1131 enum {
1132 OPAL_IMC_COUNTERS_NEST = 1,
1133 OPAL_IMC_COUNTERS_CORE = 2,
1134 OPAL_IMC_COUNTERS_TRACE = 3,
1135 };
1136
1137
1138
1139 #define OPAL_PCI_P2P_ENABLE 0x1
1140 #define OPAL_PCI_P2P_LOAD 0x2
1141 #define OPAL_PCI_P2P_STORE 0x4
1142
1143
1144 enum opal_mpipl_ops {
1145 OPAL_MPIPL_ADD_RANGE = 0,
1146 OPAL_MPIPL_REMOVE_RANGE = 1,
1147 OPAL_MPIPL_REMOVE_ALL = 2,
1148 OPAL_MPIPL_FREE_PRESERVED_MEMORY = 3,
1149 };
1150
1151
1152
1153
1154 enum opal_mpipl_tags {
1155 OPAL_MPIPL_TAG_CPU = 0,
1156 OPAL_MPIPL_TAG_OPAL = 1,
1157 OPAL_MPIPL_TAG_KERNEL = 2,
1158 OPAL_MPIPL_TAG_BOOT_MEM = 3,
1159 };
1160
1161
1162 struct opal_mpipl_region {
1163 __be64 src;
1164 __be64 dest;
1165 __be64 size;
1166 };
1167
1168
1169 #define OPAL_MPIPL_VERSION 0x01
1170
1171 struct opal_mpipl_fadump {
1172 u8 version;
1173 u8 reserved[7];
1174 __be32 crashing_pir;
1175 __be32 cpu_data_version;
1176 __be32 cpu_data_size;
1177 __be32 region_cnt;
1178 struct opal_mpipl_region region[];
1179 } __packed;
1180
1181 #endif
1182
1183 #endif