1
2 #ifndef _ASM_POWERPC_BOOK3S_32_MMU_HASH_H_
3 #define _ASM_POWERPC_BOOK3S_32_MMU_HASH_H_
4
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11
12
13
14 #define BL_128K 0x000
15 #define BL_256K 0x001
16 #define BL_512K 0x003
17 #define BL_1M 0x007
18 #define BL_2M 0x00F
19 #define BL_4M 0x01F
20 #define BL_8M 0x03F
21 #define BL_16M 0x07F
22 #define BL_32M 0x0FF
23 #define BL_64M 0x1FF
24 #define BL_128M 0x3FF
25 #define BL_256M 0x7FF
26
27
28 #define BPP_XX 0x00
29 #define BPP_RX 0x01
30 #define BPP_RW 0x02
31
32 #ifndef __ASSEMBLY__
33
34 #ifdef CONFIG_PHYS_64BIT
35 #define BAT_PHYS_ADDR(x) ((u32)((x & 0x00000000fffe0000ULL) | \
36 ((x & 0x0000000e00000000ULL) >> 24) | \
37 ((x & 0x0000000100000000ULL) >> 30)))
38 #define PHYS_BAT_ADDR(x) (((u64)(x) & 0x00000000fffe0000ULL) | \
39 (((u64)(x) << 24) & 0x0000000e00000000ULL) | \
40 (((u64)(x) << 30) & 0x0000000100000000ULL))
41 #else
42 #define BAT_PHYS_ADDR(x) (x)
43 #define PHYS_BAT_ADDR(x) ((x) & 0xfffe0000)
44 #endif
45
46 struct ppc_bat {
47 u32 batu;
48 u32 batl;
49 };
50 #endif
51
52
53
54
55
56
57 #define PP_RWXX 0
58 #define PP_RWRX 1
59 #define PP_RWRW 2
60 #define PP_RXRX 3
61
62
63 #define SR_NX 0x10000000
64 #define SR_KP 0x20000000
65 #define SR_KS 0x40000000
66
67 #ifndef __ASSEMBLY__
68
69
70
71
72
73
74 struct hash_pte {
75 unsigned long v:1;
76 unsigned long vsid:24;
77 unsigned long h:1;
78 unsigned long api:6;
79 unsigned long rpn:20;
80 unsigned long xpn:3;
81 unsigned long r:1;
82 unsigned long c:1;
83 unsigned long w:1;
84 unsigned long i:1;
85 unsigned long m:1;
86 unsigned long g:1;
87 unsigned long x:1;
88 unsigned long pp:2;
89 };
90
91 typedef struct {
92 unsigned long id;
93 unsigned long vdso_base;
94 } mm_context_t;
95
96 void update_bats(void);
97
98
99 extern s32 patch__hash_page_A0, patch__hash_page_A1, patch__hash_page_A2;
100 extern s32 patch__hash_page_B, patch__hash_page_C;
101 extern s32 patch__flush_hash_A0, patch__flush_hash_A1, patch__flush_hash_A2;
102 extern s32 patch__flush_hash_B;
103
104 #endif
105
106
107
108
109 #define mmu_virtual_psize MMU_PAGE_4K
110 #define mmu_linear_psize MMU_PAGE_256M
111
112 #endif