root/arch/nds32/include/asm/nds32_fpu_inst.h

INCLUDED FROM

   1 /* SPDX-License-Identifier: GPL-2.0 */
   2 /* Copyright (C) 2005-2018 Andes Technology Corporation */
   3 
   4 #ifndef __NDS32_FPU_INST_H
   5 #define __NDS32_FPU_INST_H
   6 
   7 #define cop0_op 0x35
   8 
   9 /*
  10  * COP0 field of opcodes.
  11  */
  12 #define fs1_op  0x0
  13 #define fs2_op  0x4
  14 #define fd1_op  0x8
  15 #define fd2_op  0xc
  16 
  17 /*
  18  * FS1 opcode.
  19  */
  20 enum fs1 {
  21         fadds_op, fsubs_op, fcpynss_op, fcpyss_op,
  22         fmadds_op, fmsubs_op, fcmovns_op, fcmovzs_op,
  23         fnmadds_op, fnmsubs_op,
  24         fmuls_op = 0xc, fdivs_op,
  25         fs1_f2op_op = 0xf
  26 };
  27 
  28 /*
  29  * FS1/F2OP opcode.
  30  */
  31 enum fs1_f2 {
  32         fs2d_op, fsqrts_op,
  33         fui2s_op = 0x8, fsi2s_op = 0xc,
  34         fs2ui_op = 0x10, fs2ui_z_op = 0x14,
  35         fs2si_op = 0x18, fs2si_z_op = 0x1c
  36 };
  37 
  38 /*
  39  * FS2 opcode.
  40  */
  41 enum fs2 {
  42         fcmpeqs_op, fcmpeqs_e_op, fcmplts_op, fcmplts_e_op,
  43         fcmples_op, fcmples_e_op, fcmpuns_op, fcmpuns_e_op
  44 };
  45 
  46 /*
  47  * FD1 opcode.
  48  */
  49 enum fd1 {
  50         faddd_op, fsubd_op, fcpynsd_op, fcpysd_op,
  51         fmaddd_op, fmsubd_op, fcmovnd_op, fcmovzd_op,
  52         fnmaddd_op, fnmsubd_op,
  53         fmuld_op = 0xc, fdivd_op, fd1_f2op_op = 0xf
  54 };
  55 
  56 /*
  57  * FD1/F2OP opcode.
  58  */
  59 enum fd1_f2 {
  60         fd2s_op, fsqrtd_op,
  61         fui2d_op = 0x8, fsi2d_op = 0xc,
  62         fd2ui_op = 0x10, fd2ui_z_op = 0x14,
  63         fd2si_op = 0x18, fd2si_z_op = 0x1c
  64 };
  65 
  66 /*
  67  * FD2 opcode.
  68  */
  69 enum fd2 {
  70         fcmpeqd_op, fcmpeqd_e_op, fcmpltd_op, fcmpltd_e_op,
  71         fcmpled_op, fcmpled_e_op, fcmpund_op, fcmpund_e_op
  72 };
  73 
  74 #define NDS32Insn(x) x
  75 
  76 #define I_OPCODE_off                    25
  77 #define NDS32Insn_OPCODE(x)             (NDS32Insn(x) >> I_OPCODE_off)
  78 
  79 #define I_OPCODE_offRt                  20
  80 #define I_OPCODE_mskRt                  (0x1fUL << I_OPCODE_offRt)
  81 #define NDS32Insn_OPCODE_Rt(x) \
  82         ((NDS32Insn(x) & I_OPCODE_mskRt) >> I_OPCODE_offRt)
  83 
  84 #define I_OPCODE_offRa                  15
  85 #define I_OPCODE_mskRa                  (0x1fUL << I_OPCODE_offRa)
  86 #define NDS32Insn_OPCODE_Ra(x) \
  87         ((NDS32Insn(x) & I_OPCODE_mskRa) >> I_OPCODE_offRa)
  88 
  89 #define I_OPCODE_offRb                  10
  90 #define I_OPCODE_mskRb                  (0x1fUL << I_OPCODE_offRb)
  91 #define NDS32Insn_OPCODE_Rb(x) \
  92         ((NDS32Insn(x) & I_OPCODE_mskRb) >> I_OPCODE_offRb)
  93 
  94 #define I_OPCODE_offbit1014             10
  95 #define I_OPCODE_mskbit1014             (0x1fUL << I_OPCODE_offbit1014)
  96 #define NDS32Insn_OPCODE_BIT1014(x) \
  97         ((NDS32Insn(x) & I_OPCODE_mskbit1014) >> I_OPCODE_offbit1014)
  98 
  99 #define I_OPCODE_offbit69               6
 100 #define I_OPCODE_mskbit69               (0xfUL << I_OPCODE_offbit69)
 101 #define NDS32Insn_OPCODE_BIT69(x) \
 102         ((NDS32Insn(x) & I_OPCODE_mskbit69) >> I_OPCODE_offbit69)
 103 
 104 #define I_OPCODE_offCOP0                0
 105 #define I_OPCODE_mskCOP0                (0x3fUL << I_OPCODE_offCOP0)
 106 #define NDS32Insn_OPCODE_COP0(x) \
 107         ((NDS32Insn(x) & I_OPCODE_mskCOP0) >> I_OPCODE_offCOP0)
 108 
 109 #endif /* __NDS32_FPU_INST_H */