arch/powerpc/include/asm/reg.h

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This source file includes following definitions.
mtmsr_isync
msr_check_and_clear
mtsrin
update_power8_hid0
   1 /* SPDX-License-Identifier: GPL-2.0 */
   2 /*
   3  * Contains the definition of registers common to all PowerPC variants.
   4  * If a register definition has been changed in a different PowerPC
   5  * variant, we will case it in #ifndef XXX ... #endif, and have the
   6  * number used in the Programming Environments Manual For 32-Bit
   7  * Implementations of the PowerPC Architecture (a.k.a. Green Book) here.
   8  */
   9 
  10 #ifndef _ASM_POWERPC_REG_H
  11 #define _ASM_POWERPC_REG_H
  12 #ifdef __KERNEL__
  13 
  14 #include <linux/stringify.h>
  15 #include <asm/cputable.h>
  16 #include <asm/asm-const.h>
  17 #include <asm/feature-fixups.h>
  18 
  19 /* Pickup Book E specific registers. */
  20 #if defined(CONFIG_BOOKE) || defined(CONFIG_40x)
  21 #include <asm/reg_booke.h>
  22 #endif /* CONFIG_BOOKE || CONFIG_40x */
  23 
  24 #ifdef CONFIG_FSL_EMB_PERFMON
  25 #include <asm/reg_fsl_emb.h>
  26 #endif
  27 
  28 #ifdef CONFIG_PPC_8xx
  29 #include <asm/reg_8xx.h>
  30 #endif /* CONFIG_PPC_8xx */
  31 
  32 #define MSR_SF_LG       63              /* Enable 64 bit mode */
  33 #define MSR_ISF_LG      61              /* Interrupt 64b mode valid on 630 */
  34 #define MSR_HV_LG       60              /* Hypervisor state */
  35 #define MSR_TS_T_LG     34              /* Trans Mem state: Transactional */
  36 #define MSR_TS_S_LG     33              /* Trans Mem state: Suspended */
  37 #define MSR_TS_LG       33              /* Trans Mem state (2 bits) */
  38 #define MSR_TM_LG       32              /* Trans Mem Available */
  39 #define MSR_VEC_LG      25              /* Enable AltiVec */
  40 #define MSR_VSX_LG      23              /* Enable VSX */
  41 #define MSR_S_LG        22              /* Secure state */
  42 #define MSR_POW_LG      18              /* Enable Power Management */
  43 #define MSR_WE_LG       18              /* Wait State Enable */
  44 #define MSR_TGPR_LG     17              /* TLB Update registers in use */
  45 #define MSR_CE_LG       17              /* Critical Interrupt Enable */
  46 #define MSR_ILE_LG      16              /* Interrupt Little Endian */
  47 #define MSR_EE_LG       15              /* External Interrupt Enable */
  48 #define MSR_PR_LG       14              /* Problem State / Privilege Level */
  49 #define MSR_FP_LG       13              /* Floating Point enable */
  50 #define MSR_ME_LG       12              /* Machine Check Enable */
  51 #define MSR_FE0_LG      11              /* Floating Exception mode 0 */
  52 #define MSR_SE_LG       10              /* Single Step */
  53 #define MSR_BE_LG       9               /* Branch Trace */
  54 #define MSR_DE_LG       9               /* Debug Exception Enable */
  55 #define MSR_FE1_LG      8               /* Floating Exception mode 1 */
  56 #define MSR_IP_LG       6               /* Exception prefix 0x000/0xFFF */
  57 #define MSR_IR_LG       5               /* Instruction Relocate */
  58 #define MSR_DR_LG       4               /* Data Relocate */
  59 #define MSR_PE_LG       3               /* Protection Enable */
  60 #define MSR_PX_LG       2               /* Protection Exclusive Mode */
  61 #define MSR_PMM_LG      2               /* Performance monitor */
  62 #define MSR_RI_LG       1               /* Recoverable Exception */
  63 #define MSR_LE_LG       0               /* Little Endian */
  64 
  65 #ifdef __ASSEMBLY__
  66 #define __MASK(X)       (1<<(X))
  67 #else
  68 #define __MASK(X)       (1UL<<(X))
  69 #endif
  70 
  71 #ifdef CONFIG_PPC64
  72 #define MSR_SF          __MASK(MSR_SF_LG)       /* Enable 64 bit mode */
  73 #define MSR_ISF         __MASK(MSR_ISF_LG)      /* Interrupt 64b mode valid on 630 */
  74 #define MSR_HV          __MASK(MSR_HV_LG)       /* Hypervisor state */
  75 #define MSR_S           __MASK(MSR_S_LG)        /* Secure state */
  76 #else
  77 /* so tests for these bits fail on 32-bit */
  78 #define MSR_SF          0
  79 #define MSR_ISF         0
  80 #define MSR_HV          0
  81 #define MSR_S           0
  82 #endif
  83 
  84 /*
  85  * To be used in shared book E/book S, this avoids needing to worry about
  86  * book S/book E in shared code
  87  */
  88 #ifndef MSR_SPE
  89 #define MSR_SPE         0
  90 #endif
  91 
  92 #define MSR_VEC         __MASK(MSR_VEC_LG)      /* Enable AltiVec */
  93 #define MSR_VSX         __MASK(MSR_VSX_LG)      /* Enable VSX */
  94 #define MSR_POW         __MASK(MSR_POW_LG)      /* Enable Power Management */
  95 #define MSR_WE          __MASK(MSR_WE_LG)       /* Wait State Enable */
  96 #define MSR_TGPR        __MASK(MSR_TGPR_LG)     /* TLB Update registers in use */
  97 #define MSR_CE          __MASK(MSR_CE_LG)       /* Critical Interrupt Enable */
  98 #define MSR_ILE         __MASK(MSR_ILE_LG)      /* Interrupt Little Endian */
  99 #define MSR_EE          __MASK(MSR_EE_LG)       /* External Interrupt Enable */
 100 #define MSR_PR          __MASK(MSR_PR_LG)       /* Problem State / Privilege Level */
 101 #define MSR_FP          __MASK(MSR_FP_LG)       /* Floating Point enable */
 102 #define MSR_ME          __MASK(MSR_ME_LG)       /* Machine Check Enable */
 103 #define MSR_FE0         __MASK(MSR_FE0_LG)      /* Floating Exception mode 0 */
 104 #define MSR_SE          __MASK(MSR_SE_LG)       /* Single Step */
 105 #define MSR_BE          __MASK(MSR_BE_LG)       /* Branch Trace */
 106 #define MSR_DE          __MASK(MSR_DE_LG)       /* Debug Exception Enable */
 107 #define MSR_FE1         __MASK(MSR_FE1_LG)      /* Floating Exception mode 1 */
 108 #define MSR_IP          __MASK(MSR_IP_LG)       /* Exception prefix 0x000/0xFFF */
 109 #define MSR_IR          __MASK(MSR_IR_LG)       /* Instruction Relocate */
 110 #define MSR_DR          __MASK(MSR_DR_LG)       /* Data Relocate */
 111 #define MSR_PE          __MASK(MSR_PE_LG)       /* Protection Enable */
 112 #define MSR_PX          __MASK(MSR_PX_LG)       /* Protection Exclusive Mode */
 113 #ifndef MSR_PMM
 114 #define MSR_PMM         __MASK(MSR_PMM_LG)      /* Performance monitor */
 115 #endif
 116 #define MSR_RI          __MASK(MSR_RI_LG)       /* Recoverable Exception */
 117 #define MSR_LE          __MASK(MSR_LE_LG)       /* Little Endian */
 118 
 119 #define MSR_TM          __MASK(MSR_TM_LG)       /* Transactional Mem Available */
 120 #define MSR_TS_N        0                       /*  Non-transactional */
 121 #define MSR_TS_S        __MASK(MSR_TS_S_LG)     /*  Transaction Suspended */
 122 #define MSR_TS_T        __MASK(MSR_TS_T_LG)     /*  Transaction Transactional */
 123 #define MSR_TS_MASK     (MSR_TS_T | MSR_TS_S)   /* Transaction State bits */
 124 #define MSR_TM_RESV(x) (((x) & MSR_TS_MASK) == MSR_TS_MASK) /* Reserved */
 125 #define MSR_TM_TRANSACTIONAL(x) (((x) & MSR_TS_MASK) == MSR_TS_T)
 126 #define MSR_TM_SUSPENDED(x)     (((x) & MSR_TS_MASK) == MSR_TS_S)
 127 
 128 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
 129 #define MSR_TM_ACTIVE(x) (((x) & MSR_TS_MASK) != 0) /* Transaction active? */
 130 #else
 131 #define MSR_TM_ACTIVE(x) 0
 132 #endif
 133 
 134 #if defined(CONFIG_PPC_BOOK3S_64)
 135 #define MSR_64BIT       MSR_SF
 136 
 137 /* Server variant */
 138 #define __MSR           (MSR_ME | MSR_RI | MSR_IR | MSR_DR | MSR_ISF |MSR_HV)
 139 #ifdef __BIG_ENDIAN__
 140 #define MSR_            __MSR
 141 #define MSR_IDLE        (MSR_ME | MSR_SF | MSR_HV)
 142 #else
 143 #define MSR_            (__MSR | MSR_LE)
 144 #define MSR_IDLE        (MSR_ME | MSR_SF | MSR_HV | MSR_LE)
 145 #endif
 146 #define MSR_KERNEL      (MSR_ | MSR_64BIT)
 147 #define MSR_USER32      (MSR_ | MSR_PR | MSR_EE)
 148 #define MSR_USER64      (MSR_USER32 | MSR_64BIT)
 149 #elif defined(CONFIG_PPC_BOOK3S_32) || defined(CONFIG_PPC_8xx)
 150 /* Default MSR for kernel mode. */
 151 #define MSR_KERNEL      (MSR_ME|MSR_RI|MSR_IR|MSR_DR)
 152 #define MSR_USER        (MSR_KERNEL|MSR_PR|MSR_EE)
 153 #endif
 154 
 155 #ifndef MSR_64BIT
 156 #define MSR_64BIT       0
 157 #endif
 158 
 159 /* Condition Register related */
 160 #define CR0_SHIFT       28
 161 #define CR0_MASK        0xF
 162 #define CR0_TBEGIN_FAILURE      (0x2 << 28) /* 0b0010 */
 163 
 164 
 165 /* Power Management - Processor Stop Status and Control Register Fields */
 166 #define PSSCR_RL_MASK           0x0000000F /* Requested Level */
 167 #define PSSCR_MTL_MASK          0x000000F0 /* Maximum Transition Level */
 168 #define PSSCR_TR_MASK           0x00000300 /* Transition State */
 169 #define PSSCR_PSLL_MASK         0x000F0000 /* Power-Saving Level Limit */
 170 #define PSSCR_EC                0x00100000 /* Exit Criterion */
 171 #define PSSCR_ESL               0x00200000 /* Enable State Loss */
 172 #define PSSCR_SD                0x00400000 /* Status Disable */
 173 #define PSSCR_PLS       0xf000000000000000 /* Power-saving Level Status */
 174 #define PSSCR_PLS_SHIFT 60
 175 #define PSSCR_GUEST_VIS 0xf0000000000003ffUL /* Guest-visible PSSCR fields */
 176 #define PSSCR_FAKE_SUSPEND      0x00000400 /* Fake-suspend bit (P9 DD2.2) */
 177 #define PSSCR_FAKE_SUSPEND_LG   10         /* Fake-suspend bit position */
 178 
 179 /* Floating Point Status and Control Register (FPSCR) Fields */
 180 #define FPSCR_FX        0x80000000      /* FPU exception summary */
 181 #define FPSCR_FEX       0x40000000      /* FPU enabled exception summary */
 182 #define FPSCR_VX        0x20000000      /* Invalid operation summary */
 183 #define FPSCR_OX        0x10000000      /* Overflow exception summary */
 184 #define FPSCR_UX        0x08000000      /* Underflow exception summary */
 185 #define FPSCR_ZX        0x04000000      /* Zero-divide exception summary */
 186 #define FPSCR_XX        0x02000000      /* Inexact exception summary */
 187 #define FPSCR_VXSNAN    0x01000000      /* Invalid op for SNaN */
 188 #define FPSCR_VXISI     0x00800000      /* Invalid op for Inv - Inv */
 189 #define FPSCR_VXIDI     0x00400000      /* Invalid op for Inv / Inv */
 190 #define FPSCR_VXZDZ     0x00200000      /* Invalid op for Zero / Zero */
 191 #define FPSCR_VXIMZ     0x00100000      /* Invalid op for Inv * Zero */
 192 #define FPSCR_VXVC      0x00080000      /* Invalid op for Compare */
 193 #define FPSCR_FR        0x00040000      /* Fraction rounded */
 194 #define FPSCR_FI        0x00020000      /* Fraction inexact */
 195 #define FPSCR_FPRF      0x0001f000      /* FPU Result Flags */
 196 #define FPSCR_FPCC      0x0000f000      /* FPU Condition Codes */
 197 #define FPSCR_VXSOFT    0x00000400      /* Invalid op for software request */
 198 #define FPSCR_VXSQRT    0x00000200      /* Invalid op for square root */
 199 #define FPSCR_VXCVI     0x00000100      /* Invalid op for integer convert */
 200 #define FPSCR_VE        0x00000080      /* Invalid op exception enable */
 201 #define FPSCR_OE        0x00000040      /* IEEE overflow exception enable */
 202 #define FPSCR_UE        0x00000020      /* IEEE underflow exception enable */
 203 #define FPSCR_ZE        0x00000010      /* IEEE zero divide exception enable */
 204 #define FPSCR_XE        0x00000008      /* FP inexact exception enable */
 205 #define FPSCR_NI        0x00000004      /* FPU non IEEE-Mode */
 206 #define FPSCR_RN        0x00000003      /* FPU rounding control */
 207 
 208 /* Bit definitions for SPEFSCR. */
 209 #define SPEFSCR_SOVH    0x80000000      /* Summary integer overflow high */
 210 #define SPEFSCR_OVH     0x40000000      /* Integer overflow high */
 211 #define SPEFSCR_FGH     0x20000000      /* Embedded FP guard bit high */
 212 #define SPEFSCR_FXH     0x10000000      /* Embedded FP sticky bit high */
 213 #define SPEFSCR_FINVH   0x08000000      /* Embedded FP invalid operation high */
 214 #define SPEFSCR_FDBZH   0x04000000      /* Embedded FP div by zero high */
 215 #define SPEFSCR_FUNFH   0x02000000      /* Embedded FP underflow high */
 216 #define SPEFSCR_FOVFH   0x01000000      /* Embedded FP overflow high */
 217 #define SPEFSCR_FINXS   0x00200000      /* Embedded FP inexact sticky */
 218 #define SPEFSCR_FINVS   0x00100000      /* Embedded FP invalid op. sticky */
 219 #define SPEFSCR_FDBZS   0x00080000      /* Embedded FP div by zero sticky */
 220 #define SPEFSCR_FUNFS   0x00040000      /* Embedded FP underflow sticky */
 221 #define SPEFSCR_FOVFS   0x00020000      /* Embedded FP overflow sticky */
 222 #define SPEFSCR_MODE    0x00010000      /* Embedded FP mode */
 223 #define SPEFSCR_SOV     0x00008000      /* Integer summary overflow */
 224 #define SPEFSCR_OV      0x00004000      /* Integer overflow */
 225 #define SPEFSCR_FG      0x00002000      /* Embedded FP guard bit */
 226 #define SPEFSCR_FX      0x00001000      /* Embedded FP sticky bit */
 227 #define SPEFSCR_FINV    0x00000800      /* Embedded FP invalid operation */
 228 #define SPEFSCR_FDBZ    0x00000400      /* Embedded FP div by zero */
 229 #define SPEFSCR_FUNF    0x00000200      /* Embedded FP underflow */
 230 #define SPEFSCR_FOVF    0x00000100      /* Embedded FP overflow */
 231 #define SPEFSCR_FINXE   0x00000040      /* Embedded FP inexact enable */
 232 #define SPEFSCR_FINVE   0x00000020      /* Embedded FP invalid op. enable */
 233 #define SPEFSCR_FDBZE   0x00000010      /* Embedded FP div by zero enable */
 234 #define SPEFSCR_FUNFE   0x00000008      /* Embedded FP underflow enable */
 235 #define SPEFSCR_FOVFE   0x00000004      /* Embedded FP overflow enable */
 236 #define SPEFSCR_FRMC    0x00000003      /* Embedded FP rounding mode control */
 237 
 238 /* Special Purpose Registers (SPRNs)*/
 239 
 240 #ifdef CONFIG_40x
 241 #define SPRN_PID        0x3B1   /* Process ID */
 242 #else
 243 #define SPRN_PID        0x030   /* Process ID */
 244 #ifdef CONFIG_BOOKE
 245 #define SPRN_PID0       SPRN_PID/* Process ID Register 0 */
 246 #endif
 247 #endif
 248 
 249 #define SPRN_CTR        0x009   /* Count Register */
 250 #define SPRN_DSCR       0x11
 251 #define SPRN_CFAR       0x1c    /* Come From Address Register */
 252 #define SPRN_AMR        0x1d    /* Authority Mask Register */
 253 #define SPRN_UAMOR      0x9d    /* User Authority Mask Override Register */
 254 #define SPRN_AMOR       0x15d   /* Authority Mask Override Register */
 255 #define SPRN_ACOP       0x1F    /* Available Coprocessor Register */
 256 #define SPRN_TFIAR      0x81    /* Transaction Failure Inst Addr   */
 257 #define SPRN_TEXASR     0x82    /* Transaction EXception & Summary */
 258 #define SPRN_TEXASRU    0x83    /* ''      ''      ''    Upper 32  */
 259 
 260 #define TEXASR_FC_LG    (63 - 7)        /* Failure Code */
 261 #define TEXASR_AB_LG    (63 - 31)       /* Abort */
 262 #define TEXASR_SU_LG    (63 - 32)       /* Suspend */
 263 #define TEXASR_HV_LG    (63 - 34)       /* Hypervisor state*/
 264 #define TEXASR_PR_LG    (63 - 35)       /* Privilege level */
 265 #define TEXASR_FS_LG    (63 - 36)       /* failure summary */
 266 #define TEXASR_EX_LG    (63 - 37)       /* TFIAR exact bit */
 267 #define TEXASR_ROT_LG   (63 - 38)       /* ROT bit */
 268 
 269 #define   TEXASR_ABORT  __MASK(TEXASR_AB_LG) /* terminated by tabort or treclaim */
 270 #define   TEXASR_SUSP   __MASK(TEXASR_SU_LG) /* tx failed in suspended state */
 271 #define   TEXASR_HV     __MASK(TEXASR_HV_LG) /* MSR[HV] when failure occurred */
 272 #define   TEXASR_PR     __MASK(TEXASR_PR_LG) /* MSR[PR] when failure occurred */
 273 #define   TEXASR_FS     __MASK(TEXASR_FS_LG) /* TEXASR Failure Summary */
 274 #define   TEXASR_EXACT  __MASK(TEXASR_EX_LG) /* TFIAR value is exact */
 275 #define   TEXASR_ROT    __MASK(TEXASR_ROT_LG)
 276 #define   TEXASR_FC     (ASM_CONST(0xFF) << TEXASR_FC_LG)
 277 
 278 #define SPRN_TFHAR      0x80    /* Transaction Failure Handler Addr */
 279 
 280 #define SPRN_TIDR       144     /* Thread ID register */
 281 #define SPRN_CTRLF      0x088
 282 #define SPRN_CTRLT      0x098
 283 #define   CTRL_CT       0xc0000000      /* current thread */
 284 #define   CTRL_CT0      0x80000000      /* thread 0 */
 285 #define   CTRL_CT1      0x40000000      /* thread 1 */
 286 #define   CTRL_TE       0x00c00000      /* thread enable */
 287 #define   CTRL_RUNLATCH 0x1
 288 #define SPRN_DAWR       0xB4
 289 #define SPRN_RPR        0xBA    /* Relative Priority Register */
 290 #define SPRN_CIABR      0xBB
 291 #define   CIABR_PRIV            0x3
 292 #define   CIABR_PRIV_USER       1
 293 #define   CIABR_PRIV_SUPER      2
 294 #define   CIABR_PRIV_HYPER      3
 295 #define SPRN_DAWRX      0xBC
 296 #define   DAWRX_USER    __MASK(0)
 297 #define   DAWRX_KERNEL  __MASK(1)
 298 #define   DAWRX_HYP     __MASK(2)
 299 #define   DAWRX_WTI     __MASK(3)
 300 #define   DAWRX_WT      __MASK(4)
 301 #define   DAWRX_DR      __MASK(5)
 302 #define   DAWRX_DW      __MASK(6)
 303 #define SPRN_DABR       0x3F5   /* Data Address Breakpoint Register */
 304 #define SPRN_DABR2      0x13D   /* e300 */
 305 #define SPRN_DABRX      0x3F7   /* Data Address Breakpoint Register Extension */
 306 #define   DABRX_USER    __MASK(0)
 307 #define   DABRX_KERNEL  __MASK(1)
 308 #define   DABRX_HYP     __MASK(2)
 309 #define   DABRX_BTI     __MASK(3)
 310 #define   DABRX_ALL     (DABRX_BTI | DABRX_HYP | DABRX_KERNEL | DABRX_USER)
 311 #define SPRN_DAR        0x013   /* Data Address Register */
 312 #define SPRN_DBCR       0x136   /* e300 Data Breakpoint Control Reg */
 313 #define SPRN_DSISR      0x012   /* Data Storage Interrupt Status Register */
 314 #define   DSISR_BAD_DIRECT_ST   0x80000000 /* Obsolete: Direct store error */
 315 #define   DSISR_NOHPTE          0x40000000 /* no translation found */
 316 #define   DSISR_ATTR_CONFLICT   0x20000000 /* P9: Process vs. Partition attr */
 317 #define   DSISR_NOEXEC_OR_G     0x10000000 /* Alias of SRR1 bit, see below */
 318 #define   DSISR_PROTFAULT       0x08000000 /* protection fault */
 319 #define   DSISR_BADACCESS       0x04000000 /* bad access to CI or G */
 320 #define   DSISR_ISSTORE         0x02000000 /* access was a store */
 321 #define   DSISR_DABRMATCH       0x00400000 /* hit data breakpoint */
 322 #define   DSISR_NOSEGMENT       0x00200000 /* STAB miss (unsupported) */
 323 #define   DSISR_KEYFAULT        0x00200000 /* Storage Key fault */
 324 #define   DSISR_BAD_EXT_CTRL    0x00100000 /* Obsolete: External ctrl error */
 325 #define   DSISR_UNSUPP_MMU      0x00080000 /* P9: Unsupported MMU config */
 326 #define   DSISR_SET_RC          0x00040000 /* P9: Failed setting of R/C bits */
 327 #define   DSISR_PRTABLE_FAULT   0x00020000 /* P9: Fault on process table */
 328 #define   DSISR_ICSWX_NO_CT     0x00004000 /* P7: icswx unavailable cp type */
 329 #define   DSISR_BAD_COPYPASTE   0x00000008 /* P9: Copy/Paste on wrong memtype */
 330 #define   DSISR_BAD_AMO         0x00000004 /* P9: Incorrect AMO opcode */
 331 #define   DSISR_BAD_CI_LDST     0x00000002 /* P8: Bad HV CI load/store */
 332 
 333 /*
 334  * DSISR_NOEXEC_OR_G doesn't actually exist. This bit is always
 335  * 0 on DSIs. However, on ISIs, the corresponding bit in SRR1
 336  * indicates an attempt at executing from a no-execute PTE
 337  * or segment or from a guarded page.
 338  *
 339  * We add a definition here for completeness as we alias
 340  * DSISR and SRR1 in do_page_fault.
 341  */
 342 
 343 /*
 344  * DSISR bits that are treated as a fault. Any bit set
 345  * here will skip hash_page, and cause do_page_fault to
 346  * trigger a SIGBUS or SIGSEGV:
 347  */
 348 #define   DSISR_BAD_FAULT_32S   (DSISR_BAD_DIRECT_ST    | \
 349                                  DSISR_BADACCESS        | \
 350                                  DSISR_BAD_EXT_CTRL)
 351 #define   DSISR_BAD_FAULT_64S   (DSISR_BAD_FAULT_32S    | \
 352                                  DSISR_ATTR_CONFLICT    | \
 353                                  DSISR_UNSUPP_MMU       | \
 354                                  DSISR_PRTABLE_FAULT    | \
 355                                  DSISR_ICSWX_NO_CT      | \
 356                                  DSISR_BAD_COPYPASTE    | \
 357                                  DSISR_BAD_AMO          | \
 358                                  DSISR_BAD_CI_LDST)
 359 /*
 360  * These bits are equivalent in SRR1 and DSISR for 0x400
 361  * instruction access interrupts on Book3S
 362  */
 363 #define   DSISR_SRR1_MATCH_32S  (DSISR_NOHPTE           | \
 364                                  DSISR_NOEXEC_OR_G      | \
 365                                  DSISR_PROTFAULT)
 366 #define   DSISR_SRR1_MATCH_64S  (DSISR_SRR1_MATCH_32S   | \
 367                                  DSISR_KEYFAULT         | \
 368                                  DSISR_UNSUPP_MMU       | \
 369                                  DSISR_SET_RC           | \
 370                                  DSISR_PRTABLE_FAULT)
 371 
 372 #define SPRN_TBRL       0x10C   /* Time Base Read Lower Register (user, R/O) */
 373 #define SPRN_TBRU       0x10D   /* Time Base Read Upper Register (user, R/O) */
 374 #define SPRN_CIR        0x11B   /* Chip Information Register (hyper, R/0) */
 375 #define SPRN_TBWL       0x11C   /* Time Base Lower Register (super, R/W) */
 376 #define SPRN_TBWU       0x11D   /* Time Base Upper Register (super, R/W) */
 377 #define SPRN_TBU40      0x11E   /* Timebase upper 40 bits (hyper, R/W) */
 378 #define SPRN_SPURR      0x134   /* Scaled PURR */
 379 #define SPRN_HSPRG0     0x130   /* Hypervisor Scratch 0 */
 380 #define SPRN_HSPRG1     0x131   /* Hypervisor Scratch 1 */
 381 #define SPRN_HDSISR     0x132
 382 #define SPRN_HDAR       0x133
 383 #define SPRN_HDEC       0x136   /* Hypervisor Decrementer */
 384 #define SPRN_HIOR       0x137   /* 970 Hypervisor interrupt offset */
 385 #define SPRN_RMOR       0x138   /* Real mode offset register */
 386 #define SPRN_HRMOR      0x139   /* Real mode offset register */
 387 #define SPRN_HSRR0      0x13A   /* Hypervisor Save/Restore 0 */
 388 #define SPRN_HSRR1      0x13B   /* Hypervisor Save/Restore 1 */
 389 #define SPRN_ASDR       0x330   /* Access segment descriptor register */
 390 #define SPRN_IC         0x350   /* Virtual Instruction Count */
 391 #define SPRN_VTB        0x351   /* Virtual Time Base */
 392 #define SPRN_LDBAR      0x352   /* LD Base Address Register */
 393 #define SPRN_PMICR      0x354   /* Power Management Idle Control Reg */
 394 #define SPRN_PMSR       0x355   /* Power Management Status Reg */
 395 #define SPRN_PMMAR      0x356   /* Power Management Memory Activity Register */
 396 #define SPRN_PSSCR      0x357   /* Processor Stop Status and Control Register (ISA 3.0) */
 397 #define SPRN_PSSCR_PR   0x337   /* PSSCR ISA 3.0, privileged mode access */
 398 #define SPRN_PMCR       0x374   /* Power Management Control Register */
 399 #define SPRN_RWMR       0x375   /* Region-Weighting Mode Register */
 400 
 401 /* HFSCR and FSCR bit numbers are the same */
 402 #define FSCR_SCV_LG     12      /* Enable System Call Vectored */
 403 #define FSCR_MSGP_LG    10      /* Enable MSGP */
 404 #define FSCR_TAR_LG     8       /* Enable Target Address Register */
 405 #define FSCR_EBB_LG     7       /* Enable Event Based Branching */
 406 #define FSCR_TM_LG      5       /* Enable Transactional Memory */
 407 #define FSCR_BHRB_LG    4       /* Enable Branch History Rolling Buffer*/
 408 #define FSCR_PM_LG      3       /* Enable prob/priv access to PMU SPRs */
 409 #define FSCR_DSCR_LG    2       /* Enable Data Stream Control Register */
 410 #define FSCR_VECVSX_LG  1       /* Enable VMX/VSX  */
 411 #define FSCR_FP_LG      0       /* Enable Floating Point */
 412 #define SPRN_FSCR       0x099   /* Facility Status & Control Register */
 413 #define   FSCR_SCV      __MASK(FSCR_SCV_LG)
 414 #define   FSCR_TAR      __MASK(FSCR_TAR_LG)
 415 #define   FSCR_EBB      __MASK(FSCR_EBB_LG)
 416 #define   FSCR_DSCR     __MASK(FSCR_DSCR_LG)
 417 #define SPRN_HFSCR      0xbe    /* HV=1 Facility Status & Control Register */
 418 #define   HFSCR_MSGP    __MASK(FSCR_MSGP_LG)
 419 #define   HFSCR_TAR     __MASK(FSCR_TAR_LG)
 420 #define   HFSCR_EBB     __MASK(FSCR_EBB_LG)
 421 #define   HFSCR_TM      __MASK(FSCR_TM_LG)
 422 #define   HFSCR_PM      __MASK(FSCR_PM_LG)
 423 #define   HFSCR_BHRB    __MASK(FSCR_BHRB_LG)
 424 #define   HFSCR_DSCR    __MASK(FSCR_DSCR_LG)
 425 #define   HFSCR_VECVSX  __MASK(FSCR_VECVSX_LG)
 426 #define   HFSCR_FP      __MASK(FSCR_FP_LG)
 427 #define   HFSCR_INTR_CAUSE (ASM_CONST(0xFF) << 56)      /* interrupt cause */
 428 #define SPRN_TAR        0x32f   /* Target Address Register */
 429 #define SPRN_LPCR       0x13E   /* LPAR Control Register */
 430 #define   LPCR_VPM0             ASM_CONST(0x8000000000000000)
 431 #define   LPCR_VPM1             ASM_CONST(0x4000000000000000)
 432 #define   LPCR_ISL              ASM_CONST(0x2000000000000000)
 433 #define   LPCR_VC_SH            61
 434 #define   LPCR_DPFD_SH          52
 435 #define   LPCR_DPFD             (ASM_CONST(7) << LPCR_DPFD_SH)
 436 #define   LPCR_VRMASD_SH        47
 437 #define   LPCR_VRMASD           (ASM_CONST(0x1f) << LPCR_VRMASD_SH)
 438 #define   LPCR_VRMA_L           ASM_CONST(0x0008000000000000)
 439 #define   LPCR_VRMA_LP0         ASM_CONST(0x0001000000000000)
 440 #define   LPCR_VRMA_LP1         ASM_CONST(0x0000800000000000)
 441 #define   LPCR_RMLS             0x1C000000      /* Implementation dependent RMO limit sel */
 442 #define   LPCR_RMLS_SH          26
 443 #define   LPCR_ILE              ASM_CONST(0x0000000002000000)   /* !HV irqs set MSR:LE */
 444 #define   LPCR_AIL              ASM_CONST(0x0000000001800000)   /* Alternate interrupt location */
 445 #define   LPCR_AIL_0            ASM_CONST(0x0000000000000000)   /* MMU off exception offset 0x0 */
 446 #define   LPCR_AIL_3            ASM_CONST(0x0000000001800000)   /* MMU on exception offset 0xc00...4xxx */
 447 #define   LPCR_ONL              ASM_CONST(0x0000000000040000)   /* online - PURR/SPURR count */
 448 #define   LPCR_LD               ASM_CONST(0x0000000000020000)   /* large decremeter */
 449 #define   LPCR_PECE             ASM_CONST(0x000000000001f000)   /* powersave exit cause enable */
 450 #define     LPCR_PECEDP ASM_CONST(0x0000000000010000)   /* directed priv dbells cause exit */
 451 #define     LPCR_PECEDH ASM_CONST(0x0000000000008000)   /* directed hyp dbells cause exit */
 452 #define     LPCR_PECE0          ASM_CONST(0x0000000000004000)   /* ext. exceptions can cause exit */
 453 #define     LPCR_PECE1          ASM_CONST(0x0000000000002000)   /* decrementer can cause exit */
 454 #define     LPCR_PECE2          ASM_CONST(0x0000000000001000)   /* machine check etc can cause exit */
 455 #define     LPCR_PECE_HVEE      ASM_CONST(0x0000400000000000)   /* P9 Wakeup on HV interrupts */
 456 #define   LPCR_MER              ASM_CONST(0x0000000000000800)   /* Mediated External Exception */
 457 #define   LPCR_MER_SH           11
 458 #define   LPCR_GTSE             ASM_CONST(0x0000000000000400)   /* Guest Translation Shootdown Enable */
 459 #define   LPCR_TC               ASM_CONST(0x0000000000000200)   /* Translation control */
 460 #define   LPCR_HEIC             ASM_CONST(0x0000000000000010)   /* Hypervisor External Interrupt Control */
 461 #define   LPCR_LPES             0x0000000c
 462 #define   LPCR_LPES0            ASM_CONST(0x0000000000000008)      /* LPAR Env selector 0 */
 463 #define   LPCR_LPES1            ASM_CONST(0x0000000000000004)      /* LPAR Env selector 1 */
 464 #define   LPCR_LPES_SH          2
 465 #define   LPCR_RMI              ASM_CONST(0x0000000000000002)      /* real mode is cache inhibit */
 466 #define   LPCR_HVICE            ASM_CONST(0x0000000000000002)      /* P9: HV interrupt enable */
 467 #define   LPCR_HDICE            ASM_CONST(0x0000000000000001)      /* Hyp Decr enable (HV,PR,EE) */
 468 #define   LPCR_UPRT             ASM_CONST(0x0000000000400000)      /* Use Process Table (ISA 3) */
 469 #define   LPCR_HR               ASM_CONST(0x0000000000100000)
 470 #ifndef SPRN_LPID
 471 #define SPRN_LPID       0x13F   /* Logical Partition Identifier */
 472 #endif
 473 #define   LPID_RSVD     0x3ff           /* Reserved LPID for partn switching */
 474 #define SPRN_HMER       0x150   /* Hypervisor maintenance exception reg */
 475 #define   HMER_DEBUG_TRIG       (1ul << (63 - 17)) /* Debug trigger */
 476 #define SPRN_HMEER      0x151   /* Hyp maintenance exception enable reg */
 477 #define SPRN_PCR        0x152   /* Processor compatibility register */
 478 #define   PCR_VEC_DIS   (__MASK(63-0))  /* Vec. disable (bit NA since POWER8) */
 479 #define   PCR_VSX_DIS   (__MASK(63-1))  /* VSX disable (bit NA since POWER8) */
 480 #define   PCR_TM_DIS    (__MASK(63-2))  /* Trans. memory disable (POWER8) */
 481 #define   PCR_HIGH_BITS (PCR_VEC_DIS | PCR_VSX_DIS | PCR_TM_DIS)
 482 /*
 483  * These bits are used in the function kvmppc_set_arch_compat() to specify and
 484  * determine both the compatibility level which we want to emulate and the
 485  * compatibility level which the host is capable of emulating.
 486  */
 487 #define   PCR_ARCH_207  0x8             /* Architecture 2.07 */
 488 #define   PCR_ARCH_206  0x4             /* Architecture 2.06 */
 489 #define   PCR_ARCH_205  0x2             /* Architecture 2.05 */
 490 #define   PCR_LOW_BITS  (PCR_ARCH_207 | PCR_ARCH_206 | PCR_ARCH_205)
 491 #define   PCR_MASK      ~(PCR_HIGH_BITS | PCR_LOW_BITS) /* PCR Reserved Bits */
 492 #define SPRN_HEIR       0x153   /* Hypervisor Emulated Instruction Register */
 493 #define SPRN_TLBINDEXR  0x154   /* P7 TLB control register */
 494 #define SPRN_TLBVPNR    0x155   /* P7 TLB control register */
 495 #define SPRN_TLBRPNR    0x156   /* P7 TLB control register */
 496 #define SPRN_TLBLPIDR   0x157   /* P7 TLB control register */
 497 #define SPRN_DBAT0L     0x219   /* Data BAT 0 Lower Register */
 498 #define SPRN_DBAT0U     0x218   /* Data BAT 0 Upper Register */
 499 #define SPRN_DBAT1L     0x21B   /* Data BAT 1 Lower Register */
 500 #define SPRN_DBAT1U     0x21A   /* Data BAT 1 Upper Register */
 501 #define SPRN_DBAT2L     0x21D   /* Data BAT 2 Lower Register */
 502 #define SPRN_DBAT2U     0x21C   /* Data BAT 2 Upper Register */
 503 #define SPRN_DBAT3L     0x21F   /* Data BAT 3 Lower Register */
 504 #define SPRN_DBAT3U     0x21E   /* Data BAT 3 Upper Register */
 505 #define SPRN_DBAT4L     0x239   /* Data BAT 4 Lower Register */
 506 #define SPRN_DBAT4U     0x238   /* Data BAT 4 Upper Register */
 507 #define SPRN_DBAT5L     0x23B   /* Data BAT 5 Lower Register */
 508 #define SPRN_DBAT5U     0x23A   /* Data BAT 5 Upper Register */
 509 #define SPRN_DBAT6L     0x23D   /* Data BAT 6 Lower Register */
 510 #define SPRN_DBAT6U     0x23C   /* Data BAT 6 Upper Register */
 511 #define SPRN_DBAT7L     0x23F   /* Data BAT 7 Lower Register */
 512 #define SPRN_DBAT7U     0x23E   /* Data BAT 7 Upper Register */
 513 #define SPRN_PPR        0x380   /* SMT Thread status Register */
 514 #define SPRN_TSCR       0x399   /* Thread Switch Control Register */
 515 
 516 #define SPRN_DEC        0x016           /* Decrement Register */
 517 #define SPRN_DER        0x095           /* Debug Enable Register */
 518 #define DER_RSTE        0x40000000      /* Reset Interrupt */
 519 #define DER_CHSTPE      0x20000000      /* Check Stop */
 520 #define DER_MCIE        0x10000000      /* Machine Check Interrupt */
 521 #define DER_EXTIE       0x02000000      /* External Interrupt */
 522 #define DER_ALIE        0x01000000      /* Alignment Interrupt */
 523 #define DER_PRIE        0x00800000      /* Program Interrupt */
 524 #define DER_FPUVIE      0x00400000      /* FP Unavailable Interrupt */
 525 #define DER_DECIE       0x00200000      /* Decrementer Interrupt */
 526 #define DER_SYSIE       0x00040000      /* System Call Interrupt */
 527 #define DER_TRE         0x00020000      /* Trace Interrupt */
 528 #define DER_SEIE        0x00004000      /* FP SW Emulation Interrupt */
 529 #define DER_ITLBMSE     0x00002000      /* Imp. Spec. Instruction TLB Miss */
 530 #define DER_ITLBERE     0x00001000      /* Imp. Spec. Instruction TLB Error */
 531 #define DER_DTLBMSE     0x00000800      /* Imp. Spec. Data TLB Miss */
 532 #define DER_DTLBERE     0x00000400      /* Imp. Spec. Data TLB Error */
 533 #define DER_LBRKE       0x00000008      /* Load/Store Breakpoint Interrupt */
 534 #define DER_IBRKE       0x00000004      /* Instruction Breakpoint Interrupt */
 535 #define DER_EBRKE       0x00000002      /* External Breakpoint Interrupt */
 536 #define DER_DPIE        0x00000001      /* Dev. Port Nonmaskable Request */
 537 #define SPRN_DMISS      0x3D0           /* Data TLB Miss Register */
 538 #define SPRN_DHDES      0x0B1           /* Directed Hyp. Doorbell Exc. State */
 539 #define SPRN_DPDES      0x0B0           /* Directed Priv. Doorbell Exc. State */
 540 #define SPRN_EAR        0x11A           /* External Address Register */
 541 #define SPRN_HASH1      0x3D2           /* Primary Hash Address Register */
 542 #define SPRN_HASH2      0x3D3           /* Secondary Hash Address Register */
 543 #define SPRN_HID0       0x3F0           /* Hardware Implementation Register 0 */
 544 #define HID0_HDICE_SH   (63 - 23)       /* 970 HDEC interrupt enable */
 545 #define HID0_EMCP       (1<<31)         /* Enable Machine Check pin */
 546 #define HID0_EBA        (1<<29)         /* Enable Bus Address Parity */
 547 #define HID0_EBD        (1<<28)         /* Enable Bus Data Parity */
 548 #define HID0_SBCLK      (1<<27)
 549 #define HID0_EICE       (1<<26)
 550 #define HID0_TBEN       (1<<26)         /* Timebase enable - 745x */
 551 #define HID0_ECLK       (1<<25)
 552 #define HID0_PAR        (1<<24)
 553 #define HID0_STEN       (1<<24)         /* Software table search enable - 745x */
 554 #define HID0_HIGH_BAT   (1<<23)         /* Enable high BATs - 7455 */
 555 #define HID0_DOZE       (1<<23)
 556 #define HID0_NAP        (1<<22)
 557 #define HID0_SLEEP      (1<<21)
 558 #define HID0_DPM        (1<<20)
 559 #define HID0_BHTCLR     (1<<18)         /* Clear branch history table - 7450 */
 560 #define HID0_XAEN       (1<<17)         /* Extended addressing enable - 7450 */
 561 #define HID0_NHR        (1<<16)         /* Not hard reset (software bit-7450)*/
 562 #define HID0_ICE        (1<<15)         /* Instruction Cache Enable */
 563 #define HID0_DCE        (1<<14)         /* Data Cache Enable */
 564 #define HID0_ILOCK      (1<<13)         /* Instruction Cache Lock */
 565 #define HID0_DLOCK      (1<<12)         /* Data Cache Lock */
 566 #define HID0_ICFI       (1<<11)         /* Instr. Cache Flash Invalidate */
 567 #define HID0_DCI        (1<<10)         /* Data Cache Invalidate */
 568 #define HID0_SPD        (1<<9)          /* Speculative disable */
 569 #define HID0_DAPUEN     (1<<8)          /* Debug APU enable */
 570 #define HID0_SGE        (1<<7)          /* Store Gathering Enable */
 571 #define HID0_SIED       (1<<7)          /* Serial Instr. Execution [Disable] */
 572 #define HID0_DCFA       (1<<6)          /* Data Cache Flush Assist */
 573 #define HID0_LRSTK      (1<<4)          /* Link register stack - 745x */
 574 #define HID0_BTIC       (1<<5)          /* Branch Target Instr Cache Enable */
 575 #define HID0_ABE        (1<<3)          /* Address Broadcast Enable */
 576 #define HID0_FOLD       (1<<3)          /* Branch Folding enable - 745x */
 577 #define HID0_BHTE       (1<<2)          /* Branch History Table Enable */
 578 #define HID0_BTCD       (1<<1)          /* Branch target cache disable */
 579 #define HID0_NOPDST     (1<<1)          /* No-op dst, dstt, etc. instr. */
 580 #define HID0_NOPTI      (1<<0)          /* No-op dcbt and dcbst instr. */
 581 /* POWER8 HID0 bits */
 582 #define HID0_POWER8_4LPARMODE   __MASK(61)
 583 #define HID0_POWER8_2LPARMODE   __MASK(57)
 584 #define HID0_POWER8_1TO2LPAR    __MASK(52)
 585 #define HID0_POWER8_1TO4LPAR    __MASK(51)
 586 #define HID0_POWER8_DYNLPARDIS  __MASK(48)
 587 
 588 /* POWER9 HID0 bits */
 589 #define HID0_POWER9_RADIX       __MASK(63 - 8)
 590 
 591 #define SPRN_HID1       0x3F1           /* Hardware Implementation Register 1 */
 592 #ifdef CONFIG_PPC_BOOK3S_32
 593 #define HID1_EMCP       (1<<31)         /* 7450 Machine Check Pin Enable */
 594 #define HID1_DFS        (1<<22)         /* 7447A Dynamic Frequency Scaling */
 595 #define HID1_PC0        (1<<16)         /* 7450 PLL_CFG[0] */
 596 #define HID1_PC1        (1<<15)         /* 7450 PLL_CFG[1] */
 597 #define HID1_PC2        (1<<14)         /* 7450 PLL_CFG[2] */
 598 #define HID1_PC3        (1<<13)         /* 7450 PLL_CFG[3] */
 599 #define HID1_SYNCBE     (1<<11)         /* 7450 ABE for sync, eieio */
 600 #define HID1_ABE        (1<<10)         /* 7450 Address Broadcast Enable */
 601 #define HID1_PS         (1<<16)         /* 750FX PLL selection */
 602 #endif
 603 #define SPRN_HID2       0x3F8           /* Hardware Implementation Register 2 */
 604 #define SPRN_HID2_GEKKO 0x398           /* Gekko HID2 Register */
 605 #define SPRN_IABR       0x3F2   /* Instruction Address Breakpoint Register */
 606 #define SPRN_IABR2      0x3FA           /* 83xx */
 607 #define SPRN_IBCR       0x135           /* 83xx Insn Breakpoint Control Reg */
 608 #define SPRN_IAMR       0x03D           /* Instr. Authority Mask Reg */
 609 #define SPRN_HID4       0x3F4           /* 970 HID4 */
 610 #define  HID4_LPES0      (1ul << (63-0)) /* LPAR env. sel. bit 0 */
 611 #define  HID4_RMLS2_SH   (63 - 2)       /* Real mode limit bottom 2 bits */
 612 #define  HID4_LPID5_SH   (63 - 6)       /* partition ID bottom 4 bits */
 613 #define  HID4_RMOR_SH    (63 - 22)      /* real mode offset (16 bits) */
 614 #define  HID4_RMOR       (0xFFFFul << HID4_RMOR_SH)
 615 #define  HID4_LPES1      (1 << (63-57)) /* LPAR env. sel. bit 1 */
 616 #define  HID4_RMLS0_SH   (63 - 58)      /* Real mode limit top bit */
 617 #define  HID4_LPID1_SH   0              /* partition ID top 2 bits */
 618 #define SPRN_HID4_GEKKO 0x3F3           /* Gekko HID4 */
 619 #define SPRN_HID5       0x3F6           /* 970 HID5 */
 620 #define SPRN_HID6       0x3F9   /* BE HID 6 */
 621 #define   HID6_LB       (0x0F<<12) /* Concurrent Large Page Modes */
 622 #define   HID6_DLP      (1<<20) /* Disable all large page modes (4K only) */
 623 #define SPRN_TSC_CELL   0x399   /* Thread switch control on Cell */
 624 #define   TSC_CELL_DEC_ENABLE_0 0x400000 /* Decrementer Interrupt */
 625 #define   TSC_CELL_DEC_ENABLE_1 0x200000 /* Decrementer Interrupt */
 626 #define   TSC_CELL_EE_ENABLE    0x100000 /* External Interrupt */
 627 #define   TSC_CELL_EE_BOOST     0x080000 /* External Interrupt Boost */
 628 #define SPRN_TSC        0x3FD   /* Thread switch control on others */
 629 #define SPRN_TST        0x3FC   /* Thread switch timeout on others */
 630 #if !defined(SPRN_IAC1) && !defined(SPRN_IAC2)
 631 #define SPRN_IAC1       0x3F4           /* Instruction Address Compare 1 */
 632 #define SPRN_IAC2       0x3F5           /* Instruction Address Compare 2 */
 633 #endif
 634 #define SPRN_IBAT0L     0x211           /* Instruction BAT 0 Lower Register */
 635 #define SPRN_IBAT0U     0x210           /* Instruction BAT 0 Upper Register */
 636 #define SPRN_IBAT1L     0x213           /* Instruction BAT 1 Lower Register */
 637 #define SPRN_IBAT1U     0x212           /* Instruction BAT 1 Upper Register */
 638 #define SPRN_IBAT2L     0x215           /* Instruction BAT 2 Lower Register */
 639 #define SPRN_IBAT2U     0x214           /* Instruction BAT 2 Upper Register */
 640 #define SPRN_IBAT3L     0x217           /* Instruction BAT 3 Lower Register */
 641 #define SPRN_IBAT3U     0x216           /* Instruction BAT 3 Upper Register */
 642 #define SPRN_IBAT4L     0x231           /* Instruction BAT 4 Lower Register */
 643 #define SPRN_IBAT4U     0x230           /* Instruction BAT 4 Upper Register */
 644 #define SPRN_IBAT5L     0x233           /* Instruction BAT 5 Lower Register */
 645 #define SPRN_IBAT5U     0x232           /* Instruction BAT 5 Upper Register */
 646 #define SPRN_IBAT6L     0x235           /* Instruction BAT 6 Lower Register */
 647 #define SPRN_IBAT6U     0x234           /* Instruction BAT 6 Upper Register */
 648 #define SPRN_IBAT7L     0x237           /* Instruction BAT 7 Lower Register */
 649 #define SPRN_IBAT7U     0x236           /* Instruction BAT 7 Upper Register */
 650 #define SPRN_ICMP       0x3D5           /* Instruction TLB Compare Register */
 651 #define SPRN_ICTC       0x3FB   /* Instruction Cache Throttling Control Reg */
 652 #ifndef SPRN_ICTRL
 653 #define SPRN_ICTRL      0x3F3   /* 1011 7450 icache and interrupt ctrl */
 654 #endif
 655 #define ICTRL_EICE      0x08000000      /* enable icache parity errs */
 656 #define ICTRL_EDC       0x04000000      /* enable dcache parity errs */
 657 #define ICTRL_EICP      0x00000100      /* enable icache par. check */
 658 #define SPRN_IMISS      0x3D4           /* Instruction TLB Miss Register */
 659 #define SPRN_IMMR       0x27E           /* Internal Memory Map Register */
 660 #define SPRN_L2CR       0x3F9           /* Level 2 Cache Control Register */
 661 #define SPRN_L2CR2      0x3f8
 662 #define L2CR_L2E                0x80000000      /* L2 enable */
 663 #define L2CR_L2PE               0x40000000      /* L2 parity enable */
 664 #define L2CR_L2SIZ_MASK         0x30000000      /* L2 size mask */
 665 #define L2CR_L2SIZ_256KB        0x10000000      /* L2 size 256KB */
 666 #define L2CR_L2SIZ_512KB        0x20000000      /* L2 size 512KB */
 667 #define L2CR_L2SIZ_1MB          0x30000000      /* L2 size 1MB */
 668 #define L2CR_L2CLK_MASK         0x0e000000      /* L2 clock mask */
 669 #define L2CR_L2CLK_DISABLED     0x00000000      /* L2 clock disabled */
 670 #define L2CR_L2CLK_DIV1         0x02000000      /* L2 clock / 1 */
 671 #define L2CR_L2CLK_DIV1_5       0x04000000      /* L2 clock / 1.5 */
 672 #define L2CR_L2CLK_DIV2         0x08000000      /* L2 clock / 2 */
 673 #define L2CR_L2CLK_DIV2_5       0x0a000000      /* L2 clock / 2.5 */
 674 #define L2CR_L2CLK_DIV3         0x0c000000      /* L2 clock / 3 */
 675 #define L2CR_L2RAM_MASK         0x01800000      /* L2 RAM type mask */
 676 #define L2CR_L2RAM_FLOW         0x00000000      /* L2 RAM flow through */
 677 #define L2CR_L2RAM_PIPE         0x01000000      /* L2 RAM pipelined */
 678 #define L2CR_L2RAM_PIPE_LW      0x01800000      /* L2 RAM pipelined latewr */
 679 #define L2CR_L2DO               0x00400000      /* L2 data only */
 680 #define L2CR_L2I                0x00200000      /* L2 global invalidate */
 681 #define L2CR_L2CTL              0x00100000      /* L2 RAM control */
 682 #define L2CR_L2WT               0x00080000      /* L2 write-through */
 683 #define L2CR_L2TS               0x00040000      /* L2 test support */
 684 #define L2CR_L2OH_MASK          0x00030000      /* L2 output hold mask */
 685 #define L2CR_L2OH_0_5           0x00000000      /* L2 output hold 0.5 ns */
 686 #define L2CR_L2OH_1_0           0x00010000      /* L2 output hold 1.0 ns */
 687 #define L2CR_L2SL               0x00008000      /* L2 DLL slow */
 688 #define L2CR_L2DF               0x00004000      /* L2 differential clock */
 689 #define L2CR_L2BYP              0x00002000      /* L2 DLL bypass */
 690 #define L2CR_L2IP               0x00000001      /* L2 GI in progress */
 691 #define L2CR_L2IO_745x          0x00100000      /* L2 instr. only (745x) */
 692 #define L2CR_L2DO_745x          0x00010000      /* L2 data only (745x) */
 693 #define L2CR_L2REP_745x         0x00001000      /* L2 repl. algorithm (745x) */
 694 #define L2CR_L2HWF_745x         0x00000800      /* L2 hardware flush (745x) */
 695 #define SPRN_L3CR               0x3FA   /* Level 3 Cache Control Register */
 696 #define L3CR_L3E                0x80000000      /* L3 enable */
 697 #define L3CR_L3PE               0x40000000      /* L3 data parity enable */
 698 #define L3CR_L3APE              0x20000000      /* L3 addr parity enable */
 699 #define L3CR_L3SIZ              0x10000000      /* L3 size */
 700 #define L3CR_L3CLKEN            0x08000000      /* L3 clock enable */
 701 #define L3CR_L3RES              0x04000000      /* L3 special reserved bit */
 702 #define L3CR_L3CLKDIV           0x03800000      /* L3 clock divisor */
 703 #define L3CR_L3IO               0x00400000      /* L3 instruction only */
 704 #define L3CR_L3SPO              0x00040000      /* L3 sample point override */
 705 #define L3CR_L3CKSP             0x00030000      /* L3 clock sample point */
 706 #define L3CR_L3PSP              0x0000e000      /* L3 P-clock sample point */
 707 #define L3CR_L3REP              0x00001000      /* L3 replacement algorithm */
 708 #define L3CR_L3HWF              0x00000800      /* L3 hardware flush */
 709 #define L3CR_L3I                0x00000400      /* L3 global invalidate */
 710 #define L3CR_L3RT               0x00000300      /* L3 SRAM type */
 711 #define L3CR_L3NIRCA            0x00000080      /* L3 non-integer ratio clock adj. */
 712 #define L3CR_L3DO               0x00000040      /* L3 data only mode */
 713 #define L3CR_PMEN               0x00000004      /* L3 private memory enable */
 714 #define L3CR_PMSIZ              0x00000001      /* L3 private memory size */
 715 
 716 #define SPRN_MSSCR0     0x3f6   /* Memory Subsystem Control Register 0 */
 717 #define SPRN_MSSSR0     0x3f7   /* Memory Subsystem Status Register 1 */
 718 #define SPRN_LDSTCR     0x3f8   /* Load/Store control register */
 719 #define SPRN_LDSTDB     0x3f4   /* */
 720 #define SPRN_LR         0x008   /* Link Register */
 721 #ifndef SPRN_PIR
 722 #define SPRN_PIR        0x3FF   /* Processor Identification Register */
 723 #endif
 724 #define SPRN_TIR        0x1BE   /* Thread Identification Register */
 725 #define SPRN_PTCR       0x1D0   /* Partition table control Register */
 726 #define SPRN_PSPB       0x09F   /* Problem State Priority Boost reg */
 727 #define SPRN_PTEHI      0x3D5   /* 981 7450 PTE HI word (S/W TLB load) */
 728 #define SPRN_PTELO      0x3D6   /* 982 7450 PTE LO word (S/W TLB load) */
 729 #define SPRN_PURR       0x135   /* Processor Utilization of Resources Reg */
 730 #define SPRN_PVR        0x11F   /* Processor Version Register */
 731 #define SPRN_RPA        0x3D6   /* Required Physical Address Register */
 732 #define SPRN_SDA        0x3BF   /* Sampled Data Address Register */
 733 #define SPRN_SDR1       0x019   /* MMU Hash Base Register */
 734 #define SPRN_ASR        0x118   /* Address Space Register */
 735 #define SPRN_SIA        0x3BB   /* Sampled Instruction Address Register */
 736 #define SPRN_SPRG0      0x110   /* Special Purpose Register General 0 */
 737 #define SPRN_SPRG1      0x111   /* Special Purpose Register General 1 */
 738 #define SPRN_SPRG2      0x112   /* Special Purpose Register General 2 */
 739 #define SPRN_SPRG3      0x113   /* Special Purpose Register General 3 */
 740 #define SPRN_USPRG3     0x103   /* SPRG3 userspace read */
 741 #define SPRN_SPRG4      0x114   /* Special Purpose Register General 4 */
 742 #define SPRN_USPRG4     0x104   /* SPRG4 userspace read */
 743 #define SPRN_SPRG5      0x115   /* Special Purpose Register General 5 */
 744 #define SPRN_USPRG5     0x105   /* SPRG5 userspace read */
 745 #define SPRN_SPRG6      0x116   /* Special Purpose Register General 6 */
 746 #define SPRN_USPRG6     0x106   /* SPRG6 userspace read */
 747 #define SPRN_SPRG7      0x117   /* Special Purpose Register General 7 */
 748 #define SPRN_USPRG7     0x107   /* SPRG7 userspace read */
 749 #define SPRN_SRR0       0x01A   /* Save/Restore Register 0 */
 750 #define SPRN_SRR1       0x01B   /* Save/Restore Register 1 */
 751 #define   SRR1_ISI_NOPT         0x40000000 /* ISI: Not found in hash */
 752 #define   SRR1_ISI_N_OR_G       0x10000000 /* ISI: Access is no-exec or G */
 753 #define   SRR1_ISI_PROT         0x08000000 /* ISI: Other protection fault */
 754 #define   SRR1_WAKEMASK         0x00380000 /* reason for wakeup */
 755 #define   SRR1_WAKEMASK_P8      0x003c0000 /* reason for wakeup on POWER8 and 9 */
 756 #define   SRR1_WAKEMCE_RESVD    0x003c0000 /* Unused/reserved value used by MCE wakeup to indicate cause to idle wakeup handler */
 757 #define   SRR1_WAKESYSERR       0x00300000 /* System error */
 758 #define   SRR1_WAKEEE           0x00200000 /* External interrupt */
 759 #define   SRR1_WAKEHVI          0x00240000 /* Hypervisor Virtualization Interrupt (P9) */
 760 #define   SRR1_WAKEMT           0x00280000 /* mtctrl */
 761 #define   SRR1_WAKEHMI          0x00280000 /* Hypervisor maintenance */
 762 #define   SRR1_WAKEDEC          0x00180000 /* Decrementer interrupt */
 763 #define   SRR1_WAKEDBELL        0x00140000 /* Privileged doorbell on P8 */
 764 #define   SRR1_WAKETHERM        0x00100000 /* Thermal management interrupt */
 765 #define   SRR1_WAKERESET        0x00100000 /* System reset */
 766 #define   SRR1_WAKEHDBELL       0x000c0000 /* Hypervisor doorbell on P8 */
 767 #define   SRR1_WAKESTATE        0x00030000 /* Powersave exit mask [46:47] */
 768 #define   SRR1_WS_HVLOSS        0x00030000 /* HV resources not maintained */
 769 #define   SRR1_WS_GPRLOSS       0x00020000 /* GPRs not maintained */
 770 #define   SRR1_WS_NOLOSS        0x00010000 /* All resources maintained */
 771 #define   SRR1_PROGTM           0x00200000 /* TM Bad Thing */
 772 #define   SRR1_PROGFPE          0x00100000 /* Floating Point Enabled */
 773 #define   SRR1_PROGILL          0x00080000 /* Illegal instruction */
 774 #define   SRR1_PROGPRIV         0x00040000 /* Privileged instruction */
 775 #define   SRR1_PROGTRAP         0x00020000 /* Trap */
 776 #define   SRR1_PROGADDR         0x00010000 /* SRR0 contains subsequent addr */
 777 
 778 #define   SRR1_MCE_MCP          0x00080000 /* Machine check signal caused interrupt */
 779 
 780 #define SPRN_HSRR0      0x13A   /* Save/Restore Register 0 */
 781 #define SPRN_HSRR1      0x13B   /* Save/Restore Register 1 */
 782 #define   HSRR1_DENORM          0x00100000 /* Denorm exception */
 783 #define   HSRR1_HISI_WRITE      0x00010000 /* HISI bcs couldn't update mem */
 784 
 785 #define SPRN_TBCTL      0x35f   /* PA6T Timebase control register */
 786 #define   TBCTL_FREEZE          0x0000000000000000ull /* Freeze all tbs */
 787 #define   TBCTL_RESTART         0x0000000100000000ull /* Restart all tbs */
 788 #define   TBCTL_UPDATE_UPPER    0x0000000200000000ull /* Set upper 32 bits */
 789 #define   TBCTL_UPDATE_LOWER    0x0000000300000000ull /* Set lower 32 bits */
 790 
 791 #ifndef SPRN_SVR
 792 #define SPRN_SVR        0x11E   /* System Version Register */
 793 #endif
 794 #define SPRN_THRM1      0x3FC           /* Thermal Management Register 1 */
 795 /* these bits were defined in inverted endian sense originally, ugh, confusing */
 796 #define THRM1_TIN       (1 << 31)
 797 #define THRM1_TIV       (1 << 30)
 798 #define THRM1_THRES(x)  ((x&0x7f)<<23)
 799 #define THRM3_SITV(x)   ((x&0x3fff)<<1)
 800 #define THRM1_TID       (1<<2)
 801 #define THRM1_TIE       (1<<1)
 802 #define THRM1_V         (1<<0)
 803 #define SPRN_THRM2      0x3FD           /* Thermal Management Register 2 */
 804 #define SPRN_THRM3      0x3FE           /* Thermal Management Register 3 */
 805 #define THRM3_E         (1<<0)
 806 #define SPRN_TLBMISS    0x3D4           /* 980 7450 TLB Miss Register */
 807 #define SPRN_UMMCR0     0x3A8   /* User Monitor Mode Control Register 0 */
 808 #define SPRN_UMMCR1     0x3AC   /* User Monitor Mode Control Register 0 */
 809 #define SPRN_UPMC1      0x3A9   /* User Performance Counter Register 1 */
 810 #define SPRN_UPMC2      0x3AA   /* User Performance Counter Register 2 */
 811 #define SPRN_UPMC3      0x3AD   /* User Performance Counter Register 3 */
 812 #define SPRN_UPMC4      0x3AE   /* User Performance Counter Register 4 */
 813 #define SPRN_USIA       0x3AB   /* User Sampled Instruction Address Register */
 814 #define SPRN_VRSAVE     0x100   /* Vector Register Save Register */
 815 #define SPRN_XER        0x001   /* Fixed Point Exception Register */
 816 
 817 #define SPRN_MMCR0_GEKKO 0x3B8 /* Gekko Monitor Mode Control Register 0 */
 818 #define SPRN_MMCR1_GEKKO 0x3BC /* Gekko Monitor Mode Control Register 1 */
 819 #define SPRN_PMC1_GEKKO  0x3B9 /* Gekko Performance Monitor Control 1 */
 820 #define SPRN_PMC2_GEKKO  0x3BA /* Gekko Performance Monitor Control 2 */
 821 #define SPRN_PMC3_GEKKO  0x3BD /* Gekko Performance Monitor Control 3 */
 822 #define SPRN_PMC4_GEKKO  0x3BE /* Gekko Performance Monitor Control 4 */
 823 #define SPRN_WPAR_GEKKO  0x399 /* Gekko Write Pipe Address Register */
 824 
 825 #define SPRN_SCOMC      0x114   /* SCOM Access Control */
 826 #define SPRN_SCOMD      0x115   /* SCOM Access DATA */
 827 
 828 /* Performance monitor SPRs */
 829 #ifdef CONFIG_PPC64
 830 #define SPRN_MMCR0      795
 831 #define   MMCR0_FC      0x80000000UL /* freeze counters */
 832 #define   MMCR0_FCS     0x40000000UL /* freeze in supervisor state */
 833 #define   MMCR0_KERNEL_DISABLE MMCR0_FCS
 834 #define   MMCR0_FCP     0x20000000UL /* freeze in problem state */
 835 #define   MMCR0_PROBLEM_DISABLE MMCR0_FCP
 836 #define   MMCR0_FCM1    0x10000000UL /* freeze counters while MSR mark = 1 */
 837 #define   MMCR0_FCM0    0x08000000UL /* freeze counters while MSR mark = 0 */
 838 #define   MMCR0_PMXE    ASM_CONST(0x04000000) /* perf mon exception enable */
 839 #define   MMCR0_FCECE   ASM_CONST(0x02000000) /* freeze ctrs on enabled cond or event */
 840 #define   MMCR0_TBEE    0x00400000UL /* time base exception enable */
 841 #define   MMCR0_BHRBA   0x00200000UL /* BHRB Access allowed in userspace */
 842 #define   MMCR0_EBE     0x00100000UL /* Event based branch enable */
 843 #define   MMCR0_PMCC    0x000c0000UL /* PMC control */
 844 #define   MMCR0_PMCC_U6 0x00080000UL /* PMC1-6 are R/W by user (PR) */
 845 #define   MMCR0_PMC1CE  0x00008000UL /* PMC1 count enable*/
 846 #define   MMCR0_PMCjCE  ASM_CONST(0x00004000) /* PMCj count enable*/
 847 #define   MMCR0_TRIGGER 0x00002000UL /* TRIGGER enable */
 848 #define   MMCR0_PMAO_SYNC ASM_CONST(0x00000800) /* PMU intr is synchronous */
 849 #define   MMCR0_C56RUN  ASM_CONST(0x00000100) /* PMC5/6 count when RUN=0 */
 850 /* performance monitor alert has occurred, set to 0 after handling exception */
 851 #define   MMCR0_PMAO    ASM_CONST(0x00000080)
 852 #define   MMCR0_SHRFC   0x00000040UL /* SHRre freeze conditions between threads */
 853 #define   MMCR0_FC56    0x00000010UL /* freeze counters 5 and 6 */
 854 #define   MMCR0_FCTI    0x00000008UL /* freeze counters in tags inactive mode */
 855 #define   MMCR0_FCTA    0x00000004UL /* freeze counters in tags active mode */
 856 #define   MMCR0_FCWAIT  0x00000002UL /* freeze counter in WAIT state */
 857 #define   MMCR0_FCHV    0x00000001UL /* freeze conditions in hypervisor mode */
 858 #define SPRN_MMCR1      798
 859 #define SPRN_MMCR2      785
 860 #define SPRN_UMMCR2     769
 861 #define SPRN_MMCRA      0x312
 862 #define   MMCRA_SDSYNC  0x80000000UL /* SDAR synced with SIAR */
 863 #define   MMCRA_SDAR_DCACHE_MISS 0x40000000UL
 864 #define   MMCRA_SDAR_ERAT_MISS   0x20000000UL
 865 #define   MMCRA_SIHV    0x10000000UL /* state of MSR HV when SIAR set */
 866 #define   MMCRA_SIPR    0x08000000UL /* state of MSR PR when SIAR set */
 867 #define   MMCRA_SLOT    0x07000000UL /* SLOT bits (37-39) */
 868 #define   MMCRA_SLOT_SHIFT      24
 869 #define   MMCRA_SAMPLE_ENABLE 0x00000001UL /* enable sampling */
 870 #define   POWER6_MMCRA_SDSYNC 0x0000080000000000ULL     /* SDAR/SIAR synced */
 871 #define   POWER6_MMCRA_SIHV   0x0000040000000000ULL
 872 #define   POWER6_MMCRA_SIPR   0x0000020000000000ULL
 873 #define   POWER6_MMCRA_THRM     0x00000020UL
 874 #define   POWER6_MMCRA_OTHER    0x0000000EUL
 875 
 876 #define   POWER7P_MMCRA_SIAR_VALID 0x10000000   /* P7+ SIAR contents valid */
 877 #define   POWER7P_MMCRA_SDAR_VALID 0x08000000   /* P7+ SDAR contents valid */
 878 
 879 #define SPRN_MMCRH      316     /* Hypervisor monitor mode control register */
 880 #define SPRN_MMCRS      894     /* Supervisor monitor mode control register */
 881 #define SPRN_MMCRC      851     /* Core monitor mode control register */
 882 #define SPRN_EBBHR      804     /* Event based branch handler register */
 883 #define SPRN_EBBRR      805     /* Event based branch return register */
 884 #define SPRN_BESCR      806     /* Branch event status and control register */
 885 #define   BESCR_GE      0x8000000000000000ULL /* Global Enable */
 886 #define SPRN_WORT       895     /* Workload optimization register - thread */
 887 #define SPRN_WORC       863     /* Workload optimization register - core */
 888 
 889 #define SPRN_PMC1       787
 890 #define SPRN_PMC2       788
 891 #define SPRN_PMC3       789
 892 #define SPRN_PMC4       790
 893 #define SPRN_PMC5       791
 894 #define SPRN_PMC6       792
 895 #define SPRN_PMC7       793
 896 #define SPRN_PMC8       794
 897 #define SPRN_SIER       784
 898 #define   SIER_SIPR             0x2000000       /* Sampled MSR_PR */
 899 #define   SIER_SIHV             0x1000000       /* Sampled MSR_HV */
 900 #define   SIER_SIAR_VALID       0x0400000       /* SIAR contents valid */
 901 #define   SIER_SDAR_VALID       0x0200000       /* SDAR contents valid */
 902 #define SPRN_SIAR       796
 903 #define SPRN_SDAR       797
 904 #define SPRN_TACR       888
 905 #define SPRN_TCSCR      889
 906 #define SPRN_CSIGR      890
 907 #define SPRN_SPMC1      892
 908 #define SPRN_SPMC2      893
 909 
 910 /* When EBB is enabled, some of MMCR0/MMCR2/SIER are user accessible */
 911 #define MMCR0_USER_MASK (MMCR0_FC | MMCR0_PMXE | MMCR0_PMAO)
 912 #define MMCR2_USER_MASK 0x4020100804020000UL /* (FC1P|FC2P|FC3P|FC4P|FC5P|FC6P) */
 913 #define SIER_USER_MASK  0x7fffffUL
 914 
 915 #define SPRN_PA6T_MMCR0 795
 916 #define   PA6T_MMCR0_EN0        0x0000000000000001UL
 917 #define   PA6T_MMCR0_EN1        0x0000000000000002UL
 918 #define   PA6T_MMCR0_EN2        0x0000000000000004UL
 919 #define   PA6T_MMCR0_EN3        0x0000000000000008UL
 920 #define   PA6T_MMCR0_EN4        0x0000000000000010UL
 921 #define   PA6T_MMCR0_EN5        0x0000000000000020UL
 922 #define   PA6T_MMCR0_SUPEN      0x0000000000000040UL
 923 #define   PA6T_MMCR0_PREN       0x0000000000000080UL
 924 #define   PA6T_MMCR0_HYPEN      0x0000000000000100UL
 925 #define   PA6T_MMCR0_FCM0       0x0000000000000200UL
 926 #define   PA6T_MMCR0_FCM1       0x0000000000000400UL
 927 #define   PA6T_MMCR0_INTGEN     0x0000000000000800UL
 928 #define   PA6T_MMCR0_INTEN0     0x0000000000001000UL
 929 #define   PA6T_MMCR0_INTEN1     0x0000000000002000UL
 930 #define   PA6T_MMCR0_INTEN2     0x0000000000004000UL
 931 #define   PA6T_MMCR0_INTEN3     0x0000000000008000UL
 932 #define   PA6T_MMCR0_INTEN4     0x0000000000010000UL
 933 #define   PA6T_MMCR0_INTEN5     0x0000000000020000UL
 934 #define   PA6T_MMCR0_DISCNT     0x0000000000040000UL
 935 #define   PA6T_MMCR0_UOP        0x0000000000080000UL
 936 #define   PA6T_MMCR0_TRG        0x0000000000100000UL
 937 #define   PA6T_MMCR0_TRGEN      0x0000000000200000UL
 938 #define   PA6T_MMCR0_TRGREG     0x0000000001600000UL
 939 #define   PA6T_MMCR0_SIARLOG    0x0000000002000000UL
 940 #define   PA6T_MMCR0_SDARLOG    0x0000000004000000UL
 941 #define   PA6T_MMCR0_PROEN      0x0000000008000000UL
 942 #define   PA6T_MMCR0_PROLOG     0x0000000010000000UL
 943 #define   PA6T_MMCR0_DAMEN2     0x0000000020000000UL
 944 #define   PA6T_MMCR0_DAMEN3     0x0000000040000000UL
 945 #define   PA6T_MMCR0_DAMEN4     0x0000000080000000UL
 946 #define   PA6T_MMCR0_DAMEN5     0x0000000100000000UL
 947 #define   PA6T_MMCR0_DAMSEL2    0x0000000200000000UL
 948 #define   PA6T_MMCR0_DAMSEL3    0x0000000400000000UL
 949 #define   PA6T_MMCR0_DAMSEL4    0x0000000800000000UL
 950 #define   PA6T_MMCR0_DAMSEL5    0x0000001000000000UL
 951 #define   PA6T_MMCR0_HANDDIS    0x0000002000000000UL
 952 #define   PA6T_MMCR0_PCTEN      0x0000004000000000UL
 953 #define   PA6T_MMCR0_SOCEN      0x0000008000000000UL
 954 #define   PA6T_MMCR0_SOCMOD     0x0000010000000000UL
 955 
 956 #define SPRN_PA6T_MMCR1 798
 957 #define   PA6T_MMCR1_ES2        0x00000000000000ffUL
 958 #define   PA6T_MMCR1_ES3        0x000000000000ff00UL
 959 #define   PA6T_MMCR1_ES4        0x0000000000ff0000UL
 960 #define   PA6T_MMCR1_ES5        0x00000000ff000000UL
 961 
 962 #define SPRN_PA6T_UPMC0 771     /* User PerfMon Counter 0 */
 963 #define SPRN_PA6T_UPMC1 772     /* ... */
 964 #define SPRN_PA6T_UPMC2 773
 965 #define SPRN_PA6T_UPMC3 774
 966 #define SPRN_PA6T_UPMC4 775
 967 #define SPRN_PA6T_UPMC5 776
 968 #define SPRN_PA6T_UMMCR0 779    /* User Monitor Mode Control Register 0 */
 969 #define SPRN_PA6T_SIAR  780     /* Sampled Instruction Address */
 970 #define SPRN_PA6T_UMMCR1 782    /* User Monitor Mode Control Register 1 */
 971 #define SPRN_PA6T_SIER  785     /* Sampled Instruction Event Register */
 972 #define SPRN_PA6T_PMC0  787
 973 #define SPRN_PA6T_PMC1  788
 974 #define SPRN_PA6T_PMC2  789
 975 #define SPRN_PA6T_PMC3  790
 976 #define SPRN_PA6T_PMC4  791
 977 #define SPRN_PA6T_PMC5  792
 978 #define SPRN_PA6T_TSR0  793     /* Timestamp Register 0 */
 979 #define SPRN_PA6T_TSR1  794     /* Timestamp Register 1 */
 980 #define SPRN_PA6T_TSR2  799     /* Timestamp Register 2 */
 981 #define SPRN_PA6T_TSR3  784     /* Timestamp Register 3 */
 982 
 983 #define SPRN_PA6T_IER   981     /* Icache Error Register */
 984 #define SPRN_PA6T_DER   982     /* Dcache Error Register */
 985 #define SPRN_PA6T_BER   862     /* BIU Error Address Register */
 986 #define SPRN_PA6T_MER   849     /* MMU Error Register */
 987 
 988 #define SPRN_PA6T_IMA0  880     /* Instruction Match Array 0 */
 989 #define SPRN_PA6T_IMA1  881     /* ... */
 990 #define SPRN_PA6T_IMA2  882
 991 #define SPRN_PA6T_IMA3  883
 992 #define SPRN_PA6T_IMA4  884
 993 #define SPRN_PA6T_IMA5  885
 994 #define SPRN_PA6T_IMA6  886
 995 #define SPRN_PA6T_IMA7  887
 996 #define SPRN_PA6T_IMA8  888
 997 #define SPRN_PA6T_IMA9  889
 998 #define SPRN_PA6T_BTCR  978     /* Breakpoint and Tagging Control Register */
 999 #define SPRN_PA6T_IMAAT 979     /* Instruction Match Array Action Table */
1000 #define SPRN_PA6T_PCCR  1019    /* Power Counter Control Register */
1001 #define SPRN_BKMK       1020    /* Cell Bookmark Register */
1002 #define SPRN_PA6T_RPCCR 1021    /* Retire PC Trace Control Register */
1003 
1004 
1005 #else /* 32-bit */
1006 #define SPRN_MMCR0      952     /* Monitor Mode Control Register 0 */
1007 #define   MMCR0_FC      0x80000000UL /* freeze counters */
1008 #define   MMCR0_FCS     0x40000000UL /* freeze in supervisor state */
1009 #define   MMCR0_FCP     0x20000000UL /* freeze in problem state */
1010 #define   MMCR0_FCM1    0x10000000UL /* freeze counters while MSR mark = 1 */
1011 #define   MMCR0_FCM0    0x08000000UL /* freeze counters while MSR mark = 0 */
1012 #define   MMCR0_PMXE    0x04000000UL /* performance monitor exception enable */
1013 #define   MMCR0_FCECE   0x02000000UL /* freeze ctrs on enabled cond or event */
1014 #define   MMCR0_TBEE    0x00400000UL /* time base exception enable */
1015 #define   MMCR0_PMC1CE  0x00008000UL /* PMC1 count enable*/
1016 #define   MMCR0_PMCnCE  0x00004000UL /* count enable for all but PMC 1*/
1017 #define   MMCR0_TRIGGER 0x00002000UL /* TRIGGER enable */
1018 #define   MMCR0_PMC1SEL 0x00001fc0UL /* PMC 1 Event */
1019 #define   MMCR0_PMC2SEL 0x0000003fUL /* PMC 2 Event */
1020 
1021 #define SPRN_MMCR1      956
1022 #define   MMCR1_PMC3SEL 0xf8000000UL /* PMC 3 Event */
1023 #define   MMCR1_PMC4SEL 0x07c00000UL /* PMC 4 Event */
1024 #define   MMCR1_PMC5SEL 0x003e0000UL /* PMC 5 Event */
1025 #define   MMCR1_PMC6SEL 0x0001f800UL /* PMC 6 Event */
1026 #define SPRN_MMCR2      944
1027 #define SPRN_PMC1       953     /* Performance Counter Register 1 */
1028 #define SPRN_PMC2       954     /* Performance Counter Register 2 */
1029 #define SPRN_PMC3       957     /* Performance Counter Register 3 */
1030 #define SPRN_PMC4       958     /* Performance Counter Register 4 */
1031 #define SPRN_PMC5       945     /* Performance Counter Register 5 */
1032 #define SPRN_PMC6       946     /* Performance Counter Register 6 */
1033 
1034 #define SPRN_SIAR       955     /* Sampled Instruction Address Register */
1035 
1036 /* Bit definitions for MMCR0 and PMC1 / PMC2. */
1037 #define MMCR0_PMC1_CYCLES       (1 << 7)
1038 #define MMCR0_PMC1_ICACHEMISS   (5 << 7)
1039 #define MMCR0_PMC1_DTLB         (6 << 7)
1040 #define MMCR0_PMC2_DCACHEMISS   0x6
1041 #define MMCR0_PMC2_CYCLES       0x1
1042 #define MMCR0_PMC2_ITLB         0x7
1043 #define MMCR0_PMC2_LOADMISSTIME 0x5
1044 #endif
1045 
1046 /*
1047  * SPRG usage:
1048  *
1049  * All 64-bit:
1050  *      - SPRG1 stores PACA pointer except 64-bit server in
1051  *        HV mode in which case it is HSPRG0
1052  *
1053  * 64-bit server:
1054  *      - SPRG0 scratch for TM recheckpoint/reclaim (reserved for HV on Power4)
1055  *      - SPRG2 scratch for exception vectors
1056  *      - SPRG3 CPU and NUMA node for VDSO getcpu (user visible)
1057  *      - HSPRG0 stores PACA in HV mode
1058  *      - HSPRG1 scratch for "HV" exceptions
1059  *
1060  * 64-bit embedded
1061  *      - SPRG0 generic exception scratch
1062  *      - SPRG2 TLB exception stack
1063  *      - SPRG3 critical exception scratch (user visible, sorry!)
1064  *      - SPRG4 unused (user visible)
1065  *      - SPRG6 TLB miss scratch (user visible, sorry !)
1066  *      - SPRG7 CPU and NUMA node for VDSO getcpu (user visible)
1067  *      - SPRG8 machine check exception scratch
1068  *      - SPRG9 debug exception scratch
1069  *
1070  * All 32-bit:
1071  *      - SPRG3 current thread_struct physical addr pointer
1072  *        (virtual on BookE, physical on others)
1073  *
1074  * 32-bit classic:
1075  *      - SPRG0 scratch for exception vectors
1076  *      - SPRG1 scratch for exception vectors
1077  *      - SPRG2 indicator that we are in RTAS
1078  *      - SPRG4 (603 only) pseudo TLB LRU data
1079  *
1080  * 32-bit 40x:
1081  *      - SPRG0 scratch for exception vectors
1082  *      - SPRG1 scratch for exception vectors
1083  *      - SPRG2 scratch for exception vectors
1084  *      - SPRG4 scratch for exception vectors (not 403)
1085  *      - SPRG5 scratch for exception vectors (not 403)
1086  *      - SPRG6 scratch for exception vectors (not 403)
1087  *      - SPRG7 scratch for exception vectors (not 403)
1088  *
1089  * 32-bit 440 and FSL BookE:
1090  *      - SPRG0 scratch for exception vectors
1091  *      - SPRG1 scratch for exception vectors (*)
1092  *      - SPRG2 scratch for crit interrupts handler
1093  *      - SPRG4 scratch for exception vectors
1094  *      - SPRG5 scratch for exception vectors
1095  *      - SPRG6 scratch for machine check handler
1096  *      - SPRG7 scratch for exception vectors
1097  *      - SPRG9 scratch for debug vectors (e500 only)
1098  *
1099  *      Additionally, BookE separates "read" and "write"
1100  *      of those registers. That allows to use the userspace
1101  *      readable variant for reads, which can avoid a fault
1102  *      with KVM type virtualization.
1103  *
1104  * 32-bit 8xx:
1105  *      - SPRG0 scratch for exception vectors
1106  *      - SPRG1 scratch for exception vectors
1107  *      - SPRG2 scratch for exception vectors
1108  *
1109  */
1110 #ifdef CONFIG_PPC64
1111 #define SPRN_SPRG_PACA          SPRN_SPRG1
1112 #else
1113 #define SPRN_SPRG_THREAD        SPRN_SPRG3
1114 #endif
1115 
1116 #ifdef CONFIG_PPC_BOOK3S_64
1117 #define SPRN_SPRG_SCRATCH0      SPRN_SPRG2
1118 #define SPRN_SPRG_HPACA         SPRN_HSPRG0
1119 #define SPRN_SPRG_HSCRATCH0     SPRN_HSPRG1
1120 #define SPRN_SPRG_VDSO_READ     SPRN_USPRG3
1121 #define SPRN_SPRG_VDSO_WRITE    SPRN_SPRG3
1122 
1123 #define GET_PACA(rX)                                    \
1124         BEGIN_FTR_SECTION_NESTED(66);                   \
1125         mfspr   rX,SPRN_SPRG_PACA;                      \
1126         FTR_SECTION_ELSE_NESTED(66);                    \
1127         mfspr   rX,SPRN_SPRG_HPACA;                     \
1128         ALT_FTR_SECTION_END_NESTED_IFCLR(CPU_FTR_HVMODE, 66)
1129 
1130 #define SET_PACA(rX)                                    \
1131         BEGIN_FTR_SECTION_NESTED(66);                   \
1132         mtspr   SPRN_SPRG_PACA,rX;                      \
1133         FTR_SECTION_ELSE_NESTED(66);                    \
1134         mtspr   SPRN_SPRG_HPACA,rX;                     \
1135         ALT_FTR_SECTION_END_NESTED_IFCLR(CPU_FTR_HVMODE, 66)
1136 
1137 #define GET_SCRATCH0(rX)                                \
1138         BEGIN_FTR_SECTION_NESTED(66);                   \
1139         mfspr   rX,SPRN_SPRG_SCRATCH0;                  \
1140         FTR_SECTION_ELSE_NESTED(66);                    \
1141         mfspr   rX,SPRN_SPRG_HSCRATCH0;                 \
1142         ALT_FTR_SECTION_END_NESTED_IFCLR(CPU_FTR_HVMODE, 66)
1143 
1144 #define SET_SCRATCH0(rX)                                \
1145         BEGIN_FTR_SECTION_NESTED(66);                   \
1146         mtspr   SPRN_SPRG_SCRATCH0,rX;                  \
1147         FTR_SECTION_ELSE_NESTED(66);                    \
1148         mtspr   SPRN_SPRG_HSCRATCH0,rX;                 \
1149         ALT_FTR_SECTION_END_NESTED_IFCLR(CPU_FTR_HVMODE, 66)
1150 
1151 #else /* CONFIG_PPC_BOOK3S_64 */
1152 #define GET_SCRATCH0(rX)        mfspr   rX,SPRN_SPRG_SCRATCH0
1153 #define SET_SCRATCH0(rX)        mtspr   SPRN_SPRG_SCRATCH0,rX
1154 
1155 #endif
1156 
1157 #ifdef CONFIG_PPC_BOOK3E_64
1158 #define SPRN_SPRG_MC_SCRATCH    SPRN_SPRG8
1159 #define SPRN_SPRG_CRIT_SCRATCH  SPRN_SPRG3
1160 #define SPRN_SPRG_DBG_SCRATCH   SPRN_SPRG9
1161 #define SPRN_SPRG_TLB_EXFRAME   SPRN_SPRG2
1162 #define SPRN_SPRG_TLB_SCRATCH   SPRN_SPRG6
1163 #define SPRN_SPRG_GEN_SCRATCH   SPRN_SPRG0
1164 #define SPRN_SPRG_GDBELL_SCRATCH SPRN_SPRG_GEN_SCRATCH
1165 #define SPRN_SPRG_VDSO_READ     SPRN_USPRG7
1166 #define SPRN_SPRG_VDSO_WRITE    SPRN_SPRG7
1167 
1168 #define SET_PACA(rX)    mtspr   SPRN_SPRG_PACA,rX
1169 #define GET_PACA(rX)    mfspr   rX,SPRN_SPRG_PACA
1170 
1171 #endif
1172 
1173 #ifdef CONFIG_PPC_BOOK3S_32
1174 #define SPRN_SPRG_SCRATCH0      SPRN_SPRG0
1175 #define SPRN_SPRG_SCRATCH1      SPRN_SPRG1
1176 #define SPRN_SPRG_PGDIR         SPRN_SPRG2
1177 #define SPRN_SPRG_603_LRU       SPRN_SPRG4
1178 #endif
1179 
1180 #ifdef CONFIG_40x
1181 #define SPRN_SPRG_SCRATCH0      SPRN_SPRG0
1182 #define SPRN_SPRG_SCRATCH1      SPRN_SPRG1
1183 #define SPRN_SPRG_SCRATCH2      SPRN_SPRG2
1184 #define SPRN_SPRG_SCRATCH3      SPRN_SPRG4
1185 #define SPRN_SPRG_SCRATCH4      SPRN_SPRG5
1186 #define SPRN_SPRG_SCRATCH5      SPRN_SPRG6
1187 #define SPRN_SPRG_SCRATCH6      SPRN_SPRG7
1188 #endif
1189 
1190 #ifdef CONFIG_BOOKE
1191 #define SPRN_SPRG_RSCRATCH0     SPRN_SPRG0
1192 #define SPRN_SPRG_WSCRATCH0     SPRN_SPRG0
1193 #define SPRN_SPRG_RSCRATCH1     SPRN_SPRG1
1194 #define SPRN_SPRG_WSCRATCH1     SPRN_SPRG1
1195 #define SPRN_SPRG_RSCRATCH_CRIT SPRN_SPRG2
1196 #define SPRN_SPRG_WSCRATCH_CRIT SPRN_SPRG2
1197 #define SPRN_SPRG_RSCRATCH2     SPRN_SPRG4R
1198 #define SPRN_SPRG_WSCRATCH2     SPRN_SPRG4W
1199 #define SPRN_SPRG_RSCRATCH3     SPRN_SPRG5R
1200 #define SPRN_SPRG_WSCRATCH3     SPRN_SPRG5W
1201 #define SPRN_SPRG_RSCRATCH_MC   SPRN_SPRG1
1202 #define SPRN_SPRG_WSCRATCH_MC   SPRN_SPRG1
1203 #define SPRN_SPRG_RSCRATCH4     SPRN_SPRG7R
1204 #define SPRN_SPRG_WSCRATCH4     SPRN_SPRG7W
1205 #ifdef CONFIG_E200
1206 #define SPRN_SPRG_RSCRATCH_DBG  SPRN_SPRG6R
1207 #define SPRN_SPRG_WSCRATCH_DBG  SPRN_SPRG6W
1208 #else
1209 #define SPRN_SPRG_RSCRATCH_DBG  SPRN_SPRG9
1210 #define SPRN_SPRG_WSCRATCH_DBG  SPRN_SPRG9
1211 #endif
1212 #endif
1213 
1214 #ifdef CONFIG_PPC_8xx
1215 #define SPRN_SPRG_SCRATCH0      SPRN_SPRG0
1216 #define SPRN_SPRG_SCRATCH1      SPRN_SPRG1
1217 #define SPRN_SPRG_SCRATCH2      SPRN_SPRG2
1218 #endif
1219 
1220 
1221 
1222 /*
1223  * An mtfsf instruction with the L bit set. On CPUs that support this a
1224  * full 64bits of FPSCR is restored and on other CPUs the L bit is ignored.
1225  *
1226  * Until binutils gets the new form of mtfsf, hardwire the instruction.
1227  */
1228 #ifdef CONFIG_PPC64
1229 #define MTFSF_L(REG) \
1230         .long (0xfc00058e | ((0xff) << 17) | ((REG) << 11) | (1 << 25))
1231 #else
1232 #define MTFSF_L(REG)    mtfsf   0xff, (REG)
1233 #endif
1234 
1235 /* Processor Version Register (PVR) field extraction */
1236 
1237 #define PVR_VER(pvr)    (((pvr) >>  16) & 0xFFFF)       /* Version field */
1238 #define PVR_REV(pvr)    (((pvr) >>   0) & 0xFFFF)       /* Revison field */
1239 
1240 #define pvr_version_is(pvr)     (PVR_VER(mfspr(SPRN_PVR)) == (pvr))
1241 
1242 /*
1243  * IBM has further subdivided the standard PowerPC 16-bit version and
1244  * revision subfields of the PVR for the PowerPC 403s into the following:
1245  */
1246 
1247 #define PVR_FAM(pvr)    (((pvr) >> 20) & 0xFFF) /* Family field */
1248 #define PVR_MEM(pvr)    (((pvr) >> 16) & 0xF)   /* Member field */
1249 #define PVR_CORE(pvr)   (((pvr) >> 12) & 0xF)   /* Core field */
1250 #define PVR_CFG(pvr)    (((pvr) >>  8) & 0xF)   /* Configuration field */
1251 #define PVR_MAJ(pvr)    (((pvr) >>  4) & 0xF)   /* Major revision field */
1252 #define PVR_MIN(pvr)    (((pvr) >>  0) & 0xF)   /* Minor revision field */
1253 
1254 /* Processor Version Numbers */
1255 
1256 #define PVR_403GA       0x00200000
1257 #define PVR_403GB       0x00200100
1258 #define PVR_403GC       0x00200200
1259 #define PVR_403GCX      0x00201400
1260 #define PVR_405GP       0x40110000
1261 #define PVR_476         0x11a52000
1262 #define PVR_476FPE      0x7ff50000
1263 #define PVR_STB03XXX    0x40310000
1264 #define PVR_NP405H      0x41410000
1265 #define PVR_NP405L      0x41610000
1266 #define PVR_601         0x00010000
1267 #define PVR_602         0x00050000
1268 #define PVR_603         0x00030000
1269 #define PVR_603e        0x00060000
1270 #define PVR_603ev       0x00070000
1271 #define PVR_603r        0x00071000
1272 #define PVR_604         0x00040000
1273 #define PVR_604e        0x00090000
1274 #define PVR_604r        0x000A0000
1275 #define PVR_620         0x00140000
1276 #define PVR_740         0x00080000
1277 #define PVR_750         PVR_740
1278 #define PVR_740P        0x10080000
1279 #define PVR_750P        PVR_740P
1280 #define PVR_7400        0x000C0000
1281 #define PVR_7410        0x800C0000
1282 #define PVR_7450        0x80000000
1283 #define PVR_8540        0x80200000
1284 #define PVR_8560        0x80200000
1285 #define PVR_VER_E500V1  0x8020
1286 #define PVR_VER_E500V2  0x8021
1287 #define PVR_VER_E500MC  0x8023
1288 #define PVR_VER_E5500   0x8024
1289 #define PVR_VER_E6500   0x8040
1290 
1291 /*
1292  * For the 8xx processors, all of them report the same PVR family for
1293  * the PowerPC core. The various versions of these processors must be
1294  * differentiated by the version number in the Communication Processor
1295  * Module (CPM).
1296  */
1297 #define PVR_8xx         0x00500000
1298 
1299 #define PVR_8240        0x00810100
1300 #define PVR_8245        0x80811014
1301 #define PVR_8260        PVR_8240
1302 
1303 /* 476 Simulator seems to currently have the PVR of the 602... */
1304 #define PVR_476_ISS     0x00052000
1305 
1306 /* 64-bit processors */
1307 #define PVR_NORTHSTAR   0x0033
1308 #define PVR_PULSAR      0x0034
1309 #define PVR_POWER4      0x0035
1310 #define PVR_ICESTAR     0x0036
1311 #define PVR_SSTAR       0x0037
1312 #define PVR_POWER4p     0x0038
1313 #define PVR_970         0x0039
1314 #define PVR_POWER5      0x003A
1315 #define PVR_POWER5p     0x003B
1316 #define PVR_970FX       0x003C
1317 #define PVR_POWER6      0x003E
1318 #define PVR_POWER7      0x003F
1319 #define PVR_630         0x0040
1320 #define PVR_630p        0x0041
1321 #define PVR_970MP       0x0044
1322 #define PVR_970GX       0x0045
1323 #define PVR_POWER7p     0x004A
1324 #define PVR_POWER8E     0x004B
1325 #define PVR_POWER8NVL   0x004C
1326 #define PVR_POWER8      0x004D
1327 #define PVR_POWER9      0x004E
1328 #define PVR_BE          0x0070
1329 #define PVR_PA6T        0x0090
1330 
1331 /* "Logical" PVR values defined in PAPR, representing architecture levels */
1332 #define PVR_ARCH_204    0x0f000001
1333 #define PVR_ARCH_205    0x0f000002
1334 #define PVR_ARCH_206    0x0f000003
1335 #define PVR_ARCH_206p   0x0f100003
1336 #define PVR_ARCH_207    0x0f000004
1337 #define PVR_ARCH_300    0x0f000005
1338 
1339 /* Macros for setting and retrieving special purpose registers */
1340 #ifndef __ASSEMBLY__
1341 #define mfmsr()         ({unsigned long rval; \
1342                         asm volatile("mfmsr %0" : "=r" (rval) : \
1343                                                 : "memory"); rval;})
1344 #ifdef CONFIG_PPC_BOOK3S_64
1345 #define __mtmsrd(v, l)  asm volatile("mtmsrd %0," __stringify(l) \
1346                                      : : "r" (v) : "memory")
1347 #define mtmsr(v)        __mtmsrd((v), 0)
1348 #define __MTMSR         "mtmsrd"
1349 #else
1350 #define mtmsr(v)        asm volatile("mtmsr %0" : \
1351                                      : "r" ((unsigned long)(v)) \
1352                                      : "memory")
1353 #define __MTMSR         "mtmsr"
1354 #endif
1355 
1356 static inline void mtmsr_isync(unsigned long val)
1357 {
1358         asm volatile(__MTMSR " %0; " ASM_FTR_IFCLR("isync", "nop", %1) : :
1359                         "r" (val), "i" (CPU_FTR_ARCH_206) : "memory");
1360 }
1361 
1362 #define mfspr(rn)       ({unsigned long rval; \
1363                         asm volatile("mfspr %0," __stringify(rn) \
1364                                 : "=r" (rval)); rval;})
1365 #ifndef mtspr
1366 #define mtspr(rn, v)    asm volatile("mtspr " __stringify(rn) ",%0" : \
1367                                      : "r" ((unsigned long)(v)) \
1368                                      : "memory")
1369 #endif
1370 #define wrtspr(rn)      asm volatile("mtspr " __stringify(rn) ",0" : \
1371                                      : : "memory")
1372 
1373 extern unsigned long msr_check_and_set(unsigned long bits);
1374 extern bool strict_msr_control;
1375 extern void __msr_check_and_clear(unsigned long bits);
1376 static inline void msr_check_and_clear(unsigned long bits)
1377 {
1378         if (strict_msr_control)
1379                 __msr_check_and_clear(bits);
1380 }
1381 
1382 #ifdef __powerpc64__
1383 #if defined(CONFIG_PPC_CELL) || defined(CONFIG_PPC_FSL_BOOK3E)
1384 #define mftb()          ({unsigned long rval;                           \
1385                         asm volatile(                                   \
1386                                 "90:    mfspr %0, %2;\n"                \
1387                                 "97:    cmpwi %0,0;\n"                  \
1388                                 "       beq- 90b;\n"                    \
1389                                 "99:\n"                                 \
1390                                 ".section __ftr_fixup,\"a\"\n"          \
1391                                 ".align 3\n"                            \
1392                                 "98:\n"                                 \
1393                                 "       .8byte %1\n"                    \
1394                                 "       .8byte %1\n"                    \
1395                                 "       .8byte 97b-98b\n"               \
1396                                 "       .8byte 99b-98b\n"               \
1397                                 "       .8byte 0\n"                     \
1398                                 "       .8byte 0\n"                     \
1399                                 ".previous"                             \
1400                         : "=r" (rval) \
1401                         : "i" (CPU_FTR_CELL_TB_BUG), "i" (SPRN_TBRL) : "cr0"); \
1402                         rval;})
1403 #else
1404 #define mftb()          ({unsigned long rval;   \
1405                         asm volatile("mfspr %0, %1" : \
1406                                      "=r" (rval) : "i" (SPRN_TBRL)); rval;})
1407 #endif /* !CONFIG_PPC_CELL */
1408 
1409 #else /* __powerpc64__ */
1410 
1411 #if defined(CONFIG_PPC_8xx)
1412 #define mftbl()         ({unsigned long rval;   \
1413                         asm volatile("mftbl %0" : "=r" (rval)); rval;})
1414 #define mftbu()         ({unsigned long rval;   \
1415                         asm volatile("mftbu %0" : "=r" (rval)); rval;})
1416 #else
1417 #define mftbl()         ({unsigned long rval;   \
1418                         asm volatile("mfspr %0, %1" : "=r" (rval) : \
1419                                 "i" (SPRN_TBRL)); rval;})
1420 #define mftbu()         ({unsigned long rval;   \
1421                         asm volatile("mfspr %0, %1" : "=r" (rval) : \
1422                                 "i" (SPRN_TBRU)); rval;})
1423 #endif
1424 #define mftb()          mftbl()
1425 #endif /* !__powerpc64__ */
1426 
1427 #define mttbl(v)        asm volatile("mttbl %0":: "r"(v))
1428 #define mttbu(v)        asm volatile("mttbu %0":: "r"(v))
1429 
1430 #ifdef CONFIG_PPC32
1431 #define mfsrin(v)       ({unsigned int rval; \
1432                         asm volatile("mfsrin %0,%1" : "=r" (rval) : "r" (v)); \
1433                                         rval;})
1434 
1435 static inline void mtsrin(u32 val, u32 idx)
1436 {
1437         asm volatile("mtsrin %0, %1" : : "r" (val), "r" (idx));
1438 }
1439 #endif
1440 
1441 #define proc_trap()     asm volatile("trap")
1442 
1443 extern unsigned long current_stack_pointer(void);
1444 
1445 extern unsigned long scom970_read(unsigned int address);
1446 extern void scom970_write(unsigned int address, unsigned long value);
1447 
1448 struct pt_regs;
1449 
1450 extern void ppc_save_regs(struct pt_regs *regs);
1451 
1452 static inline void update_power8_hid0(unsigned long hid0)
1453 {
1454         /*
1455          *  The HID0 update on Power8 should at the very least be
1456          *  preceded by a a SYNC instruction followed by an ISYNC
1457          *  instruction
1458          */
1459         asm volatile("sync; mtspr %0,%1; isync":: "i"(SPRN_HID0), "r"(hid0));
1460 }
1461 #endif /* __ASSEMBLY__ */
1462 #endif /* __KERNEL__ */
1463 #endif /* _ASM_POWERPC_REG_H */
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root/arch/powerpc/include/asm/reg.h

INCLUDED FROM

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