1 /* SPDX-License-Identifier: GPL-2.0 */
2 /*
3 * Definitions for using the Apple Descriptor-Based DMA controller
4 * in Power Macintosh computers.
5 *
6 * Copyright (C) 1996 Paul Mackerras.
7 */
8
9 #ifdef __KERNEL__
10 #ifndef _ASM_DBDMA_H_
11 #define _ASM_DBDMA_H_
12 /*
13 * DBDMA control/status registers. All little-endian.
14 */
15 struct dbdma_regs {
16 unsigned int control; /* lets you change bits in status */
17 unsigned int status; /* DMA and device status bits (see below) */
18 unsigned int cmdptr_hi; /* upper 32 bits of command address */
19 unsigned int cmdptr; /* (lower 32 bits of) command address (phys) */
20 unsigned int intr_sel; /* select interrupt condition bit */
21 unsigned int br_sel; /* select branch condition bit */
22 unsigned int wait_sel; /* select wait condition bit */
23 unsigned int xfer_mode;
24 unsigned int data2ptr_hi;
25 unsigned int data2ptr;
26 unsigned int res1;
27 unsigned int address_hi;
28 unsigned int br_addr_hi;
29 unsigned int res2[3];
30 };
31
32 /* Bits in control and status registers */
33 #define RUN 0x8000
34 #define PAUSE 0x4000
35 #define FLUSH 0x2000
36 #define WAKE 0x1000
37 #define DEAD 0x0800
38 #define ACTIVE 0x0400
39 #define BT 0x0100
40 #define DEVSTAT 0x00ff
41
42 /*
43 * DBDMA command structure. These fields are all little-endian!
44 */
45 struct dbdma_cmd {
46 __le16 req_count; /* requested byte transfer count */
47 __le16 command; /* command word (has bit-fields) */
48 __le32 phy_addr; /* physical data address */
49 __le32 cmd_dep; /* command-dependent field */
50 __le16 res_count; /* residual count after completion */
51 __le16 xfer_status; /* transfer status */
52 };
53
54 /* DBDMA command values in command field */
55 #define OUTPUT_MORE 0 /* transfer memory data to stream */
56 #define OUTPUT_LAST 0x1000 /* ditto followed by end marker */
57 #define INPUT_MORE 0x2000 /* transfer stream data to memory */
58 #define INPUT_LAST 0x3000 /* ditto, expect end marker */
59 #define STORE_WORD 0x4000 /* write word (4 bytes) to device reg */
60 #define LOAD_WORD 0x5000 /* read word (4 bytes) from device reg */
61 #define DBDMA_NOP 0x6000 /* do nothing */
62 #define DBDMA_STOP 0x7000 /* suspend processing */
63
64 /* Key values in command field */
65 #define KEY_STREAM0 0 /* usual data stream */
66 #define KEY_STREAM1 0x100 /* control/status stream */
67 #define KEY_STREAM2 0x200 /* device-dependent stream */
68 #define KEY_STREAM3 0x300 /* device-dependent stream */
69 #define KEY_REGS 0x500 /* device register space */
70 #define KEY_SYSTEM 0x600 /* system memory-mapped space */
71 #define KEY_DEVICE 0x700 /* device memory-mapped space */
72
73 /* Interrupt control values in command field */
74 #define INTR_NEVER 0 /* don't interrupt */
75 #define INTR_IFSET 0x10 /* intr if condition bit is 1 */
76 #define INTR_IFCLR 0x20 /* intr if condition bit is 0 */
77 #define INTR_ALWAYS 0x30 /* always interrupt */
78
79 /* Branch control values in command field */
80 #define BR_NEVER 0 /* don't branch */
81 #define BR_IFSET 0x4 /* branch if condition bit is 1 */
82 #define BR_IFCLR 0x8 /* branch if condition bit is 0 */
83 #define BR_ALWAYS 0xc /* always branch */
84
85 /* Wait control values in command field */
86 #define WAIT_NEVER 0 /* don't wait */
87 #define WAIT_IFSET 1 /* wait if condition bit is 1 */
88 #define WAIT_IFCLR 2 /* wait if condition bit is 0 */
89 #define WAIT_ALWAYS 3 /* always wait */
90
91 /* Align an address for a DBDMA command structure */
92 #define DBDMA_ALIGN(x) (((unsigned long)(x) + sizeof(struct dbdma_cmd) - 1) \
93 & -sizeof(struct dbdma_cmd))
94
95 /* Useful macros */
96 #define DBDMA_DO_STOP(regs) do { \
97 out_le32(&((regs)->control), (RUN|FLUSH)<<16); \
98 while(in_le32(&((regs)->status)) & (ACTIVE|FLUSH)) \
99 ; \
100 } while(0)
101
102 #define DBDMA_DO_RESET(regs) do { \
103 out_le32(&((regs)->control), (ACTIVE|DEAD|WAKE|FLUSH|PAUSE|RUN)<<16);\
104 while(in_le32(&((regs)->status)) & (RUN)) \
105 ; \
106 } while(0)
107
108 #endif /* _ASM_DBDMA_H_ */
109 #endif /* __KERNEL__ */