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7 #ifndef _ASM_POWERPC_EXCEPTION_64E_H
8 #define _ASM_POWERPC_EXCEPTION_64E_H
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36 #define PACA_EXGDBELL PACA_EXGEN
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41 #define EX_R1 (0 * 8)
42 #define EX_CR (1 * 8)
43 #define EX_R10 (2 * 8)
44 #define EX_R11 (3 * 8)
45 #define EX_R14 (4 * 8)
46 #define EX_R15 (5 * 8)
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56 #define EX_TLB_R10 ( 0 * 8)
57 #define EX_TLB_R11 ( 1 * 8)
58 #define EX_TLB_R14 ( 2 * 8)
59 #define EX_TLB_R15 ( 3 * 8)
60 #define EX_TLB_R16 ( 4 * 8)
61 #define EX_TLB_CR ( 5 * 8)
62 #define EX_TLB_R12 ( 6 * 8)
63 #define EX_TLB_R13 ( 7 * 8)
64 #define EX_TLB_DEAR ( 8 * 8)
65 #define EX_TLB_ESR ( 9 * 8)
66 #define EX_TLB_SRR0 (10 * 8)
67 #define EX_TLB_SRR1 (11 * 8)
68 #define EX_TLB_R7 (12 * 8)
69 #ifdef CONFIG_BOOK3E_MMU_TLB_STATS
70 #define EX_TLB_R8 (13 * 8)
71 #define EX_TLB_R9 (14 * 8)
72 #define EX_TLB_LR (15 * 8)
73 #define EX_TLB_SIZE (16 * 8)
74 #else
75 #define EX_TLB_SIZE (13 * 8)
76 #endif
77
78 #define START_EXCEPTION(label) \
79 .globl exc_##label##_book3e; \
80 exc_##label##_book3e:
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94 #define TLB_MISS_PROLOG \
95 mtspr SPRN_SPRG_TLB_SCRATCH,r12; \
96 mfspr r12,SPRN_SPRG_TLB_EXFRAME; \
97 std r10,EX_TLB_R10(r12); \
98 mfcr r10; \
99 std r11,EX_TLB_R11(r12); \
100 mfspr r11,SPRN_SPRG_TLB_SCRATCH; \
101 std r13,EX_TLB_R13(r12); \
102 mfspr r13,SPRN_SPRG_PACA; \
103 std r14,EX_TLB_R14(r12); \
104 addi r14,r12,EX_TLB_SIZE; \
105 std r15,EX_TLB_R15(r12); \
106 mfspr r15,SPRN_SRR1; \
107 std r16,EX_TLB_R16(r12); \
108 mfspr r16,SPRN_SRR0; \
109 std r10,EX_TLB_CR(r12); \
110 std r11,EX_TLB_R12(r12); \
111 mtspr SPRN_SPRG_TLB_EXFRAME,r14; \
112 std r15,EX_TLB_SRR1(r12); \
113 std r16,EX_TLB_SRR0(r12); \
114 TLB_MISS_PROLOG_STATS
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133 #define TLB_MISS_RESTORE(freg) \
134 ld r14,EX_TLB_CR(r12); \
135 ld r10,EX_TLB_R10(r12); \
136 ld r15,EX_TLB_SRR0(r12); \
137 ld r16,EX_TLB_SRR1(r12); \
138 mtspr SPRN_SPRG_TLB_EXFRAME,freg; \
139 ld r11,EX_TLB_R11(r12); \
140 mtcr r14; \
141 ld r13,EX_TLB_R13(r12); \
142 ld r14,EX_TLB_R14(r12); \
143 mtspr SPRN_SRR0,r15; \
144 ld r15,EX_TLB_R15(r12); \
145 mtspr SPRN_SRR1,r16; \
146 TLB_MISS_RESTORE_STATS \
147 ld r16,EX_TLB_R16(r12); \
148 ld r12,EX_TLB_R12(r12); \
149
150 #define TLB_MISS_EPILOG_SUCCESS \
151 TLB_MISS_RESTORE(r12)
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153 #define TLB_MISS_EPILOG_ERROR \
154 addi r12,r13,PACA_EXTLB; \
155 TLB_MISS_RESTORE(r12)
156
157 #define TLB_MISS_EPILOG_ERROR_SPECIAL \
158 addi r11,r13,PACA_EXTLB; \
159 TLB_MISS_RESTORE(r11)
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161 #ifdef CONFIG_BOOK3E_MMU_TLB_STATS
162 #define TLB_MISS_PROLOG_STATS \
163 mflr r10; \
164 std r8,EX_TLB_R8(r12); \
165 std r9,EX_TLB_R9(r12); \
166 std r10,EX_TLB_LR(r12);
167 #define TLB_MISS_RESTORE_STATS \
168 ld r16,EX_TLB_LR(r12); \
169 ld r9,EX_TLB_R9(r12); \
170 ld r8,EX_TLB_R8(r12); \
171 mtlr r16;
172 #define TLB_MISS_STATS_D(name) \
173 addi r9,r13,MMSTAT_DSTATS+name; \
174 bl tlb_stat_inc;
175 #define TLB_MISS_STATS_I(name) \
176 addi r9,r13,MMSTAT_ISTATS+name; \
177 bl tlb_stat_inc;
178 #define TLB_MISS_STATS_X(name) \
179 ld r8,PACA_EXTLB+EX_TLB_ESR(r13); \
180 cmpdi cr2,r8,-1; \
181 beq cr2,61f; \
182 addi r9,r13,MMSTAT_DSTATS+name; \
183 b 62f; \
184 61: addi r9,r13,MMSTAT_ISTATS+name; \
185 62: bl tlb_stat_inc;
186 #define TLB_MISS_STATS_SAVE_INFO \
187 std r14,EX_TLB_ESR(r12);
188 #define TLB_MISS_STATS_SAVE_INFO_BOLTED \
189 std r14,PACA_EXTLB+EX_TLB_ESR(r13);
190 #else
191 #define TLB_MISS_PROLOG_STATS
192 #define TLB_MISS_RESTORE_STATS
193 #define TLB_MISS_PROLOG_STATS_BOLTED
194 #define TLB_MISS_RESTORE_STATS_BOLTED
195 #define TLB_MISS_STATS_D(name)
196 #define TLB_MISS_STATS_I(name)
197 #define TLB_MISS_STATS_X(name)
198 #define TLB_MISS_STATS_Y(name)
199 #define TLB_MISS_STATS_SAVE_INFO
200 #define TLB_MISS_STATS_SAVE_INFO_BOLTED
201 #endif
202
203 #define SET_IVOR(vector_number, vector_offset) \
204 LOAD_REG_ADDR(r3,interrupt_base_book3e);\
205 ori r3,r3,vector_offset@l; \
206 mtspr SPRN_IVOR##vector_number,r3;
207
208 #define RFI_TO_KERNEL \
209 rfi
210
211 #define RFI_TO_USER \
212 rfi
213
214 #endif
215