1 /* SPDX-License-Identifier: GPL-2.0 */
2 #ifndef _ASM_POWERPC_DMA_H
3 #define _ASM_POWERPC_DMA_H
4 #ifdef __KERNEL__
5
6 /*
7 * Defines for using and allocating dma channels.
8 * Written by Hennus Bergman, 1992.
9 * High DMA channel support & info by Hannu Savolainen
10 * and John Boyd, Nov. 1992.
11 * Changes for ppc sound by Christoph Nadig
12 */
13
14 /*
15 * Note: Adapted for PowerPC by Gary Thomas
16 * Modified by Cort Dougan <cort@cs.nmt.edu>
17 *
18 * None of this really applies for Power Macintoshes. There is
19 * basically just enough here to get kernel/dma.c to compile.
20 */
21
22 #include <asm/io.h>
23 #include <linux/spinlock.h>
24
25 #ifndef MAX_DMA_CHANNELS
26 #define MAX_DMA_CHANNELS 8
27 #endif
28
29 /* The maximum address that we can perform a DMA transfer to on this platform */
30 /* Doesn't really apply... */
31 #define MAX_DMA_ADDRESS (~0UL)
32
33 #ifdef HAVE_REALLY_SLOW_DMA_CONTROLLER
34 #define dma_outb outb_p
35 #else
36 #define dma_outb outb
37 #endif
38
39 #define dma_inb inb
40
41 /*
42 * NOTES about DMA transfers:
43 *
44 * controller 1: channels 0-3, byte operations, ports 00-1F
45 * controller 2: channels 4-7, word operations, ports C0-DF
46 *
47 * - ALL registers are 8 bits only, regardless of transfer size
48 * - channel 4 is not used - cascades 1 into 2.
49 * - channels 0-3 are byte - addresses/counts are for physical bytes
50 * - channels 5-7 are word - addresses/counts are for physical words
51 * - transfers must not cross physical 64K (0-3) or 128K (5-7) boundaries
52 * - transfer count loaded to registers is 1 less than actual count
53 * - controller 2 offsets are all even (2x offsets for controller 1)
54 * - page registers for 5-7 don't use data bit 0, represent 128K pages
55 * - page registers for 0-3 use bit 0, represent 64K pages
56 *
57 * On CHRP, the W83C553F (and VLSI Tollgate?) support full 32 bit addressing.
58 * Note that addresses loaded into registers must be _physical_ addresses,
59 * not logical addresses (which may differ if paging is active).
60 *
61 * Address mapping for channels 0-3:
62 *
63 * A23 ... A16 A15 ... A8 A7 ... A0 (Physical addresses)
64 * | ... | | ... | | ... |
65 * | ... | | ... | | ... |
66 * | ... | | ... | | ... |
67 * P7 ... P0 A7 ... A0 A7 ... A0
68 * | Page | Addr MSB | Addr LSB | (DMA registers)
69 *
70 * Address mapping for channels 5-7:
71 *
72 * A23 ... A17 A16 A15 ... A9 A8 A7 ... A1 A0 (Physical addresses)
73 * | ... | \ \ ... \ \ \ ... \ \
74 * | ... | \ \ ... \ \ \ ... \ (not used)
75 * | ... | \ \ ... \ \ \ ... \
76 * P7 ... P1 (0) A7 A6 ... A0 A7 A6 ... A0
77 * | Page | Addr MSB | Addr LSB | (DMA registers)
78 *
79 * Again, channels 5-7 transfer _physical_ words (16 bits), so addresses
80 * and counts _must_ be word-aligned (the lowest address bit is _ignored_ at
81 * the hardware level, so odd-byte transfers aren't possible).
82 *
83 * Transfer count (_not # bytes_) is limited to 64K, represented as actual
84 * count - 1 : 64K => 0xFFFF, 1 => 0x0000. Thus, count is always 1 or more,
85 * and up to 128K bytes may be transferred on channels 5-7 in one operation.
86 *
87 */
88
89 /* 8237 DMA controllers */
90 #define IO_DMA1_BASE 0x00 /* 8 bit slave DMA, channels 0..3 */
91 #define IO_DMA2_BASE 0xC0 /* 16 bit master DMA, ch 4(=slave input)..7 */
92
93 /* DMA controller registers */
94 #define DMA1_CMD_REG 0x08 /* command register (w) */
95 #define DMA1_STAT_REG 0x08 /* status register (r) */
96 #define DMA1_REQ_REG 0x09 /* request register (w) */
97 #define DMA1_MASK_REG 0x0A /* single-channel mask (w) */
98 #define DMA1_MODE_REG 0x0B /* mode register (w) */
99 #define DMA1_CLEAR_FF_REG 0x0C /* clear pointer flip-flop (w) */
100 #define DMA1_TEMP_REG 0x0D /* Temporary Register (r) */
101 #define DMA1_RESET_REG 0x0D /* Master Clear (w) */
102 #define DMA1_CLR_MASK_REG 0x0E /* Clear Mask */
103 #define DMA1_MASK_ALL_REG 0x0F /* all-channels mask (w) */
104
105 #define DMA2_CMD_REG 0xD0 /* command register (w) */
106 #define DMA2_STAT_REG 0xD0 /* status register (r) */
107 #define DMA2_REQ_REG 0xD2 /* request register (w) */
108 #define DMA2_MASK_REG 0xD4 /* single-channel mask (w) */
109 #define DMA2_MODE_REG 0xD6 /* mode register (w) */
110 #define DMA2_CLEAR_FF_REG 0xD8 /* clear pointer flip-flop (w) */
111 #define DMA2_TEMP_REG 0xDA /* Temporary Register (r) */
112 #define DMA2_RESET_REG 0xDA /* Master Clear (w) */
113 #define DMA2_CLR_MASK_REG 0xDC /* Clear Mask */
114 #define DMA2_MASK_ALL_REG 0xDE /* all-channels mask (w) */
115
116 #define DMA_ADDR_0 0x00 /* DMA address registers */
117 #define DMA_ADDR_1 0x02
118 #define DMA_ADDR_2 0x04
119 #define DMA_ADDR_3 0x06
120 #define DMA_ADDR_4 0xC0
121 #define DMA_ADDR_5 0xC4
122 #define DMA_ADDR_6 0xC8
123 #define DMA_ADDR_7 0xCC
124
125 #define DMA_CNT_0 0x01 /* DMA count registers */
126 #define DMA_CNT_1 0x03
127 #define DMA_CNT_2 0x05
128 #define DMA_CNT_3 0x07
129 #define DMA_CNT_4 0xC2
130 #define DMA_CNT_5 0xC6
131 #define DMA_CNT_6 0xCA
132 #define DMA_CNT_7 0xCE
133
134 #define DMA_LO_PAGE_0 0x87 /* DMA page registers */
135 #define DMA_LO_PAGE_1 0x83
136 #define DMA_LO_PAGE_2 0x81
137 #define DMA_LO_PAGE_3 0x82
138 #define DMA_LO_PAGE_5 0x8B
139 #define DMA_LO_PAGE_6 0x89
140 #define DMA_LO_PAGE_7 0x8A
141
142 #define DMA_HI_PAGE_0 0x487 /* DMA page registers */
143 #define DMA_HI_PAGE_1 0x483
144 #define DMA_HI_PAGE_2 0x481
145 #define DMA_HI_PAGE_3 0x482
146 #define DMA_HI_PAGE_5 0x48B
147 #define DMA_HI_PAGE_6 0x489
148 #define DMA_HI_PAGE_7 0x48A
149
150 #define DMA1_EXT_REG 0x40B
151 #define DMA2_EXT_REG 0x4D6
152
153 #ifndef __powerpc64__
154 /* in arch/ppc/kernel/setup.c -- Cort */
155 extern unsigned int DMA_MODE_WRITE;
156 extern unsigned int DMA_MODE_READ;
157 extern unsigned long ISA_DMA_THRESHOLD;
158 #else
159 #define DMA_MODE_READ 0x44 /* I/O to memory, no autoinit, increment, single mode */
160 #define DMA_MODE_WRITE 0x48 /* memory to I/O, no autoinit, increment, single mode */
161 #endif
162
163 #define DMA_MODE_CASCADE 0xC0 /* pass thru DREQ->HRQ, DACK<-HLDA only */
164
165 #define DMA_AUTOINIT 0x10
166
167 extern spinlock_t dma_spin_lock;
168
169 static __inline__ unsigned long claim_dma_lock(void)
170 {
171 unsigned long flags;
172 spin_lock_irqsave(&dma_spin_lock, flags);
173 return flags;
174 }
175
176 static __inline__ void release_dma_lock(unsigned long flags)
177 {
178 spin_unlock_irqrestore(&dma_spin_lock, flags);
179 }
180
181 /* enable/disable a specific DMA channel */
182 static __inline__ void enable_dma(unsigned int dmanr)
183 {
184 unsigned char ucDmaCmd = 0x00;
185
186 if (dmanr != 4) {
187 dma_outb(0, DMA2_MASK_REG); /* This may not be enabled */
188 dma_outb(ucDmaCmd, DMA2_CMD_REG); /* Enable group */
189 }
190 if (dmanr <= 3) {
191 dma_outb(dmanr, DMA1_MASK_REG);
192 dma_outb(ucDmaCmd, DMA1_CMD_REG); /* Enable group */
193 } else {
194 dma_outb(dmanr & 3, DMA2_MASK_REG);
195 }
196 }
197
198 static __inline__ void disable_dma(unsigned int dmanr)
199 {
200 if (dmanr <= 3)
201 dma_outb(dmanr | 4, DMA1_MASK_REG);
202 else
203 dma_outb((dmanr & 3) | 4, DMA2_MASK_REG);
204 }
205
206 /* Clear the 'DMA Pointer Flip Flop'.
207 * Write 0 for LSB/MSB, 1 for MSB/LSB access.
208 * Use this once to initialize the FF to a known state.
209 * After that, keep track of it. :-)
210 * --- In order to do that, the DMA routines below should ---
211 * --- only be used while interrupts are disabled! ---
212 */
213 static __inline__ void clear_dma_ff(unsigned int dmanr)
214 {
215 if (dmanr <= 3)
216 dma_outb(0, DMA1_CLEAR_FF_REG);
217 else
218 dma_outb(0, DMA2_CLEAR_FF_REG);
219 }
220
221 /* set mode (above) for a specific DMA channel */
222 static __inline__ void set_dma_mode(unsigned int dmanr, char mode)
223 {
224 if (dmanr <= 3)
225 dma_outb(mode | dmanr, DMA1_MODE_REG);
226 else
227 dma_outb(mode | (dmanr & 3), DMA2_MODE_REG);
228 }
229
230 /* Set only the page register bits of the transfer address.
231 * This is used for successive transfers when we know the contents of
232 * the lower 16 bits of the DMA current address register, but a 64k boundary
233 * may have been crossed.
234 */
235 static __inline__ void set_dma_page(unsigned int dmanr, int pagenr)
236 {
237 switch (dmanr) {
238 case 0:
239 dma_outb(pagenr, DMA_LO_PAGE_0);
240 dma_outb(pagenr >> 8, DMA_HI_PAGE_0);
241 break;
242 case 1:
243 dma_outb(pagenr, DMA_LO_PAGE_1);
244 dma_outb(pagenr >> 8, DMA_HI_PAGE_1);
245 break;
246 case 2:
247 dma_outb(pagenr, DMA_LO_PAGE_2);
248 dma_outb(pagenr >> 8, DMA_HI_PAGE_2);
249 break;
250 case 3:
251 dma_outb(pagenr, DMA_LO_PAGE_3);
252 dma_outb(pagenr >> 8, DMA_HI_PAGE_3);
253 break;
254 case 5:
255 dma_outb(pagenr & 0xfe, DMA_LO_PAGE_5);
256 dma_outb(pagenr >> 8, DMA_HI_PAGE_5);
257 break;
258 case 6:
259 dma_outb(pagenr & 0xfe, DMA_LO_PAGE_6);
260 dma_outb(pagenr >> 8, DMA_HI_PAGE_6);
261 break;
262 case 7:
263 dma_outb(pagenr & 0xfe, DMA_LO_PAGE_7);
264 dma_outb(pagenr >> 8, DMA_HI_PAGE_7);
265 break;
266 }
267 }
268
269 /* Set transfer address & page bits for specific DMA channel.
270 * Assumes dma flipflop is clear.
271 */
272 static __inline__ void set_dma_addr(unsigned int dmanr, unsigned int phys)
273 {
274 if (dmanr <= 3) {
275 dma_outb(phys & 0xff,
276 ((dmanr & 3) << 1) + IO_DMA1_BASE);
277 dma_outb((phys >> 8) & 0xff,
278 ((dmanr & 3) << 1) + IO_DMA1_BASE);
279 } else {
280 dma_outb((phys >> 1) & 0xff,
281 ((dmanr & 3) << 2) + IO_DMA2_BASE);
282 dma_outb((phys >> 9) & 0xff,
283 ((dmanr & 3) << 2) + IO_DMA2_BASE);
284 }
285 set_dma_page(dmanr, phys >> 16);
286 }
287
288
289 /* Set transfer size (max 64k for DMA1..3, 128k for DMA5..7) for
290 * a specific DMA channel.
291 * You must ensure the parameters are valid.
292 * NOTE: from a manual: "the number of transfers is one more
293 * than the initial word count"! This is taken into account.
294 * Assumes dma flip-flop is clear.
295 * NOTE 2: "count" represents _bytes_ and must be even for channels 5-7.
296 */
297 static __inline__ void set_dma_count(unsigned int dmanr, unsigned int count)
298 {
299 count--;
300 if (dmanr <= 3) {
301 dma_outb(count & 0xff,
302 ((dmanr & 3) << 1) + 1 + IO_DMA1_BASE);
303 dma_outb((count >> 8) & 0xff,
304 ((dmanr & 3) << 1) + 1 + IO_DMA1_BASE);
305 } else {
306 dma_outb((count >> 1) & 0xff,
307 ((dmanr & 3) << 2) + 2 + IO_DMA2_BASE);
308 dma_outb((count >> 9) & 0xff,
309 ((dmanr & 3) << 2) + 2 + IO_DMA2_BASE);
310 }
311 }
312
313
314 /* Get DMA residue count. After a DMA transfer, this
315 * should return zero. Reading this while a DMA transfer is
316 * still in progress will return unpredictable results.
317 * If called before the channel has been used, it may return 1.
318 * Otherwise, it returns the number of _bytes_ left to transfer.
319 *
320 * Assumes DMA flip-flop is clear.
321 */
322 static __inline__ int get_dma_residue(unsigned int dmanr)
323 {
324 unsigned int io_port = (dmanr <= 3)
325 ? ((dmanr & 3) << 1) + 1 + IO_DMA1_BASE
326 : ((dmanr & 3) << 2) + 2 + IO_DMA2_BASE;
327
328 /* using short to get 16-bit wrap around */
329 unsigned short count;
330
331 count = 1 + dma_inb(io_port);
332 count += dma_inb(io_port) << 8;
333
334 return (dmanr <= 3) ? count : (count << 1);
335 }
336
337 /* These are in kernel/dma.c: */
338
339 /* reserve a DMA channel */
340 extern int request_dma(unsigned int dmanr, const char *device_id);
341 /* release it again */
342 extern void free_dma(unsigned int dmanr);
343
344 #ifdef CONFIG_PCI
345 extern int isa_dma_bridge_buggy;
346 #else
347 #define isa_dma_bridge_buggy (0)
348 #endif
349
350 #endif /* __KERNEL__ */
351 #endif /* _ASM_POWERPC_DMA_H */