This source file includes following definitions.
- L2_CACHE_SET
- L2_CACHE_WAY
- L2_CACHE_LINE_SIZE
- GET_L2CC_CTRL_CPU
- SET_L2CC_CTRL_CPU
- GET_L2CC_STATUS_CPU
1
2
3
4 #ifndef L2_CACHE_H
5 #define L2_CACHE_H
6
7
8 #define L2_CA_CONF_OFF 0x0
9 #define L2_IF_CONF_OFF 0x4
10 #define L2CC_SETUP_OFF 0x8
11 #define L2CC_PROT_OFF 0xC
12 #define L2CC_CTRL_OFF 0x10
13 #define L2_INT_EN_OFF 0x20
14 #define L2_STA_OFF 0x24
15 #define RDERR_ADDR_OFF 0x28
16 #define WRERR_ADDR_OFF 0x2c
17 #define EVDPTERR_ADDR_OFF 0x30
18 #define IMPL3ERR_ADDR_OFF 0x34
19 #define L2_CNT0_CTRL_OFF 0x40
20 #define L2_EVNT_CNT0_OFF 0x44
21 #define L2_CNT1_CTRL_OFF 0x48
22 #define L2_EVNT_CNT1_OFF 0x4c
23 #define L2_CCTL_CMD_OFF 0x60
24 #define L2_CCTL_STATUS_OFF 0x64
25 #define L2_LINE_TAG_OFF 0x68
26 #define L2_LINE_DPT_OFF 0x70
27
28 #define CCTL_CMD_L2_IX_INVAL 0x0
29 #define CCTL_CMD_L2_PA_INVAL 0x1
30 #define CCTL_CMD_L2_IX_WB 0x2
31 #define CCTL_CMD_L2_PA_WB 0x3
32 #define CCTL_CMD_L2_PA_WBINVAL 0x5
33 #define CCTL_CMD_L2_SYNC 0xa
34
35
36 #define CCTL_SINGLE_CMD 0
37 #define CCTL_BLOCK_CMD 0x10
38 #define CCTL_ALL_CMD 0x10
39
40
41
42
43 #define L2_CA_CONF_offL2SET 0
44 #define L2_CA_CONF_offL2WAY 4
45 #define L2_CA_CONF_offL2CLSZ 8
46 #define L2_CA_CONF_offL2DW 11
47 #define L2_CA_CONF_offL2PT 14
48 #define L2_CA_CONF_offL2VER 16
49
50 #define L2_CA_CONF_mskL2SET (0xFUL << L2_CA_CONF_offL2SET)
51 #define L2_CA_CONF_mskL2WAY (0xFUL << L2_CA_CONF_offL2WAY)
52 #define L2_CA_CONF_mskL2CLSZ (0x7UL << L2_CA_CONF_offL2CLSZ)
53 #define L2_CA_CONF_mskL2DW (0x7UL << L2_CA_CONF_offL2DW)
54 #define L2_CA_CONF_mskL2PT (0x3UL << L2_CA_CONF_offL2PT)
55 #define L2_CA_CONF_mskL2VER (0xFFFFUL << L2_CA_CONF_offL2VER)
56
57
58
59
60 #define L2CC_SETUP_offPART 0
61 #define L2CC_SETUP_mskPART (0x3UL << L2CC_SETUP_offPART)
62 #define L2CC_SETUP_offDDLATC 4
63 #define L2CC_SETUP_mskDDLATC (0x3UL << L2CC_SETUP_offDDLATC)
64 #define L2CC_SETUP_offTDLATC 8
65 #define L2CC_SETUP_mskTDLATC (0x3UL << L2CC_SETUP_offTDLATC)
66
67
68
69
70 #define L2CC_PROT_offMRWEN 31
71 #define L2CC_PROT_mskMRWEN (0x1UL << L2CC_PROT_offMRWEN)
72
73
74
75
76 #define L2CC_CTRL_offEN 31
77 #define L2CC_CTRL_mskEN (0x1UL << L2CC_CTRL_offEN)
78
79
80
81
82 #define L2_CCTL_STATUS_offCMD_COMP 31
83 #define L2_CCTL_STATUS_mskCMD_COMP (0x1 << L2_CCTL_STATUS_offCMD_COMP)
84
85 extern void __iomem *atl2c_base;
86 #include <linux/smp.h>
87 #include <asm/io.h>
88 #include <asm/bitfield.h>
89
90 #define L2C_R_REG(offset) readl(atl2c_base + offset)
91 #define L2C_W_REG(offset, value) writel(value, atl2c_base + offset)
92
93 #define L2_CMD_RDY() \
94 do{;}while((L2C_R_REG(L2_CCTL_STATUS_OFF) & L2_CCTL_STATUS_mskCMD_COMP) == 0)
95
96 static inline unsigned long L2_CACHE_SET(void)
97 {
98 return 64 << ((L2C_R_REG(L2_CA_CONF_OFF) & L2_CA_CONF_mskL2SET) >>
99 L2_CA_CONF_offL2SET);
100 }
101
102 static inline unsigned long L2_CACHE_WAY(void)
103 {
104 return 1 +
105 ((L2C_R_REG(L2_CA_CONF_OFF) & L2_CA_CONF_mskL2WAY) >>
106 L2_CA_CONF_offL2WAY);
107 }
108
109 static inline unsigned long L2_CACHE_LINE_SIZE(void)
110 {
111
112 return 4 << ((L2C_R_REG(L2_CA_CONF_OFF) & L2_CA_CONF_mskL2CLSZ) >>
113 L2_CA_CONF_offL2CLSZ);
114 }
115
116 static inline unsigned long GET_L2CC_CTRL_CPU(unsigned long cpu)
117 {
118 if (cpu == smp_processor_id())
119 return L2C_R_REG(L2CC_CTRL_OFF);
120 return L2C_R_REG(L2CC_CTRL_OFF + (cpu << 8));
121 }
122
123 static inline void SET_L2CC_CTRL_CPU(unsigned long cpu, unsigned long val)
124 {
125 if (cpu == smp_processor_id())
126 L2C_W_REG(L2CC_CTRL_OFF, val);
127 else
128 L2C_W_REG(L2CC_CTRL_OFF + (cpu << 8), val);
129 }
130
131 static inline unsigned long GET_L2CC_STATUS_CPU(unsigned long cpu)
132 {
133 if (cpu == smp_processor_id())
134 return L2C_R_REG(L2_CCTL_STATUS_OFF);
135 return L2C_R_REG(L2_CCTL_STATUS_OFF + (cpu << 8));
136 }
137 #endif