root/arch/powerpc/sysdev/xics/xics-common.c

DEFINITIONS

1. xics_update_irq_servers
2. xics_set_cpu_giq
3. xics_setup_cpu
4. xics_mask_unknown_vec
5. xics_request_ipi
6. xics_smp_probe
7. xics_teardown_cpu
8. xics_kexec_teardown_cpu
9. xics_migrate_irqs_away
10. xics_get_irq_server
11. xics_host_match
12. xics_ipi_unmask
13. xics_ipi_mask
14. xics_host_map
15. xics_host_xlate
16. xics_set_irq_type
17. xics_retrigger
18. xics_init_host
19. xics_register_ics
20. xics_get_server_size
21. xics_init

   1 // SPDX-License-Identifier: GPL-2.0-or-later
   2 /*
   3  * Copyright 2011 IBM Corporation.
   4  */
   5 #include <linux/types.h>
   6 #include <linux/threads.h>
   7 #include <linux/kernel.h>
   8 #include <linux/irq.h>
   9 #include <linux/debugfs.h>
  10 #include <linux/smp.h>
  11 #include <linux/interrupt.h>
  12 #include <linux/seq_file.h>
  13 #include <linux/init.h>
  14 #include <linux/cpu.h>
  15 #include <linux/of.h>
  16 #include <linux/slab.h>
  17 #include <linux/spinlock.h>
  18 #include <linux/delay.h>
  19 
  20 #include <asm/prom.h>
  21 #include <asm/io.h>
  22 #include <asm/smp.h>
  23 #include <asm/machdep.h>
  24 #include <asm/irq.h>
  25 #include <asm/errno.h>
  26 #include <asm/rtas.h>
  27 #include <asm/xics.h>
  28 #include <asm/firmware.h>
  29 
  30 /* Globals common to all ICP/ICS implementations */
  31 const struct icp_ops    *icp_ops;
  32 
  33 unsigned int xics_default_server                = 0xff;
  34 unsigned int xics_default_distrib_server        = 0;
  35 unsigned int xics_interrupt_server_size         = 8;
  36 
  37 DEFINE_PER_CPU(struct xics_cppr, xics_cppr);
  38 
  39 struct irq_domain *xics_host;
  40 
  41 static LIST_HEAD(ics_list);
  42 
  43 void xics_update_irq_servers(void)
  44 {
  45         int i, j;
  46         struct device_node *np;
  47         u32 ilen;
  48         const __be32 *ireg;
  49         u32 hcpuid;
  50 
  51         /* Find the server numbers for the boot cpu. */
  52         np = of_get_cpu_node(boot_cpuid, NULL);
  53         BUG_ON(!np);
  54 
  55         hcpuid = get_hard_smp_processor_id(boot_cpuid);
  56         xics_default_server = xics_default_distrib_server = hcpuid;
  57 
  58         pr_devel("xics: xics_default_server = 0x%x\n", xics_default_server);
  59 
  60         ireg = of_get_property(np, "ibm,ppc-interrupt-gserver#s", &ilen);
  61         if (!ireg) {
  62                 of_node_put(np);
  63                 return;
  64         }
  65 
  66         i = ilen / sizeof(int);
  67 
  68         /* Global interrupt distribution server is specified in the last
  69          * entry of "ibm,ppc-interrupt-gserver#s" property. Get the last
  70          * entry fom this property for current boot cpu id and use it as
  71          * default distribution server
  72          */
  73         for (j = 0; j < i; j += 2) {
  74                 if (be32_to_cpu(ireg[j]) == hcpuid) {
  75                         xics_default_distrib_server = be32_to_cpu(ireg[j+1]);
  76                         break;
  77                 }
  78         }
  79         pr_devel("xics: xics_default_distrib_server = 0x%x\n",
  80                  xics_default_distrib_server);
  81         of_node_put(np);
  82 }
  83 
  84 /* GIQ stuff, currently only supported on RTAS setups, will have
  85  * to be sorted properly for bare metal
  86  */
  87 void xics_set_cpu_giq(unsigned int gserver, unsigned int join)
  88 {
  89 #ifdef CONFIG_PPC_RTAS
  90         int index;
  91         int status;
  92 
  93         if (!rtas_indicator_present(GLOBAL_INTERRUPT_QUEUE, NULL))
  94                 return;
  95 
  96         index = (1UL << xics_interrupt_server_size) - 1 - gserver;
  97 
  98         status = rtas_set_indicator_fast(GLOBAL_INTERRUPT_QUEUE, index, join);
  99 
 100         WARN(status < 0, "set-indicator(%d, %d, %u) returned %d\n",
 101              GLOBAL_INTERRUPT_QUEUE, index, join, status);
 102 #endif
 103 }
 104 
 105 void xics_setup_cpu(void)
 106 {
 107         icp_ops->set_priority(LOWEST_PRIORITY);
 108 
 109         xics_set_cpu_giq(xics_default_distrib_server, 1);
 110 }
 111 
 112 void xics_mask_unknown_vec(unsigned int vec)
 113 {
 114         struct ics *ics;
 115 
 116         pr_err("Interrupt 0x%x (real) is invalid, disabling it.\n", vec);
 117 
 118         list_for_each_entry(ics, &ics_list, link)
 119                 ics->mask_unknown(ics, vec);
 120 }
 121 
 122 
 123 #ifdef CONFIG_SMP
 124 
 125 static void xics_request_ipi(void)
 126 {
 127         unsigned int ipi;
 128 
 129         ipi = irq_create_mapping(xics_host, XICS_IPI);
 130         BUG_ON(!ipi);
 131 
 132         /*
 133          * IPIs are marked IRQF_PERCPU. The handler was set in map.
 134          */
 135         BUG_ON(request_irq(ipi, icp_ops->ipi_action,
 136                            IRQF_PERCPU | IRQF_NO_THREAD, "IPI", NULL));
 137 }
 138 
 139 void __init xics_smp_probe(void)
 140 {
 141         /* Register all the IPIs */
 142         xics_request_ipi();
 143 
 144         /* Setup cause_ipi callback based on which ICP is used */
 145         smp_ops->cause_ipi = icp_ops->cause_ipi;
 146 }
 147 
 148 #endif /* CONFIG_SMP */
 149 
 150 void xics_teardown_cpu(void)
 151 {
 152         struct xics_cppr *os_cppr = this_cpu_ptr(&xics_cppr);
 153 
 154         /*
 155          * we have to reset the cppr index to 0 because we're
 156          * not going to return from the IPI
 157          */
 158         os_cppr->index = 0;
 159         icp_ops->set_priority(0);
 160         icp_ops->teardown_cpu();
 161 }
 162 
 163 void xics_kexec_teardown_cpu(int secondary)
 164 {
 165         xics_teardown_cpu();
 166 
 167         icp_ops->flush_ipi();
 168 
 169         /*
 170          * Some machines need to have at least one cpu in the GIQ,
 171          * so leave the master cpu in the group.
 172          */
 173         if (secondary)
 174                 xics_set_cpu_giq(xics_default_distrib_server, 0);
 175 }
 176 
 177 
 178 #ifdef CONFIG_HOTPLUG_CPU
 179 
 180 /* Interrupts are disabled. */
 181 void xics_migrate_irqs_away(void)
 182 {
 183         int cpu = smp_processor_id(), hw_cpu = hard_smp_processor_id();
 184         unsigned int irq, virq;
 185         struct irq_desc *desc;
 186 
 187         /* If we used to be the default server, move to the new "boot_cpuid" */
 188         if (hw_cpu == xics_default_server)
 189                 xics_update_irq_servers();
 190 
 191         /* Reject any interrupt that was queued to us... */
 192         icp_ops->set_priority(0);
 193 
 194         /* Remove ourselves from the global interrupt queue */
 195         xics_set_cpu_giq(xics_default_distrib_server, 0);
 196 
 197         for_each_irq_desc(virq, desc) {
 198                 struct irq_chip *chip;
 199                 long server;
 200                 unsigned long flags;
 201                 struct ics *ics;
 202 
 203                 /* We can't set affinity on ISA interrupts */
 204                 if (virq < NUM_ISA_INTERRUPTS)
 205                         continue;
 206                 /* We only need to migrate enabled IRQS */
 207                 if (!desc->action)
 208                         continue;
 209                 if (desc->irq_data.domain != xics_host)
 210                         continue;
 211                 irq = desc->irq_data.hwirq;
 212                 /* We need to get IPIs still. */
 213                 if (irq == XICS_IPI || irq == XICS_IRQ_SPURIOUS)
 214                         continue;
 215                 chip = irq_desc_get_chip(desc);
 216                 if (!chip || !chip->irq_set_affinity)
 217                         continue;
 218 
 219                 raw_spin_lock_irqsave(&desc->lock, flags);
 220 
 221                 /* Locate interrupt server */
 222                 server = -1;
 223                 ics = irq_desc_get_chip_data(desc);
 224                 if (ics)
 225                         server = ics->get_server(ics, irq);
 226                 if (server < 0) {
 227                         printk(KERN_ERR "%s: Can't find server for irq %d\n",
 228                                __func__, irq);
 229                         goto unlock;
 230                 }
 231 
 232                 /* We only support delivery to all cpus or to one cpu.
 233                  * The irq has to be migrated only in the single cpu
 234                  * case.
 235                  */
 236                 if (server != hw_cpu)
 237                         goto unlock;
 238 
 239                 /* This is expected during cpu offline. */
 240                 if (cpu_online(cpu))
 241                         pr_warn("IRQ %u affinity broken off cpu %u\n",
 242                                 virq, cpu);
 243 
 244                 /* Reset affinity to all cpus */
 245                 raw_spin_unlock_irqrestore(&desc->lock, flags);
 246                 irq_set_affinity(virq, cpu_all_mask);
 247                 continue;
 248 unlock:
 249                 raw_spin_unlock_irqrestore(&desc->lock, flags);
 250         }
 251 
 252         /* Allow "sufficient" time to drop any inflight IRQ's */
 253         mdelay(5);
 254 
 255         /*
 256          * Allow IPIs again. This is done at the very end, after migrating all
 257          * interrupts, the expectation is that we'll only get woken up by an IPI
 258          * interrupt beyond this point, but leave externals masked just to be
 259          * safe. If we're using icp-opal this may actually allow all
 260          * interrupts anyway, but that should be OK.
 261          */
 262         icp_ops->set_priority(DEFAULT_PRIORITY);
 263 
 264 }
 265 #endif /* CONFIG_HOTPLUG_CPU */
 266 
 267 #ifdef CONFIG_SMP
 268 /*
 269  * For the moment we only implement delivery to all cpus or one cpu.
 270  *
 271  * If the requested affinity is cpu_all_mask, we set global affinity.
 272  * If not we set it to the first cpu in the mask, even if multiple cpus
 273  * are set. This is so things like irqbalance (which set core and package
 274  * wide affinities) do the right thing.
 275  *
 276  * We need to fix this to implement support for the links
 277  */
 278 int xics_get_irq_server(unsigned int virq, const struct cpumask *cpumask,
 279                         unsigned int strict_check)
 280 {
 281 
 282         if (!distribute_irqs)
 283                 return xics_default_server;
 284 
 285         if (!cpumask_subset(cpu_possible_mask, cpumask)) {
 286                 int server = cpumask_first_and(cpu_online_mask, cpumask);
 287 
 288                 if (server < nr_cpu_ids)
 289                         return get_hard_smp_processor_id(server);
 290 
 291                 if (strict_check)
 292                         return -1;
 293         }
 294 
 295         /*
 296          * Workaround issue with some versions of JS20 firmware that
 297          * deliver interrupts to cpus which haven't been started. This
 298          * happens when using the maxcpus= boot option.
 299          */
 300         if (cpumask_equal(cpu_online_mask, cpu_present_mask))
 301                 return xics_default_distrib_server;
 302 
 303         return xics_default_server;
 304 }
 305 #endif /* CONFIG_SMP */
 306 
 307 static int xics_host_match(struct irq_domain *h, struct device_node *node,
 308                            enum irq_domain_bus_token bus_token)
 309 {
 310         struct ics *ics;
 311 
 312         list_for_each_entry(ics, &ics_list, link)
 313                 if (ics->host_match(ics, node))
 314                         return 1;
 315 
 316         return 0;
 317 }
 318 
 319 /* Dummies */
 320 static void xics_ipi_unmask(struct irq_data *d) { }
 321 static void xics_ipi_mask(struct irq_data *d) { }
 322 
 323 static struct irq_chip xics_ipi_chip = {
 324         .name = "XICS",
 325         .irq_eoi = NULL, /* Patched at init time */
 326         .irq_mask = xics_ipi_mask,
 327         .irq_unmask = xics_ipi_unmask,
 328 };
 329 
 330 static int xics_host_map(struct irq_domain *h, unsigned int virq,
 331                          irq_hw_number_t hw)
 332 {
 333         struct ics *ics;
 334 
 335         pr_devel("xics: map virq %d, hwirq 0x%lx\n", virq, hw);
 336 
 337         /*
 338          * Mark interrupts as edge sensitive by default so that resend
 339          * actually works. The device-tree parsing will turn the LSIs
 340          * back to level.
 341          */
 342         irq_clear_status_flags(virq, IRQ_LEVEL);
 343 
 344         /* Don't call into ICS for IPIs */
 345         if (hw == XICS_IPI) {
 346                 irq_set_chip_and_handler(virq, &xics_ipi_chip,
 347                                          handle_percpu_irq);
 348                 return 0;
 349         }
 350 
 351         /* Let the ICS setup the chip data */
 352         list_for_each_entry(ics, &ics_list, link)
 353                 if (ics->map(ics, virq) == 0)
 354                         return 0;
 355 
 356         return -EINVAL;
 357 }
 358 
 359 static int xics_host_xlate(struct irq_domain *h, struct device_node *ct,
 360                            const u32 *intspec, unsigned int intsize,
 361                            irq_hw_number_t *out_hwirq, unsigned int *out_flags)
 362 
 363 {
 364         *out_hwirq = intspec[0];
 365 
 366         /*
 367          * If intsize is at least 2, we look for the type in the second cell,
 368          * we assume the LSB indicates a level interrupt.
 369          */
 370         if (intsize > 1) {
 371                 if (intspec[1] & 1)
 372                         *out_flags = IRQ_TYPE_LEVEL_LOW;
 373                 else
 374                         *out_flags = IRQ_TYPE_EDGE_RISING;
 375         } else
 376                 *out_flags = IRQ_TYPE_LEVEL_LOW;
 377 
 378         return 0;
 379 }
 380 
 381 int xics_set_irq_type(struct irq_data *d, unsigned int flow_type)
 382 {
 383         /*
 384          * We only support these. This has really no effect other than setting
 385          * the corresponding descriptor bits mind you but those will in turn
 386          * affect the resend function when re-enabling an edge interrupt.
 387          *
 388          * Set set the default to edge as explained in map().
 389          */
 390         if (flow_type == IRQ_TYPE_DEFAULT || flow_type == IRQ_TYPE_NONE)
 391                 flow_type = IRQ_TYPE_EDGE_RISING;
 392 
 393         if (flow_type != IRQ_TYPE_EDGE_RISING &&
 394             flow_type != IRQ_TYPE_LEVEL_LOW)
 395                 return -EINVAL;
 396 
 397         irqd_set_trigger_type(d, flow_type);
 398 
 399         return IRQ_SET_MASK_OK_NOCOPY;
 400 }
 401 
 402 int xics_retrigger(struct irq_data *data)
 403 {
 404         /*
 405          * We need to push a dummy CPPR when retriggering, since the subsequent
 406          * EOI will try to pop it. Passing 0 works, as the function hard codes
 407          * the priority value anyway.
 408          */
 409         xics_push_cppr(0);
 410 
 411         /* Tell the core to do a soft retrigger */
 412         return 0;
 413 }
 414 
 415 static const struct irq_domain_ops xics_host_ops = {
 416         .match = xics_host_match,
 417         .map = xics_host_map,
 418         .xlate = xics_host_xlate,
 419 };
 420 
 421 static void __init xics_init_host(void)
 422 {
 423         xics_host = irq_domain_add_tree(NULL, &xics_host_ops, NULL);
 424         BUG_ON(xics_host == NULL);
 425         irq_set_default_host(xics_host);
 426 }
 427 
 428 void __init xics_register_ics(struct ics *ics)
 429 {
 430         list_add(&ics->link, &ics_list);
 431 }
 432 
 433 static void __init xics_get_server_size(void)
 434 {
 435         struct device_node *np;
 436         const __be32 *isize;
 437 
 438         /* We fetch the interrupt server size from the first ICS node
 439          * we find if any
 440          */
 441         np = of_find_compatible_node(NULL, NULL, "ibm,ppc-xics");
 442         if (!np)
 443                 return;
 444 
 445         isize = of_get_property(np, "ibm,interrupt-server#-size", NULL);
 446         if (isize)
 447                 xics_interrupt_server_size = be32_to_cpu(*isize);
 448 
 449         of_node_put(np);
 450 }
 451 
 452 void __init xics_init(void)
 453 {
 454         int rc = -1;
 455 
 456         /* Fist locate ICP */
 457         if (firmware_has_feature(FW_FEATURE_LPAR))
 458                 rc = icp_hv_init();
 459         if (rc < 0) {
 460                 rc = icp_native_init();
 461                 if (rc == -ENODEV)
 462                     rc = icp_opal_init();
 463         }
 464         if (rc < 0) {
 465                 pr_warn("XICS: Cannot find a Presentation Controller !\n");
 466                 return;
 467         }
 468 
 469         /* Copy get_irq callback over to ppc_md */
 470         ppc_md.get_irq = icp_ops->get_irq;
 471 
 472         /* Patch up IPI chip EOI */
 473         xics_ipi_chip.irq_eoi = icp_ops->eoi;
 474 
 475         /* Now locate ICS */
 476         rc = ics_rtas_init();
 477         if (rc < 0)
 478                 rc = ics_opal_init();
 479         if (rc < 0)
 480                 pr_warn("XICS: Cannot find a Source Controller !\n");
 481 
 482         /* Initialize common bits */
 483         xics_get_server_size();
 484         xics_update_irq_servers();
 485         xics_init_host();
 486         xics_setup_cpu();
 487 }