root/arch/powerpc/platforms/83xx/misc.c

DEFINITIONS

1. mpc83xx_restart_init
2. mpc83xx_restart
3. mpc83xx_time_init
4. mpc83xx_ipic_init_IRQ
5. mpc83xx_qe_init_IRQ
6. mpc83xx_ipic_and_qe_init_IRQ
7. mpc83xx_declare_of_platform_devices
8. mpc83xx_setup_pci
9. mpc83xx_setup_arch
10. machine_check_83xx

   1 // SPDX-License-Identifier: GPL-2.0-or-later
   2 /*
   3  * misc setup functions for MPC83xx
   4  *
   5  * Maintainer: Kumar Gala <galak@kernel.crashing.org>
   6  */
   7 
   8 #include <linux/stddef.h>
   9 #include <linux/kernel.h>
  10 #include <linux/of_platform.h>
  11 #include <linux/pci.h>
  12 
  13 #include <asm/debug.h>
  14 #include <asm/io.h>
  15 #include <asm/hw_irq.h>
  16 #include <asm/ipic.h>
  17 #include <soc/fsl/qe/qe_ic.h>
  18 #include <sysdev/fsl_soc.h>
  19 #include <sysdev/fsl_pci.h>
  20 
  21 #include "mpc83xx.h"
  22 
  23 static __be32 __iomem *restart_reg_base;
  24 
  25 static int __init mpc83xx_restart_init(void)
  26 {
  27         /* map reset restart_reg_baseister space */
  28         restart_reg_base = ioremap(get_immrbase() + 0x900, 0xff);
  29 
  30         return 0;
  31 }
  32 
  33 arch_initcall(mpc83xx_restart_init);
  34 
  35 void __noreturn mpc83xx_restart(char *cmd)
  36 {
  37 #define RST_OFFSET      0x00000900
  38 #define RST_PROT_REG    0x00000018
  39 #define RST_CTRL_REG    0x0000001c
  40 
  41         local_irq_disable();
  42 
  43         if (restart_reg_base) {
  44                 /* enable software reset "RSTE" */
  45                 out_be32(restart_reg_base + (RST_PROT_REG >> 2), 0x52535445);
  46 
  47                 /* set software hard reset */
  48                 out_be32(restart_reg_base + (RST_CTRL_REG >> 2), 0x2);
  49         } else {
  50                 printk (KERN_EMERG "Error: Restart registers not mapped, spinning!\n");
  51         }
  52 
  53         for (;;) ;
  54 }
  55 
  56 long __init mpc83xx_time_init(void)
  57 {
  58 #define SPCR_OFFSET     0x00000110
  59 #define SPCR_TBEN       0x00400000
  60         __be32 __iomem *spcr = ioremap(get_immrbase() + SPCR_OFFSET, 4);
  61         __be32 tmp;
  62 
  63         tmp = in_be32(spcr);
  64         out_be32(spcr, tmp | SPCR_TBEN);
  65 
  66         iounmap(spcr);
  67 
  68         return 0;
  69 }
  70 
  71 void __init mpc83xx_ipic_init_IRQ(void)
  72 {
  73         struct device_node *np;
  74 
  75         /* looking for fsl,pq2pro-pic which is asl compatible with fsl,ipic */
  76         np = of_find_compatible_node(NULL, NULL, "fsl,ipic");
  77         if (!np)
  78                 np = of_find_node_by_type(NULL, "ipic");
  79         if (!np)
  80                 return;
  81 
  82         ipic_init(np, 0);
  83 
  84         of_node_put(np);
  85 
  86         /* Initialize the default interrupt mapping priorities,
  87          * in case the boot rom changed something on us.
  88          */
  89         ipic_set_default_priority();
  90 }
  91 
  92 #ifdef CONFIG_QUICC_ENGINE
  93 void __init mpc83xx_qe_init_IRQ(void)
  94 {
  95         struct device_node *np;
  96 
  97         np = of_find_compatible_node(NULL, NULL, "fsl,qe-ic");
  98         if (!np) {
  99                 np = of_find_node_by_type(NULL, "qeic");
 100                 if (!np)
 101                         return;
 102         }
 103         qe_ic_init(np, 0, qe_ic_cascade_low_ipic, qe_ic_cascade_high_ipic);
 104         of_node_put(np);
 105 }
 106 
 107 void __init mpc83xx_ipic_and_qe_init_IRQ(void)
 108 {
 109         mpc83xx_ipic_init_IRQ();
 110         mpc83xx_qe_init_IRQ();
 111 }
 112 #endif /* CONFIG_QUICC_ENGINE */
 113 
 114 static const struct of_device_id of_bus_ids[] __initconst = {
 115         { .type = "soc", },
 116         { .compatible = "soc", },
 117         { .compatible = "simple-bus" },
 118         { .compatible = "gianfar" },
 119         { .compatible = "gpio-leds", },
 120         { .type = "qe", },
 121         { .compatible = "fsl,qe", },
 122         {},
 123 };
 124 
 125 int __init mpc83xx_declare_of_platform_devices(void)
 126 {
 127         of_platform_bus_probe(NULL, of_bus_ids, NULL);
 128         return 0;
 129 }
 130 
 131 #ifdef CONFIG_PCI
 132 void __init mpc83xx_setup_pci(void)
 133 {
 134         struct device_node *np;
 135 
 136         for_each_compatible_node(np, "pci", "fsl,mpc8349-pci")
 137                 mpc83xx_add_bridge(np);
 138         for_each_compatible_node(np, "pci", "fsl,mpc8314-pcie")
 139                 mpc83xx_add_bridge(np);
 140 }
 141 #endif
 142 
 143 void __init mpc83xx_setup_arch(void)
 144 {
 145         if (ppc_md.progress)
 146                 ppc_md.progress("mpc83xx_setup_arch()", 0);
 147 
 148         mpc83xx_setup_pci();
 149 }
 150 
 151 int machine_check_83xx(struct pt_regs *regs)
 152 {
 153         u32 mask = 1 << (31 - IPIC_MCP_WDT);
 154 
 155         if (!(regs->msr & SRR1_MCE_MCP) || !(ipic_get_mcp_status() & mask))
 156                 return machine_check_generic(regs);
 157         ipic_clear_mcp_status(mask);
 158 
 159         if (debugger_fault_handler(regs))
 160                 return 1;
 161 
 162         die("Watchdog NMI Reset", regs, 0);
 163 
 164         return 1;
 165 }