root/arch/powerpc/platforms/85xx/twr_p102x.c

DEFINITIONS

1. twr_p1025_pic_init
2. twr_p1025_setup_arch
3. twr_p1025_probe
4. define_machine

   1 // SPDX-License-Identifier: GPL-2.0-or-later
   2 /*
   3  * Copyright 2010-2011, 2013 Freescale Semiconductor, Inc.
   4  *
   5  * Author: Michael Johnston <michael.johnston@freescale.com>
   6  *
   7  * Description:
   8  * TWR-P102x Board Setup
   9  */
  10 
  11 #include <linux/kernel.h>
  12 #include <linux/init.h>
  13 #include <linux/errno.h>
  14 #include <linux/fsl/guts.h>
  15 #include <linux/pci.h>
  16 #include <linux/of_platform.h>
  17 
  18 #include <asm/pci-bridge.h>
  19 #include <asm/udbg.h>
  20 #include <asm/mpic.h>
  21 #include <soc/fsl/qe/qe.h>
  22 #include <soc/fsl/qe/qe_ic.h>
  23 
  24 #include <sysdev/fsl_soc.h>
  25 #include <sysdev/fsl_pci.h>
  26 #include "smp.h"
  27 
  28 #include "mpc85xx.h"
  29 
  30 static void __init twr_p1025_pic_init(void)
  31 {
  32         struct mpic *mpic;
  33 
  34 #ifdef CONFIG_QUICC_ENGINE
  35         struct device_node *np;
  36 #endif
  37 
  38         mpic = mpic_alloc(NULL, 0, MPIC_BIG_ENDIAN |
  39                         MPIC_SINGLE_DEST_CPU,
  40                         0, 256, " OpenPIC  ");
  41 
  42         BUG_ON(mpic == NULL);
  43         mpic_init(mpic);
  44 
  45 #ifdef CONFIG_QUICC_ENGINE
  46         np = of_find_compatible_node(NULL, NULL, "fsl,qe-ic");
  47         if (np) {
  48                 qe_ic_init(np, 0, qe_ic_cascade_low_mpic,
  49                                 qe_ic_cascade_high_mpic);
  50                 of_node_put(np);
  51         } else
  52                 pr_err("Could not find qe-ic node\n");
  53 #endif
  54 }
  55 
  56 /* ************************************************************************
  57  *
  58  * Setup the architecture
  59  *
  60  */
  61 static void __init twr_p1025_setup_arch(void)
  62 {
  63 #ifdef CONFIG_QUICC_ENGINE
  64         struct device_node *np;
  65 #endif
  66 
  67         if (ppc_md.progress)
  68                 ppc_md.progress("twr_p1025_setup_arch()", 0);
  69 
  70         mpc85xx_smp_init();
  71 
  72         fsl_pci_assign_primary();
  73 
  74 #ifdef CONFIG_QUICC_ENGINE
  75         mpc85xx_qe_init();
  76         mpc85xx_qe_par_io_init();
  77 
  78 #if IS_ENABLED(CONFIG_UCC_GETH) || IS_ENABLED(CONFIG_SERIAL_QE)
  79         if (machine_is(twr_p1025)) {
  80                 struct ccsr_guts __iomem *guts;
  81 
  82                 np = of_find_compatible_node(NULL, NULL, "fsl,p1021-guts");
  83                 if (np) {
  84                         guts = of_iomap(np, 0);
  85                         if (!guts)
  86                                 pr_err("twr_p1025: could not map global utilities register\n");
  87                         else {
  88                         /* P1025 has pins muxed for QE and other functions. To
  89                          * enable QE UEC mode, we need to set bit QE0 for UCC1
  90                          * in Eth mode, QE0 and QE3 for UCC5 in Eth mode, QE9
  91                          * and QE12 for QE MII management signals in PMUXCR
  92                          * register.
  93                          * Set QE mux bits in PMUXCR */
  94                         setbits32(&guts->pmuxcr, MPC85xx_PMUXCR_QE(0) |
  95                                         MPC85xx_PMUXCR_QE(3) |
  96                                         MPC85xx_PMUXCR_QE(9) |
  97                                         MPC85xx_PMUXCR_QE(12));
  98                         iounmap(guts);
  99 
 100 #if IS_ENABLED(CONFIG_SERIAL_QE)
 101                         /* On P1025TWR board, the UCC7 acted as UART port.
 102                          * However, The UCC7's CTS pin is low level in default,
 103                          * it will impact the transmission in full duplex
 104                          * communication. So disable the Flow control pin PA18.
 105                          * The UCC7 UART just can use RXD and TXD pins.
 106                          */
 107                         par_io_config_pin(0, 18, 0, 0, 0, 0);
 108 #endif
 109                         /* Drive PB29 to CPLD low - CPLD will then change
 110                          * muxing from LBC to QE */
 111                         par_io_config_pin(1, 29, 1, 0, 0, 0);
 112                         par_io_data_set(1, 29, 0);
 113                         }
 114                         of_node_put(np);
 115                 }
 116         }
 117 #endif
 118 #endif  /* CONFIG_QUICC_ENGINE */
 119 
 120         pr_info("TWR-P1025 board from Freescale Semiconductor\n");
 121 }
 122 
 123 machine_arch_initcall(twr_p1025, mpc85xx_common_publish_devices);
 124 
 125 static int __init twr_p1025_probe(void)
 126 {
 127         return of_machine_is_compatible("fsl,TWR-P1025");
 128 }
 129 
 130 define_machine(twr_p1025) {
 131         .name                   = "TWR-P1025",
 132         .probe                  = twr_p1025_probe,
 133         .setup_arch             = twr_p1025_setup_arch,
 134         .init_IRQ               = twr_p1025_pic_init,
 135 #ifdef CONFIG_PCI
 136         .pcibios_fixup_bus      = fsl_pcibios_fixup_bus,
 137 #endif
 138         .get_irq                = mpic_get_irq,
 139         .calibrate_decr         = generic_calibrate_decr,
 140         .progress               = udbg_progress,
 141 };