root/arch/powerpc/platforms/powernv/opal-imc.c

DEFINITIONS

1. imc_mem_get
2. imc_mem_set
3. imc_debugfs_create_x64
4. export_imc_mode_and_cmd
5. imc_get_mem_addr_nest
6. imc_pmu_create
7. disable_nest_pmu_counters
8. disable_core_pmu_counters
9. get_max_nest_dev
10. opal_imc_counters_probe
11. opal_imc_counters_shutdown

   1 // SPDX-License-Identifier: GPL-2.0-or-later
   2 /*
   3  * OPAL IMC interface detection driver
   4  * Supported on POWERNV platform
   5  *
   6  * Copyright    (C) 2017 Madhavan Srinivasan, IBM Corporation.
   7  *              (C) 2017 Anju T Sudhakar, IBM Corporation.
   8  *              (C) 2017 Hemant K Shaw, IBM Corporation.
   9  */
  10 #include <linux/kernel.h>
  11 #include <linux/platform_device.h>
  12 #include <linux/of.h>
  13 #include <linux/of_address.h>
  14 #include <linux/of_platform.h>
  15 #include <linux/crash_dump.h>
  16 #include <asm/opal.h>
  17 #include <asm/io.h>
  18 #include <asm/imc-pmu.h>
  19 #include <asm/cputhreads.h>
  20 #include <asm/debugfs.h>
  21 
  22 static struct dentry *imc_debugfs_parent;
  23 
  24 /* Helpers to export imc command and mode via debugfs */
  25 static int imc_mem_get(void *data, u64 *val)
  26 {
  27         *val = cpu_to_be64(*(u64 *)data);
  28         return 0;
  29 }
  30 
  31 static int imc_mem_set(void *data, u64 val)
  32 {
  33         *(u64 *)data = cpu_to_be64(val);
  34         return 0;
  35 }
  36 DEFINE_DEBUGFS_ATTRIBUTE(fops_imc_x64, imc_mem_get, imc_mem_set, "0x%016llx\n");
  37 
  38 static struct dentry *imc_debugfs_create_x64(const char *name, umode_t mode,
  39                                              struct dentry *parent, u64  *value)
  40 {
  41         return debugfs_create_file_unsafe(name, mode, parent,
  42                                           value, &fops_imc_x64);
  43 }
  44 
  45 /*
  46  * export_imc_mode_and_cmd: Create a debugfs interface
  47  *                     for imc_cmd and imc_mode
  48  *                     for each node in the system.
  49  *  imc_mode and imc_cmd can be changed by echo into
  50  *  this interface.
  51  */
  52 static void export_imc_mode_and_cmd(struct device_node *node,
  53                                     struct imc_pmu *pmu_ptr)
  54 {
  55         static u64 loc, *imc_mode_addr, *imc_cmd_addr;
  56         char mode[16], cmd[16];
  57         u32 cb_offset;
  58         struct imc_mem_info *ptr = pmu_ptr->mem_info;
  59 
  60         imc_debugfs_parent = debugfs_create_dir("imc", powerpc_debugfs_root);
  61 
  62         if (!imc_debugfs_parent)
  63                 return;
  64 
  65         if (of_property_read_u32(node, "cb_offset", &cb_offset))
  66                 cb_offset = IMC_CNTL_BLK_OFFSET;
  67 
  68         while (ptr->vbase != NULL) {
  69                 loc = (u64)(ptr->vbase) + cb_offset;
  70                 imc_mode_addr = (u64 *)(loc + IMC_CNTL_BLK_MODE_OFFSET);
  71                 sprintf(mode, "imc_mode_%d", (u32)(ptr->id));
  72                 if (!imc_debugfs_create_x64(mode, 0600, imc_debugfs_parent,
  73                                             imc_mode_addr))
  74                         goto err;
  75 
  76                 imc_cmd_addr = (u64 *)(loc + IMC_CNTL_BLK_CMD_OFFSET);
  77                 sprintf(cmd, "imc_cmd_%d", (u32)(ptr->id));
  78                 if (!imc_debugfs_create_x64(cmd, 0600, imc_debugfs_parent,
  79                                             imc_cmd_addr))
  80                         goto err;
  81                 ptr++;
  82         }
  83         return;
  84 
  85 err:
  86         debugfs_remove_recursive(imc_debugfs_parent);
  87 }
  88 
  89 /*
  90  * imc_get_mem_addr_nest: Function to get nest counter memory region
  91  * for each chip
  92  */
  93 static int imc_get_mem_addr_nest(struct device_node *node,
  94                                  struct imc_pmu *pmu_ptr,
  95                                  u32 offset)
  96 {
  97         int nr_chips = 0, i;
  98         u64 *base_addr_arr, baddr;
  99         u32 *chipid_arr;
 100 
 101         nr_chips = of_property_count_u32_elems(node, "chip-id");
 102         if (nr_chips <= 0)
 103                 return -ENODEV;
 104 
 105         base_addr_arr = kcalloc(nr_chips, sizeof(*base_addr_arr), GFP_KERNEL);
 106         if (!base_addr_arr)
 107                 return -ENOMEM;
 108 
 109         chipid_arr = kcalloc(nr_chips, sizeof(*chipid_arr), GFP_KERNEL);
 110         if (!chipid_arr) {
 111                 kfree(base_addr_arr);
 112                 return -ENOMEM;
 113         }
 114 
 115         if (of_property_read_u32_array(node, "chip-id", chipid_arr, nr_chips))
 116                 goto error;
 117 
 118         if (of_property_read_u64_array(node, "base-addr", base_addr_arr,
 119                                                                 nr_chips))
 120                 goto error;
 121 
 122         pmu_ptr->mem_info = kcalloc(nr_chips + 1, sizeof(*pmu_ptr->mem_info),
 123                                     GFP_KERNEL);
 124         if (!pmu_ptr->mem_info)
 125                 goto error;
 126 
 127         for (i = 0; i < nr_chips; i++) {
 128                 pmu_ptr->mem_info[i].id = chipid_arr[i];
 129                 baddr = base_addr_arr[i] + offset;
 130                 pmu_ptr->mem_info[i].vbase = phys_to_virt(baddr);
 131         }
 132 
 133         pmu_ptr->imc_counter_mmaped = true;
 134         kfree(base_addr_arr);
 135         kfree(chipid_arr);
 136         return 0;
 137 
 138 error:
 139         kfree(base_addr_arr);
 140         kfree(chipid_arr);
 141         return -1;
 142 }
 143 
 144 /*
 145  * imc_pmu_create : Takes the parent device which is the pmu unit, pmu_index
 146  *                  and domain as the inputs.
 147  * Allocates memory for the struct imc_pmu, sets up its domain, size and offsets
 148  */
 149 static struct imc_pmu *imc_pmu_create(struct device_node *parent, int pmu_index, int domain)
 150 {
 151         int ret = 0;
 152         struct imc_pmu *pmu_ptr;
 153         u32 offset;
 154 
 155         /* Return for unknown domain */
 156         if (domain < 0)
 157                 return NULL;
 158 
 159         /* memory for pmu */
 160         pmu_ptr = kzalloc(sizeof(*pmu_ptr), GFP_KERNEL);
 161         if (!pmu_ptr)
 162                 return NULL;
 163 
 164         /* Set the domain */
 165         pmu_ptr->domain = domain;
 166 
 167         ret = of_property_read_u32(parent, "size", &pmu_ptr->counter_mem_size);
 168         if (ret)
 169                 goto free_pmu;
 170 
 171         if (!of_property_read_u32(parent, "offset", &offset)) {
 172                 if (imc_get_mem_addr_nest(parent, pmu_ptr, offset))
 173                         goto free_pmu;
 174         }
 175 
 176         /* Function to register IMC pmu */
 177         ret = init_imc_pmu(parent, pmu_ptr, pmu_index);
 178         if (ret) {
 179                 pr_err("IMC PMU %s Register failed\n", pmu_ptr->pmu.name);
 180                 kfree(pmu_ptr->pmu.name);
 181                 if (pmu_ptr->domain == IMC_DOMAIN_NEST)
 182                         kfree(pmu_ptr->mem_info);
 183                 kfree(pmu_ptr);
 184                 return NULL;
 185         }
 186 
 187         return pmu_ptr;
 188 
 189 free_pmu:
 190         kfree(pmu_ptr);
 191         return NULL;
 192 }
 193 
 194 static void disable_nest_pmu_counters(void)
 195 {
 196         int nid, cpu;
 197         const struct cpumask *l_cpumask;
 198 
 199         get_online_cpus();
 200         for_each_node_with_cpus(nid) {
 201                 l_cpumask = cpumask_of_node(nid);
 202                 cpu = cpumask_first_and(l_cpumask, cpu_online_mask);
 203                 if (cpu >= nr_cpu_ids)
 204                         continue;
 205                 opal_imc_counters_stop(OPAL_IMC_COUNTERS_NEST,
 206                                        get_hard_smp_processor_id(cpu));
 207         }
 208         put_online_cpus();
 209 }
 210 
 211 static void disable_core_pmu_counters(void)
 212 {
 213         cpumask_t cores_map;
 214         int cpu, rc;
 215 
 216         get_online_cpus();
 217         /* Disable the IMC Core functions */
 218         cores_map = cpu_online_cores_map();
 219         for_each_cpu(cpu, &cores_map) {
 220                 rc = opal_imc_counters_stop(OPAL_IMC_COUNTERS_CORE,
 221                                             get_hard_smp_processor_id(cpu));
 222                 if (rc)
 223                         pr_err("%s: Failed to stop Core (cpu = %d)\n",
 224                                 __FUNCTION__, cpu);
 225         }
 226         put_online_cpus();
 227 }
 228 
 229 int get_max_nest_dev(void)
 230 {
 231         struct device_node *node;
 232         u32 pmu_units = 0, type;
 233 
 234         for_each_compatible_node(node, NULL, IMC_DTB_UNIT_COMPAT) {
 235                 if (of_property_read_u32(node, "type", &type))
 236                         continue;
 237 
 238                 if (type == IMC_TYPE_CHIP)
 239                         pmu_units++;
 240         }
 241 
 242         return pmu_units;
 243 }
 244 
 245 static int opal_imc_counters_probe(struct platform_device *pdev)
 246 {
 247         struct device_node *imc_dev = pdev->dev.of_node;
 248         struct imc_pmu *pmu;
 249         int pmu_count = 0, domain;
 250         bool core_imc_reg = false, thread_imc_reg = false;
 251         u32 type;
 252 
 253         /*
 254          * Check whether this is kdump kernel. If yes, force the engines to
 255          * stop and return.
 256          */
 257         if (is_kdump_kernel()) {
 258                 disable_nest_pmu_counters();
 259                 disable_core_pmu_counters();
 260                 return -ENODEV;
 261         }
 262 
 263         for_each_compatible_node(imc_dev, NULL, IMC_DTB_UNIT_COMPAT) {
 264                 pmu = NULL;
 265                 if (of_property_read_u32(imc_dev, "type", &type)) {
 266                         pr_warn("IMC Device without type property\n");
 267                         continue;
 268                 }
 269 
 270                 switch (type) {
 271                 case IMC_TYPE_CHIP:
 272                         domain = IMC_DOMAIN_NEST;
 273                         break;
 274                 case IMC_TYPE_CORE:
 275                         domain =IMC_DOMAIN_CORE;
 276                         break;
 277                 case IMC_TYPE_THREAD:
 278                         domain = IMC_DOMAIN_THREAD;
 279                         break;
 280                 case IMC_TYPE_TRACE:
 281                         /*
 282                          * FIXME. Using trace_imc events to monitor application
 283                          * or KVM thread performance can cause a checkstop
 284                          * (system crash).
 285                          * Disable it for now.
 286                          */
 287                         pr_info_once("IMC: disabling trace_imc PMU\n");
 288                         domain = -1;
 289                         break;
 290                 default:
 291                         pr_warn("IMC Unknown Device type \n");
 292                         domain = -1;
 293                         break;
 294                 }
 295 
 296                 pmu = imc_pmu_create(imc_dev, pmu_count, domain);
 297                 if (pmu != NULL) {
 298                         if (domain == IMC_DOMAIN_NEST) {
 299                                 if (!imc_debugfs_parent)
 300                                         export_imc_mode_and_cmd(imc_dev, pmu);
 301                                 pmu_count++;
 302                         }
 303                         if (domain == IMC_DOMAIN_CORE)
 304                                 core_imc_reg = true;
 305                         if (domain == IMC_DOMAIN_THREAD)
 306                                 thread_imc_reg = true;
 307                 }
 308         }
 309 
 310         /* If core imc is not registered, unregister thread-imc */
 311         if (!core_imc_reg && thread_imc_reg)
 312                 unregister_thread_imc();
 313 
 314         return 0;
 315 }
 316 
 317 static void opal_imc_counters_shutdown(struct platform_device *pdev)
 318 {
 319         /*
 320          * Function only stops the engines which is bare minimum.
 321          * TODO: Need to handle proper memory cleanup and pmu
 322          * unregister.
 323          */
 324         disable_nest_pmu_counters();
 325         disable_core_pmu_counters();
 326 }
 327 
 328 static const struct of_device_id opal_imc_match[] = {
 329         { .compatible = IMC_DTB_COMPAT },
 330         {},
 331 };
 332 
 333 static struct platform_driver opal_imc_driver = {
 334         .driver = {
 335                 .name = "opal-imc-counters",
 336                 .of_match_table = opal_imc_match,
 337         },
 338         .probe = opal_imc_counters_probe,
 339         .shutdown = opal_imc_counters_shutdown,
 340 };
 341 
 342 builtin_platform_driver(opal_imc_driver);