This source file includes following definitions.
- pe_level_printk
- iommu_setup
- pci_reset_phbs_setup
- pnv_pci_is_m64
- pnv_pci_is_m64_flags
- pnv_ioda_init_pe
- pnv_ioda_reserve_pe
- pnv_ioda_alloc_pe
- pnv_ioda_free_pe
- pnv_ioda2_init_m64
- pnv_ioda_reserve_dev_m64_pe
- pnv_ioda1_init_m64
- pnv_ioda_reserve_m64_pe
- pnv_ioda_pick_m64_pe
- pnv_ioda_parse_m64_window
- pnv_ioda_freeze_pe
- pnv_ioda_unfreeze_pe
- pnv_ioda_get_pe_state
- pnv_ioda_get_pe
- pnv_ioda_set_one_peltv
- pnv_ioda_set_peltv
- pnv_ioda_deconfigure_pe
- pnv_ioda_configure_pe
- pnv_pci_vf_resource_shift
- pnv_ioda_setup_dev_PE
- pnv_ioda_setup_same_PE
- pnv_ioda_setup_bus_PE
- pnv_ioda_setup_npu_PE
- pnv_ioda_setup_npu_PEs
- pnv_pci_ioda_setup_PEs
- pnv_pci_vf_release_m64
- pnv_pci_vf_assign_m64
- pnv_pci_ioda2_release_dma_pe
- pnv_ioda_release_vf_PE
- pnv_pci_sriov_disable
- pnv_ioda_setup_vf_PE
- pnv_pci_sriov_enable
- pnv_pcibios_sriov_disable
- pnv_pcibios_sriov_enable
- pnv_pci_ioda_dma_dev_setup
- pnv_pci_ioda_dma_64bit_bypass
- pnv_pci_ioda_iommu_bypass_supported
- pnv_ioda_setup_bus_dma
- pnv_ioda_get_inval_reg
- pnv_pci_p7ioc_tce_invalidate
- pnv_ioda1_tce_build
- pnv_ioda_tce_xchg_no_kill
- pnv_ioda1_tce_free
- pnv_pci_phb3_tce_invalidate_entire
- pnv_pci_phb3_tce_invalidate_pe
- pnv_pci_phb3_tce_invalidate
- pnv_pci_ioda2_tce_invalidate_pe
- pnv_pci_ioda2_tce_invalidate
- pnv_pci_ioda2_tce_invalidate_entire
- pnv_ioda2_tce_build
- pnv_ioda2_tce_free
- pnv_pci_ioda_dev_dma_weight
- pnv_pci_ioda_pe_dma_weight
- pnv_pci_ioda1_setup_dma_pe
- pnv_pci_ioda2_set_window
- pnv_pci_ioda2_set_bypass
- pnv_pci_ioda2_create_table
- pnv_pci_ioda2_setup_default_config
- pnv_pci_ioda2_unset_window
- pnv_pci_ioda2_get_table_size
- pnv_pci_ioda2_create_table_userspace
- pnv_ioda2_take_ownership
- pnv_ioda2_release_ownership
- pnv_ioda_setup_bus_iommu_group_add_devices
- pnv_ioda_setup_bus_iommu_group
- pnv_pci_ioda_setup_iommu_api
- pnv_pci_ioda_setup_iommu_api
- pnv_ioda_parse_tce_sizes
- pnv_pci_ioda2_setup_dma_pe
- pnv_opal_pci_msi_eoi
- pnv_ioda2_msi_eoi
- pnv_set_msi_irq_chip
- is_pnv_opal_msi
- pnv_pci_ioda_msi_setup
- pnv_pci_init_ioda_msis
- pnv_pci_ioda_fixup_iov_resources
- pnv_pci_ioda_fixup_iov
- pnv_ioda_setup_pe_res
- pnv_ioda_setup_pe_seg
- pnv_pci_diag_data_set
- pnv_pci_ioda_create_dbgfs
- pnv_pci_enable_bridge
- pnv_pci_enable_bridges
- pnv_pci_ioda_fixup
- pnv_pci_window_alignment
- pnv_pci_fixup_bridge_resources
- pnv_pci_setup_bridge
- pnv_pci_default_alignment
- pnv_pci_iov_resource_alignment
- pnv_pci_enable_device_hook
- pnv_pci_ioda1_unset_window
- pnv_pci_ioda1_release_pe_dma
- pnv_pci_ioda2_release_pe_dma
- pnv_ioda_free_pe_seg
- pnv_ioda_release_pe_seg
- pnv_ioda_release_pe
- pnv_pci_release_device
- pnv_npu_disable_device
- pnv_pci_ioda_shutdown
- pnv_pci_init_ioda_phb
- pnv_pci_init_ioda2_phb
- pnv_pci_init_npu_phb
- pnv_pci_init_npu2_opencapi_phb
- pnv_npu2_opencapi_cfg_size_fixup
- pnv_pci_init_ioda_hub
1
2
3
4
5
6
7
8 #undef DEBUG
9
10 #include <linux/kernel.h>
11 #include <linux/pci.h>
12 #include <linux/crash_dump.h>
13 #include <linux/delay.h>
14 #include <linux/string.h>
15 #include <linux/init.h>
16 #include <linux/memblock.h>
17 #include <linux/irq.h>
18 #include <linux/io.h>
19 #include <linux/msi.h>
20 #include <linux/iommu.h>
21 #include <linux/rculist.h>
22 #include <linux/sizes.h>
23
24 #include <asm/sections.h>
25 #include <asm/io.h>
26 #include <asm/prom.h>
27 #include <asm/pci-bridge.h>
28 #include <asm/machdep.h>
29 #include <asm/msi_bitmap.h>
30 #include <asm/ppc-pci.h>
31 #include <asm/opal.h>
32 #include <asm/iommu.h>
33 #include <asm/tce.h>
34 #include <asm/xics.h>
35 #include <asm/debugfs.h>
36 #include <asm/firmware.h>
37 #include <asm/pnv-pci.h>
38 #include <asm/mmzone.h>
39
40 #include <misc/cxl-base.h>
41
42 #include "powernv.h"
43 #include "pci.h"
44 #include "../../../../drivers/pci/pci.h"
45
46 #define PNV_IODA1_M64_NUM 16
47 #define PNV_IODA1_M64_SEGS 8
48 #define PNV_IODA1_DMA32_SEGSIZE 0x10000000
49
50 static const char * const pnv_phb_names[] = { "IODA1", "IODA2", "NPU_NVLINK",
51 "NPU_OCAPI" };
52
53 static void pnv_pci_ioda2_set_bypass(struct pnv_ioda_pe *pe, bool enable);
54
55 void pe_level_printk(const struct pnv_ioda_pe *pe, const char *level,
56 const char *fmt, ...)
57 {
58 struct va_format vaf;
59 va_list args;
60 char pfix[32];
61
62 va_start(args, fmt);
63
64 vaf.fmt = fmt;
65 vaf.va = &args;
66
67 if (pe->flags & PNV_IODA_PE_DEV)
68 strlcpy(pfix, dev_name(&pe->pdev->dev), sizeof(pfix));
69 else if (pe->flags & (PNV_IODA_PE_BUS | PNV_IODA_PE_BUS_ALL))
70 sprintf(pfix, "%04x:%02x ",
71 pci_domain_nr(pe->pbus), pe->pbus->number);
72 #ifdef CONFIG_PCI_IOV
73 else if (pe->flags & PNV_IODA_PE_VF)
74 sprintf(pfix, "%04x:%02x:%2x.%d",
75 pci_domain_nr(pe->parent_dev->bus),
76 (pe->rid & 0xff00) >> 8,
77 PCI_SLOT(pe->rid), PCI_FUNC(pe->rid));
78 #endif
79
80 printk("%spci %s: [PE# %.2x] %pV",
81 level, pfix, pe->pe_number, &vaf);
82
83 va_end(args);
84 }
85
86 static bool pnv_iommu_bypass_disabled __read_mostly;
87 static bool pci_reset_phbs __read_mostly;
88
89 static int __init iommu_setup(char *str)
90 {
91 if (!str)
92 return -EINVAL;
93
94 while (*str) {
95 if (!strncmp(str, "nobypass", 8)) {
96 pnv_iommu_bypass_disabled = true;
97 pr_info("PowerNV: IOMMU bypass window disabled.\n");
98 break;
99 }
100 str += strcspn(str, ",");
101 if (*str == ',')
102 str++;
103 }
104
105 return 0;
106 }
107 early_param("iommu", iommu_setup);
108
109 static int __init pci_reset_phbs_setup(char *str)
110 {
111 pci_reset_phbs = true;
112 return 0;
113 }
114
115 early_param("ppc_pci_reset_phbs", pci_reset_phbs_setup);
116
117 static inline bool pnv_pci_is_m64(struct pnv_phb *phb, struct resource *r)
118 {
119
120
121
122
123
124
125
126 return (r->start >= phb->ioda.m64_base &&
127 r->start < (phb->ioda.m64_base + phb->ioda.m64_size));
128 }
129
130 static inline bool pnv_pci_is_m64_flags(unsigned long resource_flags)
131 {
132 unsigned long flags = (IORESOURCE_MEM_64 | IORESOURCE_PREFETCH);
133
134 return (resource_flags & flags) == flags;
135 }
136
137 static struct pnv_ioda_pe *pnv_ioda_init_pe(struct pnv_phb *phb, int pe_no)
138 {
139 s64 rc;
140
141 phb->ioda.pe_array[pe_no].phb = phb;
142 phb->ioda.pe_array[pe_no].pe_number = pe_no;
143
144
145
146
147
148
149 rc = opal_pci_eeh_freeze_clear(phb->opal_id, pe_no,
150 OPAL_EEH_ACTION_CLEAR_FREEZE_ALL);
151 if (rc != OPAL_SUCCESS && rc != OPAL_UNSUPPORTED)
152 pr_warn("%s: Error %lld unfreezing PHB#%x-PE#%x\n",
153 __func__, rc, phb->hose->global_number, pe_no);
154
155 return &phb->ioda.pe_array[pe_no];
156 }
157
158 static void pnv_ioda_reserve_pe(struct pnv_phb *phb, int pe_no)
159 {
160 if (!(pe_no >= 0 && pe_no < phb->ioda.total_pe_num)) {
161 pr_warn("%s: Invalid PE %x on PHB#%x\n",
162 __func__, pe_no, phb->hose->global_number);
163 return;
164 }
165
166 if (test_and_set_bit(pe_no, phb->ioda.pe_alloc))
167 pr_debug("%s: PE %x was reserved on PHB#%x\n",
168 __func__, pe_no, phb->hose->global_number);
169
170 pnv_ioda_init_pe(phb, pe_no);
171 }
172
173 static struct pnv_ioda_pe *pnv_ioda_alloc_pe(struct pnv_phb *phb)
174 {
175 long pe;
176
177 for (pe = phb->ioda.total_pe_num - 1; pe >= 0; pe--) {
178 if (!test_and_set_bit(pe, phb->ioda.pe_alloc))
179 return pnv_ioda_init_pe(phb, pe);
180 }
181
182 return NULL;
183 }
184
185 static void pnv_ioda_free_pe(struct pnv_ioda_pe *pe)
186 {
187 struct pnv_phb *phb = pe->phb;
188 unsigned int pe_num = pe->pe_number;
189
190 WARN_ON(pe->pdev);
191 WARN_ON(pe->npucomp);
192 kfree(pe->npucomp);
193 memset(pe, 0, sizeof(struct pnv_ioda_pe));
194 clear_bit(pe_num, phb->ioda.pe_alloc);
195 }
196
197
198 static int pnv_ioda2_init_m64(struct pnv_phb *phb)
199 {
200 const char *desc;
201 struct resource *r;
202 s64 rc;
203
204
205 rc = opal_pci_set_phb_mem_window(phb->opal_id,
206 OPAL_M64_WINDOW_TYPE,
207 phb->ioda.m64_bar_idx,
208 phb->ioda.m64_base,
209 0,
210 phb->ioda.m64_size);
211 if (rc != OPAL_SUCCESS) {
212 desc = "configuring";
213 goto fail;
214 }
215
216
217 rc = opal_pci_phb_mmio_enable(phb->opal_id,
218 OPAL_M64_WINDOW_TYPE,
219 phb->ioda.m64_bar_idx,
220 OPAL_ENABLE_M64_SPLIT);
221 if (rc != OPAL_SUCCESS) {
222 desc = "enabling";
223 goto fail;
224 }
225
226
227
228
229
230 r = &phb->hose->mem_resources[1];
231 if (phb->ioda.reserved_pe_idx == 0)
232 r->start += (2 * phb->ioda.m64_segsize);
233 else if (phb->ioda.reserved_pe_idx == (phb->ioda.total_pe_num - 1))
234 r->end -= (2 * phb->ioda.m64_segsize);
235 else
236 pr_warn(" Cannot strip M64 segment for reserved PE#%x\n",
237 phb->ioda.reserved_pe_idx);
238
239 return 0;
240
241 fail:
242 pr_warn(" Failure %lld %s M64 BAR#%d\n",
243 rc, desc, phb->ioda.m64_bar_idx);
244 opal_pci_phb_mmio_enable(phb->opal_id,
245 OPAL_M64_WINDOW_TYPE,
246 phb->ioda.m64_bar_idx,
247 OPAL_DISABLE_M64);
248 return -EIO;
249 }
250
251 static void pnv_ioda_reserve_dev_m64_pe(struct pci_dev *pdev,
252 unsigned long *pe_bitmap)
253 {
254 struct pci_controller *hose = pci_bus_to_host(pdev->bus);
255 struct pnv_phb *phb = hose->private_data;
256 struct resource *r;
257 resource_size_t base, sgsz, start, end;
258 int segno, i;
259
260 base = phb->ioda.m64_base;
261 sgsz = phb->ioda.m64_segsize;
262 for (i = 0; i <= PCI_ROM_RESOURCE; i++) {
263 r = &pdev->resource[i];
264 if (!r->parent || !pnv_pci_is_m64(phb, r))
265 continue;
266
267 start = _ALIGN_DOWN(r->start - base, sgsz);
268 end = _ALIGN_UP(r->end - base, sgsz);
269 for (segno = start / sgsz; segno < end / sgsz; segno++) {
270 if (pe_bitmap)
271 set_bit(segno, pe_bitmap);
272 else
273 pnv_ioda_reserve_pe(phb, segno);
274 }
275 }
276 }
277
278 static int pnv_ioda1_init_m64(struct pnv_phb *phb)
279 {
280 struct resource *r;
281 int index;
282
283
284
285
286
287
288 for (index = 0; index < PNV_IODA1_M64_NUM; index++) {
289 unsigned long base, segsz = phb->ioda.m64_segsize;
290 int64_t rc;
291
292 base = phb->ioda.m64_base +
293 index * PNV_IODA1_M64_SEGS * segsz;
294 rc = opal_pci_set_phb_mem_window(phb->opal_id,
295 OPAL_M64_WINDOW_TYPE, index, base, 0,
296 PNV_IODA1_M64_SEGS * segsz);
297 if (rc != OPAL_SUCCESS) {
298 pr_warn(" Error %lld setting M64 PHB#%x-BAR#%d\n",
299 rc, phb->hose->global_number, index);
300 goto fail;
301 }
302
303 rc = opal_pci_phb_mmio_enable(phb->opal_id,
304 OPAL_M64_WINDOW_TYPE, index,
305 OPAL_ENABLE_M64_SPLIT);
306 if (rc != OPAL_SUCCESS) {
307 pr_warn(" Error %lld enabling M64 PHB#%x-BAR#%d\n",
308 rc, phb->hose->global_number, index);
309 goto fail;
310 }
311 }
312
313
314
315
316
317 r = &phb->hose->mem_resources[1];
318 if (phb->ioda.reserved_pe_idx == 0)
319 r->start += (2 * phb->ioda.m64_segsize);
320 else if (phb->ioda.reserved_pe_idx == (phb->ioda.total_pe_num - 1))
321 r->end -= (2 * phb->ioda.m64_segsize);
322 else
323 WARN(1, "Wrong reserved PE#%x on PHB#%x\n",
324 phb->ioda.reserved_pe_idx, phb->hose->global_number);
325
326 return 0;
327
328 fail:
329 for ( ; index >= 0; index--)
330 opal_pci_phb_mmio_enable(phb->opal_id,
331 OPAL_M64_WINDOW_TYPE, index, OPAL_DISABLE_M64);
332
333 return -EIO;
334 }
335
336 static void pnv_ioda_reserve_m64_pe(struct pci_bus *bus,
337 unsigned long *pe_bitmap,
338 bool all)
339 {
340 struct pci_dev *pdev;
341
342 list_for_each_entry(pdev, &bus->devices, bus_list) {
343 pnv_ioda_reserve_dev_m64_pe(pdev, pe_bitmap);
344
345 if (all && pdev->subordinate)
346 pnv_ioda_reserve_m64_pe(pdev->subordinate,
347 pe_bitmap, all);
348 }
349 }
350
351 static struct pnv_ioda_pe *pnv_ioda_pick_m64_pe(struct pci_bus *bus, bool all)
352 {
353 struct pci_controller *hose = pci_bus_to_host(bus);
354 struct pnv_phb *phb = hose->private_data;
355 struct pnv_ioda_pe *master_pe, *pe;
356 unsigned long size, *pe_alloc;
357 int i;
358
359
360 if (pci_is_root_bus(bus))
361 return NULL;
362
363
364 size = _ALIGN_UP(phb->ioda.total_pe_num / 8, sizeof(unsigned long));
365 pe_alloc = kzalloc(size, GFP_KERNEL);
366 if (!pe_alloc) {
367 pr_warn("%s: Out of memory !\n",
368 __func__);
369 return NULL;
370 }
371
372
373 pnv_ioda_reserve_m64_pe(bus, pe_alloc, all);
374
375
376
377
378
379
380 if (bitmap_empty(pe_alloc, phb->ioda.total_pe_num)) {
381 kfree(pe_alloc);
382 return NULL;
383 }
384
385
386
387
388
389 master_pe = NULL;
390 i = -1;
391 while ((i = find_next_bit(pe_alloc, phb->ioda.total_pe_num, i + 1)) <
392 phb->ioda.total_pe_num) {
393 pe = &phb->ioda.pe_array[i];
394
395 phb->ioda.m64_segmap[pe->pe_number] = pe->pe_number;
396 if (!master_pe) {
397 pe->flags |= PNV_IODA_PE_MASTER;
398 INIT_LIST_HEAD(&pe->slaves);
399 master_pe = pe;
400 } else {
401 pe->flags |= PNV_IODA_PE_SLAVE;
402 pe->master = master_pe;
403 list_add_tail(&pe->list, &master_pe->slaves);
404 }
405
406
407
408
409
410
411
412
413 if (phb->type == PNV_PHB_IODA1) {
414 int64_t rc;
415
416 rc = opal_pci_map_pe_mmio_window(phb->opal_id,
417 pe->pe_number, OPAL_M64_WINDOW_TYPE,
418 pe->pe_number / PNV_IODA1_M64_SEGS,
419 pe->pe_number % PNV_IODA1_M64_SEGS);
420 if (rc != OPAL_SUCCESS)
421 pr_warn("%s: Error %lld mapping M64 for PHB#%x-PE#%x\n",
422 __func__, rc, phb->hose->global_number,
423 pe->pe_number);
424 }
425 }
426
427 kfree(pe_alloc);
428 return master_pe;
429 }
430
431 static void __init pnv_ioda_parse_m64_window(struct pnv_phb *phb)
432 {
433 struct pci_controller *hose = phb->hose;
434 struct device_node *dn = hose->dn;
435 struct resource *res;
436 u32 m64_range[2], i;
437 const __be32 *r;
438 u64 pci_addr;
439
440 if (phb->type != PNV_PHB_IODA1 && phb->type != PNV_PHB_IODA2) {
441 pr_info(" Not support M64 window\n");
442 return;
443 }
444
445 if (!firmware_has_feature(FW_FEATURE_OPAL)) {
446 pr_info(" Firmware too old to support M64 window\n");
447 return;
448 }
449
450 r = of_get_property(dn, "ibm,opal-m64-window", NULL);
451 if (!r) {
452 pr_info(" No <ibm,opal-m64-window> on %pOF\n",
453 dn);
454 return;
455 }
456
457
458
459
460
461 if (of_property_read_u32_array(dn, "ibm,opal-available-m64-ranges",
462 m64_range, 2)) {
463
464 m64_range[0] = 0;
465 m64_range[1] = 16;
466 }
467
468 if (m64_range[1] > 63) {
469 pr_warn("%s: Limiting M64 range to 63 (from %d) on PHB#%x\n",
470 __func__, m64_range[1], phb->hose->global_number);
471 m64_range[1] = 63;
472 }
473
474 if (m64_range[1] <= m64_range[0]) {
475 pr_warn("%s: M64 empty, disabling M64 usage on PHB#%x\n",
476 __func__, phb->hose->global_number);
477 return;
478 }
479
480
481 res = &hose->mem_resources[1];
482 res->name = dn->full_name;
483 res->start = of_translate_address(dn, r + 2);
484 res->end = res->start + of_read_number(r + 4, 2) - 1;
485 res->flags = (IORESOURCE_MEM | IORESOURCE_MEM_64 | IORESOURCE_PREFETCH);
486 pci_addr = of_read_number(r, 2);
487 hose->mem_offset[1] = res->start - pci_addr;
488
489 phb->ioda.m64_size = resource_size(res);
490 phb->ioda.m64_segsize = phb->ioda.m64_size / phb->ioda.total_pe_num;
491 phb->ioda.m64_base = pci_addr;
492
493
494 pr_info(" MEM 0x%016llx..0x%016llx -> 0x%016llx (M64 #%d..%d)\n",
495 res->start, res->end, pci_addr, m64_range[0],
496 m64_range[0] + m64_range[1] - 1);
497
498
499 phb->ioda.m64_bar_alloc = (unsigned long)-1;
500
501
502 m64_range[1]--;
503 phb->ioda.m64_bar_idx = m64_range[0] + m64_range[1];
504
505 pr_info(" Using M64 #%d as default window\n", phb->ioda.m64_bar_idx);
506
507
508 for (i = m64_range[0]; i < m64_range[1]; i++)
509 clear_bit(i, &phb->ioda.m64_bar_alloc);
510
511
512
513
514
515 if (phb->type == PNV_PHB_IODA1)
516 phb->init_m64 = pnv_ioda1_init_m64;
517 else
518 phb->init_m64 = pnv_ioda2_init_m64;
519 }
520
521 static void pnv_ioda_freeze_pe(struct pnv_phb *phb, int pe_no)
522 {
523 struct pnv_ioda_pe *pe = &phb->ioda.pe_array[pe_no];
524 struct pnv_ioda_pe *slave;
525 s64 rc;
526
527
528 if (pe->flags & PNV_IODA_PE_SLAVE) {
529 pe = pe->master;
530 if (WARN_ON(!pe || !(pe->flags & PNV_IODA_PE_MASTER)))
531 return;
532
533 pe_no = pe->pe_number;
534 }
535
536
537 rc = opal_pci_eeh_freeze_set(phb->opal_id,
538 pe_no,
539 OPAL_EEH_ACTION_SET_FREEZE_ALL);
540 if (rc != OPAL_SUCCESS) {
541 pr_warn("%s: Failure %lld freezing PHB#%x-PE#%x\n",
542 __func__, rc, phb->hose->global_number, pe_no);
543 return;
544 }
545
546
547 if (!(pe->flags & PNV_IODA_PE_MASTER))
548 return;
549
550 list_for_each_entry(slave, &pe->slaves, list) {
551 rc = opal_pci_eeh_freeze_set(phb->opal_id,
552 slave->pe_number,
553 OPAL_EEH_ACTION_SET_FREEZE_ALL);
554 if (rc != OPAL_SUCCESS)
555 pr_warn("%s: Failure %lld freezing PHB#%x-PE#%x\n",
556 __func__, rc, phb->hose->global_number,
557 slave->pe_number);
558 }
559 }
560
561 static int pnv_ioda_unfreeze_pe(struct pnv_phb *phb, int pe_no, int opt)
562 {
563 struct pnv_ioda_pe *pe, *slave;
564 s64 rc;
565
566
567 pe = &phb->ioda.pe_array[pe_no];
568 if (pe->flags & PNV_IODA_PE_SLAVE) {
569 pe = pe->master;
570 WARN_ON(!pe || !(pe->flags & PNV_IODA_PE_MASTER));
571 pe_no = pe->pe_number;
572 }
573
574
575 rc = opal_pci_eeh_freeze_clear(phb->opal_id, pe_no, opt);
576 if (rc != OPAL_SUCCESS) {
577 pr_warn("%s: Failure %lld clear %d on PHB#%x-PE#%x\n",
578 __func__, rc, opt, phb->hose->global_number, pe_no);
579 return -EIO;
580 }
581
582 if (!(pe->flags & PNV_IODA_PE_MASTER))
583 return 0;
584
585
586 list_for_each_entry(slave, &pe->slaves, list) {
587 rc = opal_pci_eeh_freeze_clear(phb->opal_id,
588 slave->pe_number,
589 opt);
590 if (rc != OPAL_SUCCESS) {
591 pr_warn("%s: Failure %lld clear %d on PHB#%x-PE#%x\n",
592 __func__, rc, opt, phb->hose->global_number,
593 slave->pe_number);
594 return -EIO;
595 }
596 }
597
598 return 0;
599 }
600
601 static int pnv_ioda_get_pe_state(struct pnv_phb *phb, int pe_no)
602 {
603 struct pnv_ioda_pe *slave, *pe;
604 u8 fstate = 0, state;
605 __be16 pcierr = 0;
606 s64 rc;
607
608
609 if (pe_no < 0 || pe_no >= phb->ioda.total_pe_num)
610 return OPAL_EEH_STOPPED_PERM_UNAVAIL;
611
612
613
614
615
616 pe = &phb->ioda.pe_array[pe_no];
617 if (pe->flags & PNV_IODA_PE_SLAVE) {
618 pe = pe->master;
619 WARN_ON(!pe || !(pe->flags & PNV_IODA_PE_MASTER));
620 pe_no = pe->pe_number;
621 }
622
623
624 rc = opal_pci_eeh_freeze_status(phb->opal_id, pe_no,
625 &state, &pcierr, NULL);
626 if (rc != OPAL_SUCCESS) {
627 pr_warn("%s: Failure %lld getting "
628 "PHB#%x-PE#%x state\n",
629 __func__, rc,
630 phb->hose->global_number, pe_no);
631 return OPAL_EEH_STOPPED_TEMP_UNAVAIL;
632 }
633
634
635 if (!(pe->flags & PNV_IODA_PE_MASTER))
636 return state;
637
638 list_for_each_entry(slave, &pe->slaves, list) {
639 rc = opal_pci_eeh_freeze_status(phb->opal_id,
640 slave->pe_number,
641 &fstate,
642 &pcierr,
643 NULL);
644 if (rc != OPAL_SUCCESS) {
645 pr_warn("%s: Failure %lld getting "
646 "PHB#%x-PE#%x state\n",
647 __func__, rc,
648 phb->hose->global_number, slave->pe_number);
649 return OPAL_EEH_STOPPED_TEMP_UNAVAIL;
650 }
651
652
653
654
655
656 if (fstate > state)
657 state = fstate;
658 }
659
660 return state;
661 }
662
663 struct pnv_ioda_pe *pnv_ioda_get_pe(struct pci_dev *dev)
664 {
665 struct pci_controller *hose = pci_bus_to_host(dev->bus);
666 struct pnv_phb *phb = hose->private_data;
667 struct pci_dn *pdn = pci_get_pdn(dev);
668
669 if (!pdn)
670 return NULL;
671 if (pdn->pe_number == IODA_INVALID_PE)
672 return NULL;
673 return &phb->ioda.pe_array[pdn->pe_number];
674 }
675
676 static int pnv_ioda_set_one_peltv(struct pnv_phb *phb,
677 struct pnv_ioda_pe *parent,
678 struct pnv_ioda_pe *child,
679 bool is_add)
680 {
681 const char *desc = is_add ? "adding" : "removing";
682 uint8_t op = is_add ? OPAL_ADD_PE_TO_DOMAIN :
683 OPAL_REMOVE_PE_FROM_DOMAIN;
684 struct pnv_ioda_pe *slave;
685 long rc;
686
687
688 rc = opal_pci_set_peltv(phb->opal_id, parent->pe_number,
689 child->pe_number, op);
690 if (rc != OPAL_SUCCESS) {
691 pe_warn(child, "OPAL error %ld %s to parent PELTV\n",
692 rc, desc);
693 return -ENXIO;
694 }
695
696 if (!(child->flags & PNV_IODA_PE_MASTER))
697 return 0;
698
699
700 list_for_each_entry(slave, &child->slaves, list) {
701 rc = opal_pci_set_peltv(phb->opal_id, parent->pe_number,
702 slave->pe_number, op);
703 if (rc != OPAL_SUCCESS) {
704 pe_warn(slave, "OPAL error %ld %s to parent PELTV\n",
705 rc, desc);
706 return -ENXIO;
707 }
708 }
709
710 return 0;
711 }
712
713 static int pnv_ioda_set_peltv(struct pnv_phb *phb,
714 struct pnv_ioda_pe *pe,
715 bool is_add)
716 {
717 struct pnv_ioda_pe *slave;
718 struct pci_dev *pdev = NULL;
719 int ret;
720
721
722
723
724
725 if (is_add) {
726 opal_pci_eeh_freeze_clear(phb->opal_id, pe->pe_number,
727 OPAL_EEH_ACTION_CLEAR_FREEZE_ALL);
728 if (pe->flags & PNV_IODA_PE_MASTER) {
729 list_for_each_entry(slave, &pe->slaves, list)
730 opal_pci_eeh_freeze_clear(phb->opal_id,
731 slave->pe_number,
732 OPAL_EEH_ACTION_CLEAR_FREEZE_ALL);
733 }
734 }
735
736
737
738
739
740
741
742 ret = pnv_ioda_set_one_peltv(phb, pe, pe, is_add);
743 if (ret)
744 return ret;
745
746
747 if (pe->flags & PNV_IODA_PE_MASTER) {
748 list_for_each_entry(slave, &pe->slaves, list) {
749 ret = pnv_ioda_set_one_peltv(phb, slave, pe, is_add);
750 if (ret)
751 return ret;
752 }
753 }
754
755 if (pe->flags & (PNV_IODA_PE_BUS_ALL | PNV_IODA_PE_BUS))
756 pdev = pe->pbus->self;
757 else if (pe->flags & PNV_IODA_PE_DEV)
758 pdev = pe->pdev->bus->self;
759 #ifdef CONFIG_PCI_IOV
760 else if (pe->flags & PNV_IODA_PE_VF)
761 pdev = pe->parent_dev;
762 #endif
763 while (pdev) {
764 struct pci_dn *pdn = pci_get_pdn(pdev);
765 struct pnv_ioda_pe *parent;
766
767 if (pdn && pdn->pe_number != IODA_INVALID_PE) {
768 parent = &phb->ioda.pe_array[pdn->pe_number];
769 ret = pnv_ioda_set_one_peltv(phb, parent, pe, is_add);
770 if (ret)
771 return ret;
772 }
773
774 pdev = pdev->bus->self;
775 }
776
777 return 0;
778 }
779
780 static int pnv_ioda_deconfigure_pe(struct pnv_phb *phb, struct pnv_ioda_pe *pe)
781 {
782 struct pci_dev *parent;
783 uint8_t bcomp, dcomp, fcomp;
784 int64_t rc;
785 long rid_end, rid;
786
787
788 if (pe->pbus) {
789 int count;
790
791 dcomp = OPAL_IGNORE_RID_DEVICE_NUMBER;
792 fcomp = OPAL_IGNORE_RID_FUNCTION_NUMBER;
793 parent = pe->pbus->self;
794 if (pe->flags & PNV_IODA_PE_BUS_ALL)
795 count = pe->pbus->busn_res.end - pe->pbus->busn_res.start + 1;
796 else
797 count = 1;
798
799 switch(count) {
800 case 1: bcomp = OpalPciBusAll; break;
801 case 2: bcomp = OpalPciBus7Bits; break;
802 case 4: bcomp = OpalPciBus6Bits; break;
803 case 8: bcomp = OpalPciBus5Bits; break;
804 case 16: bcomp = OpalPciBus4Bits; break;
805 case 32: bcomp = OpalPciBus3Bits; break;
806 default:
807 dev_err(&pe->pbus->dev, "Number of subordinate buses %d unsupported\n",
808 count);
809
810 bcomp = OpalPciBusAll;
811 }
812 rid_end = pe->rid + (count << 8);
813 } else {
814 #ifdef CONFIG_PCI_IOV
815 if (pe->flags & PNV_IODA_PE_VF)
816 parent = pe->parent_dev;
817 else
818 #endif
819 parent = pe->pdev->bus->self;
820 bcomp = OpalPciBusAll;
821 dcomp = OPAL_COMPARE_RID_DEVICE_NUMBER;
822 fcomp = OPAL_COMPARE_RID_FUNCTION_NUMBER;
823 rid_end = pe->rid + 1;
824 }
825
826
827 for (rid = pe->rid; rid < rid_end; rid++)
828 phb->ioda.pe_rmap[rid] = IODA_INVALID_PE;
829
830
831 while (parent) {
832 struct pci_dn *pdn = pci_get_pdn(parent);
833 if (pdn && pdn->pe_number != IODA_INVALID_PE) {
834 rc = opal_pci_set_peltv(phb->opal_id, pdn->pe_number,
835 pe->pe_number, OPAL_REMOVE_PE_FROM_DOMAIN);
836
837 }
838 parent = parent->bus->self;
839 }
840
841 opal_pci_eeh_freeze_clear(phb->opal_id, pe->pe_number,
842 OPAL_EEH_ACTION_CLEAR_FREEZE_ALL);
843
844
845 rc = opal_pci_set_peltv(phb->opal_id, pe->pe_number,
846 pe->pe_number, OPAL_REMOVE_PE_FROM_DOMAIN);
847 if (rc)
848 pe_warn(pe, "OPAL error %lld remove self from PELTV\n", rc);
849 rc = opal_pci_set_pe(phb->opal_id, pe->pe_number, pe->rid,
850 bcomp, dcomp, fcomp, OPAL_UNMAP_PE);
851 if (rc)
852 pe_err(pe, "OPAL error %lld trying to setup PELT table\n", rc);
853
854 pe->pbus = NULL;
855 pe->pdev = NULL;
856 #ifdef CONFIG_PCI_IOV
857 pe->parent_dev = NULL;
858 #endif
859
860 return 0;
861 }
862
863 static int pnv_ioda_configure_pe(struct pnv_phb *phb, struct pnv_ioda_pe *pe)
864 {
865 struct pci_dev *parent;
866 uint8_t bcomp, dcomp, fcomp;
867 long rc, rid_end, rid;
868
869
870 if (pe->pbus) {
871 int count;
872
873 dcomp = OPAL_IGNORE_RID_DEVICE_NUMBER;
874 fcomp = OPAL_IGNORE_RID_FUNCTION_NUMBER;
875 parent = pe->pbus->self;
876 if (pe->flags & PNV_IODA_PE_BUS_ALL)
877 count = pe->pbus->busn_res.end - pe->pbus->busn_res.start + 1;
878 else
879 count = 1;
880
881 switch(count) {
882 case 1: bcomp = OpalPciBusAll; break;
883 case 2: bcomp = OpalPciBus7Bits; break;
884 case 4: bcomp = OpalPciBus6Bits; break;
885 case 8: bcomp = OpalPciBus5Bits; break;
886 case 16: bcomp = OpalPciBus4Bits; break;
887 case 32: bcomp = OpalPciBus3Bits; break;
888 default:
889 dev_err(&pe->pbus->dev, "Number of subordinate buses %d unsupported\n",
890 count);
891
892 bcomp = OpalPciBusAll;
893 }
894 rid_end = pe->rid + (count << 8);
895 } else {
896 #ifdef CONFIG_PCI_IOV
897 if (pe->flags & PNV_IODA_PE_VF)
898 parent = pe->parent_dev;
899 else
900 #endif
901 parent = pe->pdev->bus->self;
902 bcomp = OpalPciBusAll;
903 dcomp = OPAL_COMPARE_RID_DEVICE_NUMBER;
904 fcomp = OPAL_COMPARE_RID_FUNCTION_NUMBER;
905 rid_end = pe->rid + 1;
906 }
907
908
909
910
911
912
913
914 rc = opal_pci_set_pe(phb->opal_id, pe->pe_number, pe->rid,
915 bcomp, dcomp, fcomp, OPAL_MAP_PE);
916 if (rc) {
917 pe_err(pe, "OPAL error %ld trying to setup PELT table\n", rc);
918 return -ENXIO;
919 }
920
921
922
923
924
925 if (phb->type != PNV_PHB_NPU_NVLINK && phb->type != PNV_PHB_NPU_OCAPI)
926 pnv_ioda_set_peltv(phb, pe, true);
927
928
929 for (rid = pe->rid; rid < rid_end; rid++)
930 phb->ioda.pe_rmap[rid] = pe->pe_number;
931
932
933 if (phb->type != PNV_PHB_IODA1) {
934 pe->mve_number = 0;
935 goto out;
936 }
937
938 pe->mve_number = pe->pe_number;
939 rc = opal_pci_set_mve(phb->opal_id, pe->mve_number, pe->pe_number);
940 if (rc != OPAL_SUCCESS) {
941 pe_err(pe, "OPAL error %ld setting up MVE %x\n",
942 rc, pe->mve_number);
943 pe->mve_number = -1;
944 } else {
945 rc = opal_pci_set_mve_enable(phb->opal_id,
946 pe->mve_number, OPAL_ENABLE_MVE);
947 if (rc) {
948 pe_err(pe, "OPAL error %ld enabling MVE %x\n",
949 rc, pe->mve_number);
950 pe->mve_number = -1;
951 }
952 }
953
954 out:
955 return 0;
956 }
957
958 #ifdef CONFIG_PCI_IOV
959 static int pnv_pci_vf_resource_shift(struct pci_dev *dev, int offset)
960 {
961 struct pci_dn *pdn = pci_get_pdn(dev);
962 int i;
963 struct resource *res, res2;
964 resource_size_t size;
965 u16 num_vfs;
966
967 if (!dev->is_physfn)
968 return -EINVAL;
969
970
971
972
973
974
975
976
977
978 num_vfs = pdn->num_vfs;
979 for (i = 0; i < PCI_SRIOV_NUM_BARS; i++) {
980 res = &dev->resource[i + PCI_IOV_RESOURCES];
981 if (!res->flags || !res->parent)
982 continue;
983
984
985
986
987
988
989
990 size = pci_iov_resource_size(dev, i + PCI_IOV_RESOURCES);
991 res2.flags = res->flags;
992 res2.start = res->start + (size * offset);
993 res2.end = res2.start + (size * num_vfs) - 1;
994
995 if (res2.end > res->end) {
996 dev_err(&dev->dev, "VF BAR%d: %pR would extend past %pR (trying to enable %d VFs shifted by %d)\n",
997 i, &res2, res, num_vfs, offset);
998 return -EBUSY;
999 }
1000 }
1001
1002
1003
1004
1005
1006
1007
1008
1009
1010 for (i = 0; i < PCI_SRIOV_NUM_BARS; i++) {
1011 res = &dev->resource[i + PCI_IOV_RESOURCES];
1012 if (!res->flags || !res->parent)
1013 continue;
1014
1015 size = pci_iov_resource_size(dev, i + PCI_IOV_RESOURCES);
1016 res2 = *res;
1017 res->start += size * offset;
1018
1019 dev_info(&dev->dev, "VF BAR%d: %pR shifted to %pR (%sabling %d VFs shifted by %d)\n",
1020 i, &res2, res, (offset > 0) ? "En" : "Dis",
1021 num_vfs, offset);
1022
1023 if (offset < 0) {
1024 devm_release_resource(&dev->dev, &pdn->holes[i]);
1025 memset(&pdn->holes[i], 0, sizeof(pdn->holes[i]));
1026 }
1027
1028 pci_update_resource(dev, i + PCI_IOV_RESOURCES);
1029
1030 if (offset > 0) {
1031 pdn->holes[i].start = res2.start;
1032 pdn->holes[i].end = res2.start + size * offset - 1;
1033 pdn->holes[i].flags = IORESOURCE_BUS;
1034 pdn->holes[i].name = "pnv_iov_reserved";
1035 devm_request_resource(&dev->dev, res->parent,
1036 &pdn->holes[i]);
1037 }
1038 }
1039 return 0;
1040 }
1041 #endif
1042
1043 static struct pnv_ioda_pe *pnv_ioda_setup_dev_PE(struct pci_dev *dev)
1044 {
1045 struct pci_controller *hose = pci_bus_to_host(dev->bus);
1046 struct pnv_phb *phb = hose->private_data;
1047 struct pci_dn *pdn = pci_get_pdn(dev);
1048 struct pnv_ioda_pe *pe;
1049
1050 if (!pdn) {
1051 pr_err("%s: Device tree node not associated properly\n",
1052 pci_name(dev));
1053 return NULL;
1054 }
1055 if (pdn->pe_number != IODA_INVALID_PE)
1056 return NULL;
1057
1058 pe = pnv_ioda_alloc_pe(phb);
1059 if (!pe) {
1060 pr_warn("%s: Not enough PE# available, disabling device\n",
1061 pci_name(dev));
1062 return NULL;
1063 }
1064
1065
1066
1067
1068
1069
1070
1071
1072 pci_dev_get(dev);
1073 pdn->pe_number = pe->pe_number;
1074 pe->flags = PNV_IODA_PE_DEV;
1075 pe->pdev = dev;
1076 pe->pbus = NULL;
1077 pe->mve_number = -1;
1078 pe->rid = dev->bus->number << 8 | pdn->devfn;
1079
1080 pe_info(pe, "Associated device to PE\n");
1081
1082 if (pnv_ioda_configure_pe(phb, pe)) {
1083
1084 pnv_ioda_free_pe(pe);
1085 pdn->pe_number = IODA_INVALID_PE;
1086 pe->pdev = NULL;
1087 pci_dev_put(dev);
1088 return NULL;
1089 }
1090
1091
1092 list_add_tail(&pe->list, &phb->ioda.pe_list);
1093
1094 return pe;
1095 }
1096
1097 static void pnv_ioda_setup_same_PE(struct pci_bus *bus, struct pnv_ioda_pe *pe)
1098 {
1099 struct pci_dev *dev;
1100
1101 list_for_each_entry(dev, &bus->devices, bus_list) {
1102 struct pci_dn *pdn = pci_get_pdn(dev);
1103
1104 if (pdn == NULL) {
1105 pr_warn("%s: No device node associated with device !\n",
1106 pci_name(dev));
1107 continue;
1108 }
1109
1110
1111
1112
1113
1114
1115 if (pdn->pe_number != IODA_INVALID_PE)
1116 continue;
1117
1118 pe->device_count++;
1119 pdn->pe_number = pe->pe_number;
1120 if ((pe->flags & PNV_IODA_PE_BUS_ALL) && dev->subordinate)
1121 pnv_ioda_setup_same_PE(dev->subordinate, pe);
1122 }
1123 }
1124
1125
1126
1127
1128
1129
1130
1131 static struct pnv_ioda_pe *pnv_ioda_setup_bus_PE(struct pci_bus *bus, bool all)
1132 {
1133 struct pci_controller *hose = pci_bus_to_host(bus);
1134 struct pnv_phb *phb = hose->private_data;
1135 struct pnv_ioda_pe *pe = NULL;
1136 unsigned int pe_num;
1137
1138
1139
1140
1141
1142 pe_num = phb->ioda.pe_rmap[bus->number << 8];
1143 if (pe_num != IODA_INVALID_PE) {
1144 pe = &phb->ioda.pe_array[pe_num];
1145 pnv_ioda_setup_same_PE(bus, pe);
1146 return NULL;
1147 }
1148
1149
1150 if (pci_is_root_bus(bus) &&
1151 phb->ioda.root_pe_idx != IODA_INVALID_PE)
1152 pe = &phb->ioda.pe_array[phb->ioda.root_pe_idx];
1153
1154
1155 if (!pe)
1156 pe = pnv_ioda_pick_m64_pe(bus, all);
1157
1158
1159 if (!pe)
1160 pe = pnv_ioda_alloc_pe(phb);
1161
1162 if (!pe) {
1163 pr_warn("%s: Not enough PE# available for PCI bus %04x:%02x\n",
1164 __func__, pci_domain_nr(bus), bus->number);
1165 return NULL;
1166 }
1167
1168 pe->flags |= (all ? PNV_IODA_PE_BUS_ALL : PNV_IODA_PE_BUS);
1169 pe->pbus = bus;
1170 pe->pdev = NULL;
1171 pe->mve_number = -1;
1172 pe->rid = bus->busn_res.start << 8;
1173
1174 if (all)
1175 pe_info(pe, "Secondary bus %pad..%pad associated with PE#%x\n",
1176 &bus->busn_res.start, &bus->busn_res.end,
1177 pe->pe_number);
1178 else
1179 pe_info(pe, "Secondary bus %pad associated with PE#%x\n",
1180 &bus->busn_res.start, pe->pe_number);
1181
1182 if (pnv_ioda_configure_pe(phb, pe)) {
1183
1184 pnv_ioda_free_pe(pe);
1185 pe->pbus = NULL;
1186 return NULL;
1187 }
1188
1189
1190 pnv_ioda_setup_same_PE(bus, pe);
1191
1192
1193 list_add_tail(&pe->list, &phb->ioda.pe_list);
1194
1195 return pe;
1196 }
1197
1198 static struct pnv_ioda_pe *pnv_ioda_setup_npu_PE(struct pci_dev *npu_pdev)
1199 {
1200 int pe_num, found_pe = false, rc;
1201 long rid;
1202 struct pnv_ioda_pe *pe;
1203 struct pci_dev *gpu_pdev;
1204 struct pci_dn *npu_pdn;
1205 struct pci_controller *hose = pci_bus_to_host(npu_pdev->bus);
1206 struct pnv_phb *phb = hose->private_data;
1207
1208
1209
1210
1211
1212
1213
1214
1215
1216
1217 gpu_pdev = pnv_pci_get_gpu_dev(npu_pdev);
1218 for (pe_num = 0; pe_num < phb->ioda.total_pe_num; pe_num++) {
1219 pe = &phb->ioda.pe_array[pe_num];
1220 if (!pe->pdev)
1221 continue;
1222
1223 if (pnv_pci_get_gpu_dev(pe->pdev) == gpu_pdev) {
1224
1225
1226
1227
1228
1229 dev_info(&npu_pdev->dev,
1230 "Associating to existing PE %x\n", pe_num);
1231 pci_dev_get(npu_pdev);
1232 npu_pdn = pci_get_pdn(npu_pdev);
1233 rid = npu_pdev->bus->number << 8 | npu_pdn->devfn;
1234 npu_pdn->pe_number = pe_num;
1235 phb->ioda.pe_rmap[rid] = pe->pe_number;
1236
1237
1238 rc = opal_pci_set_pe(phb->opal_id, pe_num, rid,
1239 OpalPciBusAll,
1240 OPAL_COMPARE_RID_DEVICE_NUMBER,
1241 OPAL_COMPARE_RID_FUNCTION_NUMBER,
1242 OPAL_MAP_PE);
1243 WARN_ON(rc != OPAL_SUCCESS);
1244 found_pe = true;
1245 break;
1246 }
1247 }
1248
1249 if (!found_pe)
1250
1251
1252
1253
1254 return pnv_ioda_setup_dev_PE(npu_pdev);
1255 else
1256 return pe;
1257 }
1258
1259 static void pnv_ioda_setup_npu_PEs(struct pci_bus *bus)
1260 {
1261 struct pci_dev *pdev;
1262
1263 list_for_each_entry(pdev, &bus->devices, bus_list)
1264 pnv_ioda_setup_npu_PE(pdev);
1265 }
1266
1267 static void pnv_pci_ioda_setup_PEs(void)
1268 {
1269 struct pci_controller *hose;
1270 struct pnv_phb *phb;
1271 struct pci_bus *bus;
1272 struct pci_dev *pdev;
1273 struct pnv_ioda_pe *pe;
1274
1275 list_for_each_entry(hose, &hose_list, list_node) {
1276 phb = hose->private_data;
1277 if (phb->type == PNV_PHB_NPU_NVLINK) {
1278
1279 pnv_ioda_reserve_pe(phb, 0);
1280 pnv_ioda_setup_npu_PEs(hose->bus);
1281 if (phb->model == PNV_PHB_MODEL_NPU2)
1282 WARN_ON_ONCE(pnv_npu2_init(hose));
1283 }
1284 if (phb->type == PNV_PHB_NPU_OCAPI) {
1285 bus = hose->bus;
1286 list_for_each_entry(pdev, &bus->devices, bus_list)
1287 pnv_ioda_setup_dev_PE(pdev);
1288 }
1289 }
1290 list_for_each_entry(hose, &hose_list, list_node) {
1291 phb = hose->private_data;
1292 if (phb->type != PNV_PHB_IODA2)
1293 continue;
1294
1295 list_for_each_entry(pe, &phb->ioda.pe_list, list)
1296 pnv_npu2_map_lpar(pe, MSR_DR | MSR_PR | MSR_HV);
1297 }
1298 }
1299
1300 #ifdef CONFIG_PCI_IOV
1301 static int pnv_pci_vf_release_m64(struct pci_dev *pdev, u16 num_vfs)
1302 {
1303 struct pci_bus *bus;
1304 struct pci_controller *hose;
1305 struct pnv_phb *phb;
1306 struct pci_dn *pdn;
1307 int i, j;
1308 int m64_bars;
1309
1310 bus = pdev->bus;
1311 hose = pci_bus_to_host(bus);
1312 phb = hose->private_data;
1313 pdn = pci_get_pdn(pdev);
1314
1315 if (pdn->m64_single_mode)
1316 m64_bars = num_vfs;
1317 else
1318 m64_bars = 1;
1319
1320 for (i = 0; i < PCI_SRIOV_NUM_BARS; i++)
1321 for (j = 0; j < m64_bars; j++) {
1322 if (pdn->m64_map[j][i] == IODA_INVALID_M64)
1323 continue;
1324 opal_pci_phb_mmio_enable(phb->opal_id,
1325 OPAL_M64_WINDOW_TYPE, pdn->m64_map[j][i], 0);
1326 clear_bit(pdn->m64_map[j][i], &phb->ioda.m64_bar_alloc);
1327 pdn->m64_map[j][i] = IODA_INVALID_M64;
1328 }
1329
1330 kfree(pdn->m64_map);
1331 return 0;
1332 }
1333
1334 static int pnv_pci_vf_assign_m64(struct pci_dev *pdev, u16 num_vfs)
1335 {
1336 struct pci_bus *bus;
1337 struct pci_controller *hose;
1338 struct pnv_phb *phb;
1339 struct pci_dn *pdn;
1340 unsigned int win;
1341 struct resource *res;
1342 int i, j;
1343 int64_t rc;
1344 int total_vfs;
1345 resource_size_t size, start;
1346 int pe_num;
1347 int m64_bars;
1348
1349 bus = pdev->bus;
1350 hose = pci_bus_to_host(bus);
1351 phb = hose->private_data;
1352 pdn = pci_get_pdn(pdev);
1353 total_vfs = pci_sriov_get_totalvfs(pdev);
1354
1355 if (pdn->m64_single_mode)
1356 m64_bars = num_vfs;
1357 else
1358 m64_bars = 1;
1359
1360 pdn->m64_map = kmalloc_array(m64_bars,
1361 sizeof(*pdn->m64_map),
1362 GFP_KERNEL);
1363 if (!pdn->m64_map)
1364 return -ENOMEM;
1365
1366 for (i = 0; i < m64_bars ; i++)
1367 for (j = 0; j < PCI_SRIOV_NUM_BARS; j++)
1368 pdn->m64_map[i][j] = IODA_INVALID_M64;
1369
1370
1371 for (i = 0; i < PCI_SRIOV_NUM_BARS; i++) {
1372 res = &pdev->resource[i + PCI_IOV_RESOURCES];
1373 if (!res->flags || !res->parent)
1374 continue;
1375
1376 for (j = 0; j < m64_bars; j++) {
1377 do {
1378 win = find_next_zero_bit(&phb->ioda.m64_bar_alloc,
1379 phb->ioda.m64_bar_idx + 1, 0);
1380
1381 if (win >= phb->ioda.m64_bar_idx + 1)
1382 goto m64_failed;
1383 } while (test_and_set_bit(win, &phb->ioda.m64_bar_alloc));
1384
1385 pdn->m64_map[j][i] = win;
1386
1387 if (pdn->m64_single_mode) {
1388 size = pci_iov_resource_size(pdev,
1389 PCI_IOV_RESOURCES + i);
1390 start = res->start + size * j;
1391 } else {
1392 size = resource_size(res);
1393 start = res->start;
1394 }
1395
1396
1397 if (pdn->m64_single_mode) {
1398 pe_num = pdn->pe_num_map[j];
1399 rc = opal_pci_map_pe_mmio_window(phb->opal_id,
1400 pe_num, OPAL_M64_WINDOW_TYPE,
1401 pdn->m64_map[j][i], 0);
1402 }
1403
1404 rc = opal_pci_set_phb_mem_window(phb->opal_id,
1405 OPAL_M64_WINDOW_TYPE,
1406 pdn->m64_map[j][i],
1407 start,
1408 0,
1409 size);
1410
1411
1412 if (rc != OPAL_SUCCESS) {
1413 dev_err(&pdev->dev, "Failed to map M64 window #%d: %lld\n",
1414 win, rc);
1415 goto m64_failed;
1416 }
1417
1418 if (pdn->m64_single_mode)
1419 rc = opal_pci_phb_mmio_enable(phb->opal_id,
1420 OPAL_M64_WINDOW_TYPE, pdn->m64_map[j][i], 2);
1421 else
1422 rc = opal_pci_phb_mmio_enable(phb->opal_id,
1423 OPAL_M64_WINDOW_TYPE, pdn->m64_map[j][i], 1);
1424
1425 if (rc != OPAL_SUCCESS) {
1426 dev_err(&pdev->dev, "Failed to enable M64 window #%d: %llx\n",
1427 win, rc);
1428 goto m64_failed;
1429 }
1430 }
1431 }
1432 return 0;
1433
1434 m64_failed:
1435 pnv_pci_vf_release_m64(pdev, num_vfs);
1436 return -EBUSY;
1437 }
1438
1439 static long pnv_pci_ioda2_unset_window(struct iommu_table_group *table_group,
1440 int num);
1441
1442 static void pnv_pci_ioda2_release_dma_pe(struct pci_dev *dev, struct pnv_ioda_pe *pe)
1443 {
1444 struct iommu_table *tbl;
1445 int64_t rc;
1446
1447 tbl = pe->table_group.tables[0];
1448 rc = pnv_pci_ioda2_unset_window(&pe->table_group, 0);
1449 if (rc)
1450 pe_warn(pe, "OPAL error %lld release DMA window\n", rc);
1451
1452 pnv_pci_ioda2_set_bypass(pe, false);
1453 if (pe->table_group.group) {
1454 iommu_group_put(pe->table_group.group);
1455 BUG_ON(pe->table_group.group);
1456 }
1457 iommu_tce_table_put(tbl);
1458 }
1459
1460 static void pnv_ioda_release_vf_PE(struct pci_dev *pdev)
1461 {
1462 struct pci_bus *bus;
1463 struct pci_controller *hose;
1464 struct pnv_phb *phb;
1465 struct pnv_ioda_pe *pe, *pe_n;
1466 struct pci_dn *pdn;
1467
1468 bus = pdev->bus;
1469 hose = pci_bus_to_host(bus);
1470 phb = hose->private_data;
1471 pdn = pci_get_pdn(pdev);
1472
1473 if (!pdev->is_physfn)
1474 return;
1475
1476 list_for_each_entry_safe(pe, pe_n, &phb->ioda.pe_list, list) {
1477 if (pe->parent_dev != pdev)
1478 continue;
1479
1480 pnv_pci_ioda2_release_dma_pe(pdev, pe);
1481
1482
1483 mutex_lock(&phb->ioda.pe_list_mutex);
1484 list_del(&pe->list);
1485 mutex_unlock(&phb->ioda.pe_list_mutex);
1486
1487 pnv_ioda_deconfigure_pe(phb, pe);
1488
1489 pnv_ioda_free_pe(pe);
1490 }
1491 }
1492
1493 void pnv_pci_sriov_disable(struct pci_dev *pdev)
1494 {
1495 struct pci_bus *bus;
1496 struct pci_controller *hose;
1497 struct pnv_phb *phb;
1498 struct pnv_ioda_pe *pe;
1499 struct pci_dn *pdn;
1500 u16 num_vfs, i;
1501
1502 bus = pdev->bus;
1503 hose = pci_bus_to_host(bus);
1504 phb = hose->private_data;
1505 pdn = pci_get_pdn(pdev);
1506 num_vfs = pdn->num_vfs;
1507
1508
1509 pnv_ioda_release_vf_PE(pdev);
1510
1511 if (phb->type == PNV_PHB_IODA2) {
1512 if (!pdn->m64_single_mode)
1513 pnv_pci_vf_resource_shift(pdev, -*pdn->pe_num_map);
1514
1515
1516 pnv_pci_vf_release_m64(pdev, num_vfs);
1517
1518
1519 if (pdn->m64_single_mode) {
1520 for (i = 0; i < num_vfs; i++) {
1521 if (pdn->pe_num_map[i] == IODA_INVALID_PE)
1522 continue;
1523
1524 pe = &phb->ioda.pe_array[pdn->pe_num_map[i]];
1525 pnv_ioda_free_pe(pe);
1526 }
1527 } else
1528 bitmap_clear(phb->ioda.pe_alloc, *pdn->pe_num_map, num_vfs);
1529
1530 kfree(pdn->pe_num_map);
1531 }
1532 }
1533
1534 static void pnv_pci_ioda2_setup_dma_pe(struct pnv_phb *phb,
1535 struct pnv_ioda_pe *pe);
1536 #ifdef CONFIG_IOMMU_API
1537 static void pnv_ioda_setup_bus_iommu_group(struct pnv_ioda_pe *pe,
1538 struct iommu_table_group *table_group, struct pci_bus *bus);
1539
1540 #endif
1541 static void pnv_ioda_setup_vf_PE(struct pci_dev *pdev, u16 num_vfs)
1542 {
1543 struct pci_bus *bus;
1544 struct pci_controller *hose;
1545 struct pnv_phb *phb;
1546 struct pnv_ioda_pe *pe;
1547 int pe_num;
1548 u16 vf_index;
1549 struct pci_dn *pdn;
1550
1551 bus = pdev->bus;
1552 hose = pci_bus_to_host(bus);
1553 phb = hose->private_data;
1554 pdn = pci_get_pdn(pdev);
1555
1556 if (!pdev->is_physfn)
1557 return;
1558
1559
1560 for (vf_index = 0; vf_index < num_vfs; vf_index++) {
1561 int vf_devfn = pci_iov_virtfn_devfn(pdev, vf_index);
1562 int vf_bus = pci_iov_virtfn_bus(pdev, vf_index);
1563 struct pci_dn *vf_pdn;
1564
1565 if (pdn->m64_single_mode)
1566 pe_num = pdn->pe_num_map[vf_index];
1567 else
1568 pe_num = *pdn->pe_num_map + vf_index;
1569
1570 pe = &phb->ioda.pe_array[pe_num];
1571 pe->pe_number = pe_num;
1572 pe->phb = phb;
1573 pe->flags = PNV_IODA_PE_VF;
1574 pe->pbus = NULL;
1575 pe->parent_dev = pdev;
1576 pe->mve_number = -1;
1577 pe->rid = (vf_bus << 8) | vf_devfn;
1578
1579 pe_info(pe, "VF %04d:%02d:%02d.%d associated with PE#%x\n",
1580 hose->global_number, pdev->bus->number,
1581 PCI_SLOT(vf_devfn), PCI_FUNC(vf_devfn), pe_num);
1582
1583 if (pnv_ioda_configure_pe(phb, pe)) {
1584
1585 pnv_ioda_free_pe(pe);
1586 pe->pdev = NULL;
1587 continue;
1588 }
1589
1590
1591 mutex_lock(&phb->ioda.pe_list_mutex);
1592 list_add_tail(&pe->list, &phb->ioda.pe_list);
1593 mutex_unlock(&phb->ioda.pe_list_mutex);
1594
1595
1596 list_for_each_entry(vf_pdn, &pdn->parent->child_list, list) {
1597 if (vf_pdn->busno == vf_bus &&
1598 vf_pdn->devfn == vf_devfn) {
1599 vf_pdn->pe_number = pe_num;
1600 break;
1601 }
1602 }
1603
1604 pnv_pci_ioda2_setup_dma_pe(phb, pe);
1605 #ifdef CONFIG_IOMMU_API
1606 iommu_register_group(&pe->table_group,
1607 pe->phb->hose->global_number, pe->pe_number);
1608 pnv_ioda_setup_bus_iommu_group(pe, &pe->table_group, NULL);
1609 #endif
1610 }
1611 }
1612
1613 int pnv_pci_sriov_enable(struct pci_dev *pdev, u16 num_vfs)
1614 {
1615 struct pci_bus *bus;
1616 struct pci_controller *hose;
1617 struct pnv_phb *phb;
1618 struct pnv_ioda_pe *pe;
1619 struct pci_dn *pdn;
1620 int ret;
1621 u16 i;
1622
1623 bus = pdev->bus;
1624 hose = pci_bus_to_host(bus);
1625 phb = hose->private_data;
1626 pdn = pci_get_pdn(pdev);
1627
1628 if (phb->type == PNV_PHB_IODA2) {
1629 if (!pdn->vfs_expanded) {
1630 dev_info(&pdev->dev, "don't support this SRIOV device"
1631 " with non 64bit-prefetchable IOV BAR\n");
1632 return -ENOSPC;
1633 }
1634
1635
1636
1637
1638
1639 if (pdn->m64_single_mode && num_vfs > phb->ioda.m64_bar_idx) {
1640 dev_info(&pdev->dev, "Not enough M64 BAR for VFs\n");
1641 return -EBUSY;
1642 }
1643
1644
1645 if (pdn->m64_single_mode)
1646 pdn->pe_num_map = kmalloc_array(num_vfs,
1647 sizeof(*pdn->pe_num_map),
1648 GFP_KERNEL);
1649 else
1650 pdn->pe_num_map = kmalloc(sizeof(*pdn->pe_num_map), GFP_KERNEL);
1651
1652 if (!pdn->pe_num_map)
1653 return -ENOMEM;
1654
1655 if (pdn->m64_single_mode)
1656 for (i = 0; i < num_vfs; i++)
1657 pdn->pe_num_map[i] = IODA_INVALID_PE;
1658
1659
1660 if (pdn->m64_single_mode) {
1661 for (i = 0; i < num_vfs; i++) {
1662 pe = pnv_ioda_alloc_pe(phb);
1663 if (!pe) {
1664 ret = -EBUSY;
1665 goto m64_failed;
1666 }
1667
1668 pdn->pe_num_map[i] = pe->pe_number;
1669 }
1670 } else {
1671 mutex_lock(&phb->ioda.pe_alloc_mutex);
1672 *pdn->pe_num_map = bitmap_find_next_zero_area(
1673 phb->ioda.pe_alloc, phb->ioda.total_pe_num,
1674 0, num_vfs, 0);
1675 if (*pdn->pe_num_map >= phb->ioda.total_pe_num) {
1676 mutex_unlock(&phb->ioda.pe_alloc_mutex);
1677 dev_info(&pdev->dev, "Failed to enable VF%d\n", num_vfs);
1678 kfree(pdn->pe_num_map);
1679 return -EBUSY;
1680 }
1681 bitmap_set(phb->ioda.pe_alloc, *pdn->pe_num_map, num_vfs);
1682 mutex_unlock(&phb->ioda.pe_alloc_mutex);
1683 }
1684 pdn->num_vfs = num_vfs;
1685
1686
1687 ret = pnv_pci_vf_assign_m64(pdev, num_vfs);
1688 if (ret) {
1689 dev_info(&pdev->dev, "Not enough M64 window resources\n");
1690 goto m64_failed;
1691 }
1692
1693
1694
1695
1696
1697
1698 if (!pdn->m64_single_mode) {
1699 ret = pnv_pci_vf_resource_shift(pdev, *pdn->pe_num_map);
1700 if (ret)
1701 goto m64_failed;
1702 }
1703 }
1704
1705
1706 pnv_ioda_setup_vf_PE(pdev, num_vfs);
1707
1708 return 0;
1709
1710 m64_failed:
1711 if (pdn->m64_single_mode) {
1712 for (i = 0; i < num_vfs; i++) {
1713 if (pdn->pe_num_map[i] == IODA_INVALID_PE)
1714 continue;
1715
1716 pe = &phb->ioda.pe_array[pdn->pe_num_map[i]];
1717 pnv_ioda_free_pe(pe);
1718 }
1719 } else
1720 bitmap_clear(phb->ioda.pe_alloc, *pdn->pe_num_map, num_vfs);
1721
1722
1723 kfree(pdn->pe_num_map);
1724
1725 return ret;
1726 }
1727
1728 int pnv_pcibios_sriov_disable(struct pci_dev *pdev)
1729 {
1730 pnv_pci_sriov_disable(pdev);
1731
1732
1733 remove_dev_pci_data(pdev);
1734 return 0;
1735 }
1736
1737 int pnv_pcibios_sriov_enable(struct pci_dev *pdev, u16 num_vfs)
1738 {
1739
1740 add_dev_pci_data(pdev);
1741
1742 return pnv_pci_sriov_enable(pdev, num_vfs);
1743 }
1744 #endif
1745
1746 static void pnv_pci_ioda_dma_dev_setup(struct pnv_phb *phb, struct pci_dev *pdev)
1747 {
1748 struct pci_dn *pdn = pci_get_pdn(pdev);
1749 struct pnv_ioda_pe *pe;
1750
1751
1752
1753
1754
1755
1756 if (!pdn || pdn->pe_number == IODA_INVALID_PE)
1757 return;
1758
1759 pe = &phb->ioda.pe_array[pdn->pe_number];
1760 WARN_ON(get_dma_ops(&pdev->dev) != &dma_iommu_ops);
1761 pdev->dev.archdata.dma_offset = pe->tce_bypass_base;
1762 set_iommu_table_base(&pdev->dev, pe->table_group.tables[0]);
1763
1764
1765
1766
1767
1768
1769 }
1770
1771
1772
1773
1774
1775
1776
1777
1778
1779
1780
1781
1782
1783
1784
1785
1786
1787
1788 static int pnv_pci_ioda_dma_64bit_bypass(struct pnv_ioda_pe *pe)
1789 {
1790 u64 window_size, table_size, tce_count, addr;
1791 struct page *table_pages;
1792 u64 tce_order = 28;
1793 __be64 *tces;
1794 s64 rc;
1795
1796
1797
1798
1799
1800 window_size = roundup_pow_of_two(memory_hotplug_max() + (1ULL << 32));
1801 tce_count = window_size >> tce_order;
1802 table_size = tce_count << 3;
1803
1804 if (table_size < PAGE_SIZE)
1805 table_size = PAGE_SIZE;
1806
1807 table_pages = alloc_pages_node(pe->phb->hose->node, GFP_KERNEL,
1808 get_order(table_size));
1809 if (!table_pages)
1810 goto err;
1811
1812 tces = page_address(table_pages);
1813 if (!tces)
1814 goto err;
1815
1816 memset(tces, 0, table_size);
1817
1818 for (addr = 0; addr < memory_hotplug_max(); addr += (1 << tce_order)) {
1819 tces[(addr + (1ULL << 32)) >> tce_order] =
1820 cpu_to_be64(addr | TCE_PCI_READ | TCE_PCI_WRITE);
1821 }
1822
1823 rc = opal_pci_map_pe_dma_window(pe->phb->opal_id,
1824 pe->pe_number,
1825
1826 (pe->pe_number << 1) + 0,
1827 1,
1828 __pa(tces),
1829 table_size,
1830 1 << tce_order);
1831 if (rc == OPAL_SUCCESS) {
1832 pe_info(pe, "Using 64-bit DMA iommu bypass (through TVE#0)\n");
1833 return 0;
1834 }
1835 err:
1836 pe_err(pe, "Error configuring 64-bit DMA bypass\n");
1837 return -EIO;
1838 }
1839
1840 static bool pnv_pci_ioda_iommu_bypass_supported(struct pci_dev *pdev,
1841 u64 dma_mask)
1842 {
1843 struct pci_controller *hose = pci_bus_to_host(pdev->bus);
1844 struct pnv_phb *phb = hose->private_data;
1845 struct pci_dn *pdn = pci_get_pdn(pdev);
1846 struct pnv_ioda_pe *pe;
1847
1848 if (WARN_ON(!pdn || pdn->pe_number == IODA_INVALID_PE))
1849 return false;
1850
1851 pe = &phb->ioda.pe_array[pdn->pe_number];
1852 if (pe->tce_bypass_enabled) {
1853 u64 top = pe->tce_bypass_base + memblock_end_of_DRAM() - 1;
1854 if (dma_mask >= top)
1855 return true;
1856 }
1857
1858
1859
1860
1861
1862
1863
1864 if (dma_mask >> 32 &&
1865 dma_mask > (memory_hotplug_max() + (1ULL << 32)) &&
1866
1867 (pe->device_count == 1 || !pe->pbus) &&
1868 phb->model == PNV_PHB_MODEL_PHB3) {
1869
1870 s64 rc = pnv_pci_ioda_dma_64bit_bypass(pe);
1871 if (rc)
1872 return false;
1873
1874 pdev->dev.archdata.dma_offset = (1ULL << 32);
1875 return true;
1876 }
1877
1878 return false;
1879 }
1880
1881 static void pnv_ioda_setup_bus_dma(struct pnv_ioda_pe *pe, struct pci_bus *bus)
1882 {
1883 struct pci_dev *dev;
1884
1885 list_for_each_entry(dev, &bus->devices, bus_list) {
1886 set_iommu_table_base(&dev->dev, pe->table_group.tables[0]);
1887 dev->dev.archdata.dma_offset = pe->tce_bypass_base;
1888
1889 if ((pe->flags & PNV_IODA_PE_BUS_ALL) && dev->subordinate)
1890 pnv_ioda_setup_bus_dma(pe, dev->subordinate);
1891 }
1892 }
1893
1894 static inline __be64 __iomem *pnv_ioda_get_inval_reg(struct pnv_phb *phb,
1895 bool real_mode)
1896 {
1897 return real_mode ? (__be64 __iomem *)(phb->regs_phys + 0x210) :
1898 (phb->regs + 0x210);
1899 }
1900
1901 static void pnv_pci_p7ioc_tce_invalidate(struct iommu_table *tbl,
1902 unsigned long index, unsigned long npages, bool rm)
1903 {
1904 struct iommu_table_group_link *tgl = list_first_entry_or_null(
1905 &tbl->it_group_list, struct iommu_table_group_link,
1906 next);
1907 struct pnv_ioda_pe *pe = container_of(tgl->table_group,
1908 struct pnv_ioda_pe, table_group);
1909 __be64 __iomem *invalidate = pnv_ioda_get_inval_reg(pe->phb, rm);
1910 unsigned long start, end, inc;
1911
1912 start = __pa(((__be64 *)tbl->it_base) + index - tbl->it_offset);
1913 end = __pa(((__be64 *)tbl->it_base) + index - tbl->it_offset +
1914 npages - 1);
1915
1916
1917 start |= (1ull << 63);
1918 end |= (1ull << 63);
1919 inc = 16;
1920 end |= inc - 1;
1921
1922 mb();
1923 while (start <= end) {
1924 if (rm)
1925 __raw_rm_writeq_be(start, invalidate);
1926 else
1927 __raw_writeq_be(start, invalidate);
1928
1929 start += inc;
1930 }
1931
1932
1933
1934
1935
1936 }
1937
1938 static int pnv_ioda1_tce_build(struct iommu_table *tbl, long index,
1939 long npages, unsigned long uaddr,
1940 enum dma_data_direction direction,
1941 unsigned long attrs)
1942 {
1943 int ret = pnv_tce_build(tbl, index, npages, uaddr, direction,
1944 attrs);
1945
1946 if (!ret)
1947 pnv_pci_p7ioc_tce_invalidate(tbl, index, npages, false);
1948
1949 return ret;
1950 }
1951
1952 #ifdef CONFIG_IOMMU_API
1953
1954 static int pnv_ioda_tce_xchg_no_kill(struct iommu_table *tbl, long index,
1955 unsigned long *hpa, enum dma_data_direction *direction,
1956 bool realmode)
1957 {
1958 return pnv_tce_xchg(tbl, index, hpa, direction, !realmode);
1959 }
1960 #endif
1961
1962 static void pnv_ioda1_tce_free(struct iommu_table *tbl, long index,
1963 long npages)
1964 {
1965 pnv_tce_free(tbl, index, npages);
1966
1967 pnv_pci_p7ioc_tce_invalidate(tbl, index, npages, false);
1968 }
1969
1970 static struct iommu_table_ops pnv_ioda1_iommu_ops = {
1971 .set = pnv_ioda1_tce_build,
1972 #ifdef CONFIG_IOMMU_API
1973 .xchg_no_kill = pnv_ioda_tce_xchg_no_kill,
1974 .tce_kill = pnv_pci_p7ioc_tce_invalidate,
1975 .useraddrptr = pnv_tce_useraddrptr,
1976 #endif
1977 .clear = pnv_ioda1_tce_free,
1978 .get = pnv_tce_get,
1979 };
1980
1981 #define PHB3_TCE_KILL_INVAL_ALL PPC_BIT(0)
1982 #define PHB3_TCE_KILL_INVAL_PE PPC_BIT(1)
1983 #define PHB3_TCE_KILL_INVAL_ONE PPC_BIT(2)
1984
1985 static void pnv_pci_phb3_tce_invalidate_entire(struct pnv_phb *phb, bool rm)
1986 {
1987 __be64 __iomem *invalidate = pnv_ioda_get_inval_reg(phb, rm);
1988 const unsigned long val = PHB3_TCE_KILL_INVAL_ALL;
1989
1990 mb();
1991 if (rm)
1992 __raw_rm_writeq_be(val, invalidate);
1993 else
1994 __raw_writeq_be(val, invalidate);
1995 }
1996
1997 static inline void pnv_pci_phb3_tce_invalidate_pe(struct pnv_ioda_pe *pe)
1998 {
1999
2000 __be64 __iomem *invalidate = pnv_ioda_get_inval_reg(pe->phb, false);
2001 unsigned long val = PHB3_TCE_KILL_INVAL_PE | (pe->pe_number & 0xFF);
2002
2003 mb();
2004 __raw_writeq_be(val, invalidate);
2005 }
2006
2007 static void pnv_pci_phb3_tce_invalidate(struct pnv_ioda_pe *pe, bool rm,
2008 unsigned shift, unsigned long index,
2009 unsigned long npages)
2010 {
2011 __be64 __iomem *invalidate = pnv_ioda_get_inval_reg(pe->phb, rm);
2012 unsigned long start, end, inc;
2013
2014
2015 start = PHB3_TCE_KILL_INVAL_ONE;
2016 start |= (pe->pe_number & 0xFF);
2017 end = start;
2018
2019
2020 start |= (index << shift);
2021 end |= ((index + npages - 1) << shift);
2022 inc = (0x1ull << shift);
2023 mb();
2024
2025 while (start <= end) {
2026 if (rm)
2027 __raw_rm_writeq_be(start, invalidate);
2028 else
2029 __raw_writeq_be(start, invalidate);
2030 start += inc;
2031 }
2032 }
2033
2034 static inline void pnv_pci_ioda2_tce_invalidate_pe(struct pnv_ioda_pe *pe)
2035 {
2036 struct pnv_phb *phb = pe->phb;
2037
2038 if (phb->model == PNV_PHB_MODEL_PHB3 && phb->regs)
2039 pnv_pci_phb3_tce_invalidate_pe(pe);
2040 else
2041 opal_pci_tce_kill(phb->opal_id, OPAL_PCI_TCE_KILL_PE,
2042 pe->pe_number, 0, 0, 0);
2043 }
2044
2045 static void pnv_pci_ioda2_tce_invalidate(struct iommu_table *tbl,
2046 unsigned long index, unsigned long npages, bool rm)
2047 {
2048 struct iommu_table_group_link *tgl;
2049
2050 list_for_each_entry_lockless(tgl, &tbl->it_group_list, next) {
2051 struct pnv_ioda_pe *pe = container_of(tgl->table_group,
2052 struct pnv_ioda_pe, table_group);
2053 struct pnv_phb *phb = pe->phb;
2054 unsigned int shift = tbl->it_page_shift;
2055
2056
2057
2058
2059
2060
2061 if (phb->model == PNV_PHB_MODEL_NPU) {
2062
2063
2064
2065
2066
2067 pnv_pci_phb3_tce_invalidate_entire(phb, rm);
2068 continue;
2069 }
2070 if (phb->model == PNV_PHB_MODEL_PHB3 && phb->regs)
2071 pnv_pci_phb3_tce_invalidate(pe, rm, shift,
2072 index, npages);
2073 else
2074 opal_pci_tce_kill(phb->opal_id,
2075 OPAL_PCI_TCE_KILL_PAGES,
2076 pe->pe_number, 1u << shift,
2077 index << shift, npages);
2078 }
2079 }
2080
2081 void pnv_pci_ioda2_tce_invalidate_entire(struct pnv_phb *phb, bool rm)
2082 {
2083 if (phb->model == PNV_PHB_MODEL_NPU || phb->model == PNV_PHB_MODEL_PHB3)
2084 pnv_pci_phb3_tce_invalidate_entire(phb, rm);
2085 else
2086 opal_pci_tce_kill(phb->opal_id, OPAL_PCI_TCE_KILL, 0, 0, 0, 0);
2087 }
2088
2089 static int pnv_ioda2_tce_build(struct iommu_table *tbl, long index,
2090 long npages, unsigned long uaddr,
2091 enum dma_data_direction direction,
2092 unsigned long attrs)
2093 {
2094 int ret = pnv_tce_build(tbl, index, npages, uaddr, direction,
2095 attrs);
2096
2097 if (!ret)
2098 pnv_pci_ioda2_tce_invalidate(tbl, index, npages, false);
2099
2100 return ret;
2101 }
2102
2103 static void pnv_ioda2_tce_free(struct iommu_table *tbl, long index,
2104 long npages)
2105 {
2106 pnv_tce_free(tbl, index, npages);
2107
2108 pnv_pci_ioda2_tce_invalidate(tbl, index, npages, false);
2109 }
2110
2111 static struct iommu_table_ops pnv_ioda2_iommu_ops = {
2112 .set = pnv_ioda2_tce_build,
2113 #ifdef CONFIG_IOMMU_API
2114 .xchg_no_kill = pnv_ioda_tce_xchg_no_kill,
2115 .tce_kill = pnv_pci_ioda2_tce_invalidate,
2116 .useraddrptr = pnv_tce_useraddrptr,
2117 #endif
2118 .clear = pnv_ioda2_tce_free,
2119 .get = pnv_tce_get,
2120 .free = pnv_pci_ioda2_table_free_pages,
2121 };
2122
2123 static int pnv_pci_ioda_dev_dma_weight(struct pci_dev *dev, void *data)
2124 {
2125 unsigned int *weight = (unsigned int *)data;
2126
2127
2128
2129
2130 if (dev->hdr_type != PCI_HEADER_TYPE_NORMAL)
2131 return 0;
2132
2133 if (dev->class == PCI_CLASS_SERIAL_USB_UHCI ||
2134 dev->class == PCI_CLASS_SERIAL_USB_OHCI ||
2135 dev->class == PCI_CLASS_SERIAL_USB_EHCI)
2136 *weight += 3;
2137 else if ((dev->class >> 8) == PCI_CLASS_STORAGE_RAID)
2138 *weight += 15;
2139 else
2140 *weight += 10;
2141
2142 return 0;
2143 }
2144
2145 static unsigned int pnv_pci_ioda_pe_dma_weight(struct pnv_ioda_pe *pe)
2146 {
2147 unsigned int weight = 0;
2148
2149
2150 #ifdef CONFIG_PCI_IOV
2151 if ((pe->flags & PNV_IODA_PE_VF) && pe->parent_dev) {
2152 pnv_pci_ioda_dev_dma_weight(pe->parent_dev, &weight);
2153 return weight;
2154 }
2155 #endif
2156
2157 if ((pe->flags & PNV_IODA_PE_DEV) && pe->pdev) {
2158 pnv_pci_ioda_dev_dma_weight(pe->pdev, &weight);
2159 } else if ((pe->flags & PNV_IODA_PE_BUS) && pe->pbus) {
2160 struct pci_dev *pdev;
2161
2162 list_for_each_entry(pdev, &pe->pbus->devices, bus_list)
2163 pnv_pci_ioda_dev_dma_weight(pdev, &weight);
2164 } else if ((pe->flags & PNV_IODA_PE_BUS_ALL) && pe->pbus) {
2165 pci_walk_bus(pe->pbus, pnv_pci_ioda_dev_dma_weight, &weight);
2166 }
2167
2168 return weight;
2169 }
2170
2171 static void pnv_pci_ioda1_setup_dma_pe(struct pnv_phb *phb,
2172 struct pnv_ioda_pe *pe)
2173 {
2174
2175 struct page *tce_mem = NULL;
2176 struct iommu_table *tbl;
2177 unsigned int weight, total_weight = 0;
2178 unsigned int tce32_segsz, base, segs, avail, i;
2179 int64_t rc;
2180 void *addr;
2181
2182
2183
2184
2185 weight = pnv_pci_ioda_pe_dma_weight(pe);
2186 if (!weight)
2187 return;
2188
2189 pci_walk_bus(phb->hose->bus, pnv_pci_ioda_dev_dma_weight,
2190 &total_weight);
2191 segs = (weight * phb->ioda.dma32_count) / total_weight;
2192 if (!segs)
2193 segs = 1;
2194
2195
2196
2197
2198
2199
2200
2201 do {
2202 for (base = 0; base <= phb->ioda.dma32_count - segs; base++) {
2203 for (avail = 0, i = base; i < base + segs; i++) {
2204 if (phb->ioda.dma32_segmap[i] ==
2205 IODA_INVALID_PE)
2206 avail++;
2207 }
2208
2209 if (avail == segs)
2210 goto found;
2211 }
2212 } while (--segs);
2213
2214 if (!segs) {
2215 pe_warn(pe, "No available DMA32 segments\n");
2216 return;
2217 }
2218
2219 found:
2220 tbl = pnv_pci_table_alloc(phb->hose->node);
2221 if (WARN_ON(!tbl))
2222 return;
2223
2224 iommu_register_group(&pe->table_group, phb->hose->global_number,
2225 pe->pe_number);
2226 pnv_pci_link_table_and_group(phb->hose->node, 0, tbl, &pe->table_group);
2227
2228
2229 pe_info(pe, "DMA weight %d (%d), assigned (%d) %d DMA32 segments\n",
2230 weight, total_weight, base, segs);
2231 pe_info(pe, " Setting up 32-bit TCE table at %08x..%08x\n",
2232 base * PNV_IODA1_DMA32_SEGSIZE,
2233 (base + segs) * PNV_IODA1_DMA32_SEGSIZE - 1);
2234
2235
2236
2237
2238
2239
2240
2241
2242
2243 tce32_segsz = PNV_IODA1_DMA32_SEGSIZE >> (IOMMU_PAGE_SHIFT_4K - 3);
2244 tce_mem = alloc_pages_node(phb->hose->node, GFP_KERNEL,
2245 get_order(tce32_segsz * segs));
2246 if (!tce_mem) {
2247 pe_err(pe, " Failed to allocate a 32-bit TCE memory\n");
2248 goto fail;
2249 }
2250 addr = page_address(tce_mem);
2251 memset(addr, 0, tce32_segsz * segs);
2252
2253
2254 for (i = 0; i < segs; i++) {
2255 rc = opal_pci_map_pe_dma_window(phb->opal_id,
2256 pe->pe_number,
2257 base + i, 1,
2258 __pa(addr) + tce32_segsz * i,
2259 tce32_segsz, IOMMU_PAGE_SIZE_4K);
2260 if (rc) {
2261 pe_err(pe, " Failed to configure 32-bit TCE table, err %lld\n",
2262 rc);
2263 goto fail;
2264 }
2265 }
2266
2267
2268 for (i = base; i < base + segs; i++)
2269 phb->ioda.dma32_segmap[i] = pe->pe_number;
2270
2271
2272 pnv_pci_setup_iommu_table(tbl, addr, tce32_segsz * segs,
2273 base * PNV_IODA1_DMA32_SEGSIZE,
2274 IOMMU_PAGE_SHIFT_4K);
2275
2276 tbl->it_ops = &pnv_ioda1_iommu_ops;
2277 pe->table_group.tce32_start = tbl->it_offset << tbl->it_page_shift;
2278 pe->table_group.tce32_size = tbl->it_size << tbl->it_page_shift;
2279 iommu_init_table(tbl, phb->hose->node, 0, 0);
2280
2281 if (pe->flags & (PNV_IODA_PE_BUS | PNV_IODA_PE_BUS_ALL))
2282 pnv_ioda_setup_bus_dma(pe, pe->pbus);
2283
2284 return;
2285 fail:
2286
2287 if (tce_mem)
2288 __free_pages(tce_mem, get_order(tce32_segsz * segs));
2289 if (tbl) {
2290 pnv_pci_unlink_table_and_group(tbl, &pe->table_group);
2291 iommu_tce_table_put(tbl);
2292 }
2293 }
2294
2295 static long pnv_pci_ioda2_set_window(struct iommu_table_group *table_group,
2296 int num, struct iommu_table *tbl)
2297 {
2298 struct pnv_ioda_pe *pe = container_of(table_group, struct pnv_ioda_pe,
2299 table_group);
2300 struct pnv_phb *phb = pe->phb;
2301 int64_t rc;
2302 const unsigned long size = tbl->it_indirect_levels ?
2303 tbl->it_level_size : tbl->it_size;
2304 const __u64 start_addr = tbl->it_offset << tbl->it_page_shift;
2305 const __u64 win_size = tbl->it_size << tbl->it_page_shift;
2306
2307 pe_info(pe, "Setting up window#%d %llx..%llx pg=%lx\n",
2308 num, start_addr, start_addr + win_size - 1,
2309 IOMMU_PAGE_SIZE(tbl));
2310
2311
2312
2313
2314
2315 rc = opal_pci_map_pe_dma_window(phb->opal_id,
2316 pe->pe_number,
2317 (pe->pe_number << 1) + num,
2318 tbl->it_indirect_levels + 1,
2319 __pa(tbl->it_base),
2320 size << 3,
2321 IOMMU_PAGE_SIZE(tbl));
2322 if (rc) {
2323 pe_err(pe, "Failed to configure TCE table, err %lld\n", rc);
2324 return rc;
2325 }
2326
2327 pnv_pci_link_table_and_group(phb->hose->node, num,
2328 tbl, &pe->table_group);
2329 pnv_pci_ioda2_tce_invalidate_pe(pe);
2330
2331 return 0;
2332 }
2333
2334 static void pnv_pci_ioda2_set_bypass(struct pnv_ioda_pe *pe, bool enable)
2335 {
2336 uint16_t window_id = (pe->pe_number << 1 ) + 1;
2337 int64_t rc;
2338
2339 pe_info(pe, "%sabling 64-bit DMA bypass\n", enable ? "En" : "Dis");
2340 if (enable) {
2341 phys_addr_t top = memblock_end_of_DRAM();
2342
2343 top = roundup_pow_of_two(top);
2344 rc = opal_pci_map_pe_dma_window_real(pe->phb->opal_id,
2345 pe->pe_number,
2346 window_id,
2347 pe->tce_bypass_base,
2348 top);
2349 } else {
2350 rc = opal_pci_map_pe_dma_window_real(pe->phb->opal_id,
2351 pe->pe_number,
2352 window_id,
2353 pe->tce_bypass_base,
2354 0);
2355 }
2356 if (rc)
2357 pe_err(pe, "OPAL error %lld configuring bypass window\n", rc);
2358 else
2359 pe->tce_bypass_enabled = enable;
2360 }
2361
2362 static long pnv_pci_ioda2_create_table(struct iommu_table_group *table_group,
2363 int num, __u32 page_shift, __u64 window_size, __u32 levels,
2364 bool alloc_userspace_copy, struct iommu_table **ptbl)
2365 {
2366 struct pnv_ioda_pe *pe = container_of(table_group, struct pnv_ioda_pe,
2367 table_group);
2368 int nid = pe->phb->hose->node;
2369 __u64 bus_offset = num ? pe->tce_bypass_base : table_group->tce32_start;
2370 long ret;
2371 struct iommu_table *tbl;
2372
2373 tbl = pnv_pci_table_alloc(nid);
2374 if (!tbl)
2375 return -ENOMEM;
2376
2377 tbl->it_ops = &pnv_ioda2_iommu_ops;
2378
2379 ret = pnv_pci_ioda2_table_alloc_pages(nid,
2380 bus_offset, page_shift, window_size,
2381 levels, alloc_userspace_copy, tbl);
2382 if (ret) {
2383 iommu_tce_table_put(tbl);
2384 return ret;
2385 }
2386
2387 *ptbl = tbl;
2388
2389 return 0;
2390 }
2391
2392 static long pnv_pci_ioda2_setup_default_config(struct pnv_ioda_pe *pe)
2393 {
2394 struct iommu_table *tbl = NULL;
2395 long rc;
2396 unsigned long res_start, res_end;
2397
2398
2399
2400
2401
2402
2403 const u64 max_memory = __rounddown_pow_of_two(memory_hotplug_max());
2404
2405
2406
2407
2408
2409
2410 const u64 maxblock = 1UL << (PAGE_SHIFT + MAX_ORDER - 1);
2411
2412
2413
2414
2415
2416
2417
2418
2419
2420 const u64 window_size = min((maxblock * 8) << PAGE_SHIFT, max_memory);
2421
2422 unsigned long tces_order = ilog2(window_size >> PAGE_SHIFT);
2423 unsigned long tcelevel_order = ilog2(maxblock >> 3);
2424 unsigned int levels = tces_order / tcelevel_order;
2425
2426 if (tces_order % tcelevel_order)
2427 levels += 1;
2428
2429
2430
2431
2432 levels = max_t(unsigned int, levels, POWERNV_IOMMU_DEFAULT_LEVELS);
2433
2434 rc = pnv_pci_ioda2_create_table(&pe->table_group, 0, PAGE_SHIFT,
2435 window_size, levels, false, &tbl);
2436 if (rc) {
2437 pe_err(pe, "Failed to create 32-bit TCE table, err %ld",
2438 rc);
2439 return rc;
2440 }
2441
2442
2443 res_start = 0;
2444 res_end = 0;
2445 if (window_size > pe->phb->ioda.m32_pci_base) {
2446 res_start = pe->phb->ioda.m32_pci_base >> tbl->it_page_shift;
2447 res_end = min(window_size, SZ_4G) >> tbl->it_page_shift;
2448 }
2449 iommu_init_table(tbl, pe->phb->hose->node, res_start, res_end);
2450
2451 rc = pnv_pci_ioda2_set_window(&pe->table_group, 0, tbl);
2452 if (rc) {
2453 pe_err(pe, "Failed to configure 32-bit TCE table, err %ld\n",
2454 rc);
2455 iommu_tce_table_put(tbl);
2456 return rc;
2457 }
2458
2459 if (!pnv_iommu_bypass_disabled)
2460 pnv_pci_ioda2_set_bypass(pe, true);
2461
2462
2463
2464
2465
2466
2467 if (pe->pdev)
2468 set_iommu_table_base(&pe->pdev->dev, tbl);
2469
2470 return 0;
2471 }
2472
2473 #if defined(CONFIG_IOMMU_API) || defined(CONFIG_PCI_IOV)
2474 static long pnv_pci_ioda2_unset_window(struct iommu_table_group *table_group,
2475 int num)
2476 {
2477 struct pnv_ioda_pe *pe = container_of(table_group, struct pnv_ioda_pe,
2478 table_group);
2479 struct pnv_phb *phb = pe->phb;
2480 long ret;
2481
2482 pe_info(pe, "Removing DMA window #%d\n", num);
2483
2484 ret = opal_pci_map_pe_dma_window(phb->opal_id, pe->pe_number,
2485 (pe->pe_number << 1) + num,
2486 0, 0,
2487 0, 0);
2488 if (ret)
2489 pe_warn(pe, "Unmapping failed, ret = %ld\n", ret);
2490 else
2491 pnv_pci_ioda2_tce_invalidate_pe(pe);
2492
2493 pnv_pci_unlink_table_and_group(table_group->tables[num], table_group);
2494
2495 return ret;
2496 }
2497 #endif
2498
2499 #ifdef CONFIG_IOMMU_API
2500 unsigned long pnv_pci_ioda2_get_table_size(__u32 page_shift,
2501 __u64 window_size, __u32 levels)
2502 {
2503 unsigned long bytes = 0;
2504 const unsigned window_shift = ilog2(window_size);
2505 unsigned entries_shift = window_shift - page_shift;
2506 unsigned table_shift = entries_shift + 3;
2507 unsigned long tce_table_size = max(0x1000UL, 1UL << table_shift);
2508 unsigned long direct_table_size;
2509
2510 if (!levels || (levels > POWERNV_IOMMU_MAX_LEVELS) ||
2511 !is_power_of_2(window_size))
2512 return 0;
2513
2514
2515 entries_shift = (entries_shift + levels - 1) / levels;
2516 table_shift = entries_shift + 3;
2517 table_shift = max_t(unsigned, table_shift, PAGE_SHIFT);
2518 direct_table_size = 1UL << table_shift;
2519
2520 for ( ; levels; --levels) {
2521 bytes += _ALIGN_UP(tce_table_size, direct_table_size);
2522
2523 tce_table_size /= direct_table_size;
2524 tce_table_size <<= 3;
2525 tce_table_size = max_t(unsigned long,
2526 tce_table_size, direct_table_size);
2527 }
2528
2529 return bytes + bytes;
2530 }
2531
2532 static long pnv_pci_ioda2_create_table_userspace(
2533 struct iommu_table_group *table_group,
2534 int num, __u32 page_shift, __u64 window_size, __u32 levels,
2535 struct iommu_table **ptbl)
2536 {
2537 long ret = pnv_pci_ioda2_create_table(table_group,
2538 num, page_shift, window_size, levels, true, ptbl);
2539
2540 if (!ret)
2541 (*ptbl)->it_allocated_size = pnv_pci_ioda2_get_table_size(
2542 page_shift, window_size, levels);
2543 return ret;
2544 }
2545
2546 static void pnv_ioda2_take_ownership(struct iommu_table_group *table_group)
2547 {
2548 struct pnv_ioda_pe *pe = container_of(table_group, struct pnv_ioda_pe,
2549 table_group);
2550
2551 struct iommu_table *tbl = pe->table_group.tables[0];
2552
2553 pnv_pci_ioda2_set_bypass(pe, false);
2554 pnv_pci_ioda2_unset_window(&pe->table_group, 0);
2555 if (pe->pbus)
2556 pnv_ioda_setup_bus_dma(pe, pe->pbus);
2557 else if (pe->pdev)
2558 set_iommu_table_base(&pe->pdev->dev, NULL);
2559 iommu_tce_table_put(tbl);
2560 }
2561
2562 static void pnv_ioda2_release_ownership(struct iommu_table_group *table_group)
2563 {
2564 struct pnv_ioda_pe *pe = container_of(table_group, struct pnv_ioda_pe,
2565 table_group);
2566
2567 pnv_pci_ioda2_setup_default_config(pe);
2568 if (pe->pbus)
2569 pnv_ioda_setup_bus_dma(pe, pe->pbus);
2570 }
2571
2572 static struct iommu_table_group_ops pnv_pci_ioda2_ops = {
2573 .get_table_size = pnv_pci_ioda2_get_table_size,
2574 .create_table = pnv_pci_ioda2_create_table_userspace,
2575 .set_window = pnv_pci_ioda2_set_window,
2576 .unset_window = pnv_pci_ioda2_unset_window,
2577 .take_ownership = pnv_ioda2_take_ownership,
2578 .release_ownership = pnv_ioda2_release_ownership,
2579 };
2580
2581 static void pnv_ioda_setup_bus_iommu_group_add_devices(struct pnv_ioda_pe *pe,
2582 struct iommu_table_group *table_group,
2583 struct pci_bus *bus)
2584 {
2585 struct pci_dev *dev;
2586
2587 list_for_each_entry(dev, &bus->devices, bus_list) {
2588 iommu_add_device(table_group, &dev->dev);
2589
2590 if ((pe->flags & PNV_IODA_PE_BUS_ALL) && dev->subordinate)
2591 pnv_ioda_setup_bus_iommu_group_add_devices(pe,
2592 table_group, dev->subordinate);
2593 }
2594 }
2595
2596 static void pnv_ioda_setup_bus_iommu_group(struct pnv_ioda_pe *pe,
2597 struct iommu_table_group *table_group, struct pci_bus *bus)
2598 {
2599
2600 if (pe->flags & PNV_IODA_PE_DEV)
2601 iommu_add_device(table_group, &pe->pdev->dev);
2602
2603 if ((pe->flags & (PNV_IODA_PE_BUS | PNV_IODA_PE_BUS_ALL)) || bus)
2604 pnv_ioda_setup_bus_iommu_group_add_devices(pe, table_group,
2605 bus);
2606 }
2607
2608 static unsigned long pnv_ioda_parse_tce_sizes(struct pnv_phb *phb);
2609
2610 static void pnv_pci_ioda_setup_iommu_api(void)
2611 {
2612 struct pci_controller *hose;
2613 struct pnv_phb *phb;
2614 struct pnv_ioda_pe *pe;
2615
2616
2617
2618
2619
2620
2621
2622
2623
2624
2625
2626
2627
2628
2629
2630 list_for_each_entry(hose, &hose_list, list_node) {
2631 phb = hose->private_data;
2632
2633 if (phb->type == PNV_PHB_NPU_NVLINK ||
2634 phb->type == PNV_PHB_NPU_OCAPI)
2635 continue;
2636
2637 list_for_each_entry(pe, &phb->ioda.pe_list, list) {
2638 struct iommu_table_group *table_group;
2639
2640 table_group = pnv_try_setup_npu_table_group(pe);
2641 if (!table_group) {
2642 if (!pnv_pci_ioda_pe_dma_weight(pe))
2643 continue;
2644
2645 table_group = &pe->table_group;
2646 iommu_register_group(&pe->table_group,
2647 pe->phb->hose->global_number,
2648 pe->pe_number);
2649 }
2650 pnv_ioda_setup_bus_iommu_group(pe, table_group,
2651 pe->pbus);
2652 }
2653 }
2654
2655
2656
2657
2658
2659 list_for_each_entry(hose, &hose_list, list_node) {
2660 unsigned long pgsizes;
2661
2662 phb = hose->private_data;
2663
2664 if (phb->type != PNV_PHB_NPU_NVLINK)
2665 continue;
2666
2667 pgsizes = pnv_ioda_parse_tce_sizes(phb);
2668 list_for_each_entry(pe, &phb->ioda.pe_list, list) {
2669
2670
2671
2672
2673
2674 pe->table_group.pgsizes = pgsizes;
2675 pnv_npu_compound_attach(pe);
2676 }
2677 }
2678 }
2679 #else
2680 static void pnv_pci_ioda_setup_iommu_api(void) { };
2681 #endif
2682
2683 static unsigned long pnv_ioda_parse_tce_sizes(struct pnv_phb *phb)
2684 {
2685 struct pci_controller *hose = phb->hose;
2686 struct device_node *dn = hose->dn;
2687 unsigned long mask = 0;
2688 int i, rc, count;
2689 u32 val;
2690
2691 count = of_property_count_u32_elems(dn, "ibm,supported-tce-sizes");
2692 if (count <= 0) {
2693 mask = SZ_4K | SZ_64K;
2694
2695 if (cpu_has_feature(CPU_FTR_ARCH_207S) &&
2696 !cpu_has_feature(CPU_FTR_ARCH_300))
2697 mask |= SZ_16M | SZ_256M;
2698 return mask;
2699 }
2700
2701 for (i = 0; i < count; i++) {
2702 rc = of_property_read_u32_index(dn, "ibm,supported-tce-sizes",
2703 i, &val);
2704 if (rc == 0)
2705 mask |= 1ULL << val;
2706 }
2707
2708 return mask;
2709 }
2710
2711 static void pnv_pci_ioda2_setup_dma_pe(struct pnv_phb *phb,
2712 struct pnv_ioda_pe *pe)
2713 {
2714 int64_t rc;
2715
2716 if (!pnv_pci_ioda_pe_dma_weight(pe))
2717 return;
2718
2719
2720 pe->tce_bypass_base = 1ull << 59;
2721
2722
2723 pe_info(pe, "Setting up 32-bit TCE table at 0..%08x\n",
2724 phb->ioda.m32_pci_base);
2725
2726
2727 pe->table_group.tce32_start = 0;
2728 pe->table_group.tce32_size = phb->ioda.m32_pci_base;
2729 pe->table_group.max_dynamic_windows_supported =
2730 IOMMU_TABLE_GROUP_MAX_TABLES;
2731 pe->table_group.max_levels = POWERNV_IOMMU_MAX_LEVELS;
2732 pe->table_group.pgsizes = pnv_ioda_parse_tce_sizes(phb);
2733 #ifdef CONFIG_IOMMU_API
2734 pe->table_group.ops = &pnv_pci_ioda2_ops;
2735 #endif
2736
2737 rc = pnv_pci_ioda2_setup_default_config(pe);
2738 if (rc)
2739 return;
2740
2741 if (pe->flags & (PNV_IODA_PE_BUS | PNV_IODA_PE_BUS_ALL))
2742 pnv_ioda_setup_bus_dma(pe, pe->pbus);
2743 }
2744
2745 int64_t pnv_opal_pci_msi_eoi(struct irq_chip *chip, unsigned int hw_irq)
2746 {
2747 struct pnv_phb *phb = container_of(chip, struct pnv_phb,
2748 ioda.irq_chip);
2749
2750 return opal_pci_msi_eoi(phb->opal_id, hw_irq);
2751 }
2752
2753 static void pnv_ioda2_msi_eoi(struct irq_data *d)
2754 {
2755 int64_t rc;
2756 unsigned int hw_irq = (unsigned int)irqd_to_hwirq(d);
2757 struct irq_chip *chip = irq_data_get_irq_chip(d);
2758
2759 rc = pnv_opal_pci_msi_eoi(chip, hw_irq);
2760 WARN_ON_ONCE(rc);
2761
2762 icp_native_eoi(d);
2763 }
2764
2765
2766 void pnv_set_msi_irq_chip(struct pnv_phb *phb, unsigned int virq)
2767 {
2768 struct irq_data *idata;
2769 struct irq_chip *ichip;
2770
2771
2772 if (phb->model != PNV_PHB_MODEL_PHB3)
2773 return;
2774
2775 if (!phb->ioda.irq_chip_init) {
2776
2777
2778
2779
2780 idata = irq_get_irq_data(virq);
2781 ichip = irq_data_get_irq_chip(idata);
2782 phb->ioda.irq_chip_init = 1;
2783 phb->ioda.irq_chip = *ichip;
2784 phb->ioda.irq_chip.irq_eoi = pnv_ioda2_msi_eoi;
2785 }
2786 irq_set_chip(virq, &phb->ioda.irq_chip);
2787 }
2788
2789
2790
2791
2792
2793 bool is_pnv_opal_msi(struct irq_chip *chip)
2794 {
2795 return chip->irq_eoi == pnv_ioda2_msi_eoi;
2796 }
2797 EXPORT_SYMBOL_GPL(is_pnv_opal_msi);
2798
2799 static int pnv_pci_ioda_msi_setup(struct pnv_phb *phb, struct pci_dev *dev,
2800 unsigned int hwirq, unsigned int virq,
2801 unsigned int is_64, struct msi_msg *msg)
2802 {
2803 struct pnv_ioda_pe *pe = pnv_ioda_get_pe(dev);
2804 unsigned int xive_num = hwirq - phb->msi_base;
2805 __be32 data;
2806 int rc;
2807
2808
2809 if (pe == NULL)
2810 return -ENXIO;
2811
2812
2813 if (pe->mve_number < 0)
2814 return -ENXIO;
2815
2816
2817 if (dev->no_64bit_msi)
2818 is_64 = 0;
2819
2820
2821 rc = opal_pci_set_xive_pe(phb->opal_id, pe->pe_number, xive_num);
2822 if (rc) {
2823 pr_warn("%s: OPAL error %d setting XIVE %d PE\n",
2824 pci_name(dev), rc, xive_num);
2825 return -EIO;
2826 }
2827
2828 if (is_64) {
2829 __be64 addr64;
2830
2831 rc = opal_get_msi_64(phb->opal_id, pe->mve_number, xive_num, 1,
2832 &addr64, &data);
2833 if (rc) {
2834 pr_warn("%s: OPAL error %d getting 64-bit MSI data\n",
2835 pci_name(dev), rc);
2836 return -EIO;
2837 }
2838 msg->address_hi = be64_to_cpu(addr64) >> 32;
2839 msg->address_lo = be64_to_cpu(addr64) & 0xfffffffful;
2840 } else {
2841 __be32 addr32;
2842
2843 rc = opal_get_msi_32(phb->opal_id, pe->mve_number, xive_num, 1,
2844 &addr32, &data);
2845 if (rc) {
2846 pr_warn("%s: OPAL error %d getting 32-bit MSI data\n",
2847 pci_name(dev), rc);
2848 return -EIO;
2849 }
2850 msg->address_hi = 0;
2851 msg->address_lo = be32_to_cpu(addr32);
2852 }
2853 msg->data = be32_to_cpu(data);
2854
2855 pnv_set_msi_irq_chip(phb, virq);
2856
2857 pr_devel("%s: %s-bit MSI on hwirq %x (xive #%d),"
2858 " address=%x_%08x data=%x PE# %x\n",
2859 pci_name(dev), is_64 ? "64" : "32", hwirq, xive_num,
2860 msg->address_hi, msg->address_lo, data, pe->pe_number);
2861
2862 return 0;
2863 }
2864
2865 static void pnv_pci_init_ioda_msis(struct pnv_phb *phb)
2866 {
2867 unsigned int count;
2868 const __be32 *prop = of_get_property(phb->hose->dn,
2869 "ibm,opal-msi-ranges", NULL);
2870 if (!prop) {
2871
2872 prop = of_get_property(phb->hose->dn, "msi-ranges", NULL);
2873 }
2874 if (!prop)
2875 return;
2876
2877 phb->msi_base = be32_to_cpup(prop);
2878 count = be32_to_cpup(prop + 1);
2879 if (msi_bitmap_alloc(&phb->msi_bmp, count, phb->hose->dn)) {
2880 pr_err("PCI %d: Failed to allocate MSI bitmap !\n",
2881 phb->hose->global_number);
2882 return;
2883 }
2884
2885 phb->msi_setup = pnv_pci_ioda_msi_setup;
2886 phb->msi32_support = 1;
2887 pr_info(" Allocated bitmap for %d MSIs (base IRQ 0x%x)\n",
2888 count, phb->msi_base);
2889 }
2890
2891 #ifdef CONFIG_PCI_IOV
2892 static void pnv_pci_ioda_fixup_iov_resources(struct pci_dev *pdev)
2893 {
2894 struct pci_controller *hose = pci_bus_to_host(pdev->bus);
2895 struct pnv_phb *phb = hose->private_data;
2896 const resource_size_t gate = phb->ioda.m64_segsize >> 2;
2897 struct resource *res;
2898 int i;
2899 resource_size_t size, total_vf_bar_sz;
2900 struct pci_dn *pdn;
2901 int mul, total_vfs;
2902
2903 pdn = pci_get_pdn(pdev);
2904 pdn->vfs_expanded = 0;
2905 pdn->m64_single_mode = false;
2906
2907 total_vfs = pci_sriov_get_totalvfs(pdev);
2908 mul = phb->ioda.total_pe_num;
2909 total_vf_bar_sz = 0;
2910
2911 for (i = 0; i < PCI_SRIOV_NUM_BARS; i++) {
2912 res = &pdev->resource[i + PCI_IOV_RESOURCES];
2913 if (!res->flags || res->parent)
2914 continue;
2915 if (!pnv_pci_is_m64_flags(res->flags)) {
2916 dev_warn(&pdev->dev, "Don't support SR-IOV with"
2917 " non M64 VF BAR%d: %pR. \n",
2918 i, res);
2919 goto truncate_iov;
2920 }
2921
2922 total_vf_bar_sz += pci_iov_resource_size(pdev,
2923 i + PCI_IOV_RESOURCES);
2924
2925
2926
2927
2928
2929
2930
2931
2932
2933
2934
2935
2936
2937 if (total_vf_bar_sz > gate) {
2938 mul = roundup_pow_of_two(total_vfs);
2939 dev_info(&pdev->dev,
2940 "VF BAR Total IOV size %llx > %llx, roundup to %d VFs\n",
2941 total_vf_bar_sz, gate, mul);
2942 pdn->m64_single_mode = true;
2943 break;
2944 }
2945 }
2946
2947 for (i = 0; i < PCI_SRIOV_NUM_BARS; i++) {
2948 res = &pdev->resource[i + PCI_IOV_RESOURCES];
2949 if (!res->flags || res->parent)
2950 continue;
2951
2952 size = pci_iov_resource_size(pdev, i + PCI_IOV_RESOURCES);
2953
2954
2955
2956
2957 if (pdn->m64_single_mode && (size < SZ_32M))
2958 goto truncate_iov;
2959 dev_dbg(&pdev->dev, " Fixing VF BAR%d: %pR to\n", i, res);
2960 res->end = res->start + size * mul - 1;
2961 dev_dbg(&pdev->dev, " %pR\n", res);
2962 dev_info(&pdev->dev, "VF BAR%d: %pR (expanded to %d VFs for PE alignment)",
2963 i, res, mul);
2964 }
2965 pdn->vfs_expanded = mul;
2966
2967 return;
2968
2969 truncate_iov:
2970
2971 for (i = 0; i < PCI_SRIOV_NUM_BARS; i++) {
2972 res = &pdev->resource[i + PCI_IOV_RESOURCES];
2973 res->flags = 0;
2974 res->end = res->start - 1;
2975 }
2976 }
2977
2978 static void pnv_pci_ioda_fixup_iov(struct pci_dev *pdev)
2979 {
2980 if (WARN_ON(pci_dev_is_added(pdev)))
2981 return;
2982
2983 if (pdev->is_virtfn) {
2984 struct pnv_ioda_pe *pe = pnv_ioda_get_pe(pdev);
2985
2986
2987
2988
2989
2990
2991 pe->pdev = pdev;
2992 WARN_ON(!(pe->flags & PNV_IODA_PE_VF));
2993 } else if (pdev->is_physfn) {
2994
2995
2996
2997
2998 pnv_pci_ioda_fixup_iov_resources(pdev);
2999 }
3000 }
3001 #endif
3002
3003 static void pnv_ioda_setup_pe_res(struct pnv_ioda_pe *pe,
3004 struct resource *res)
3005 {
3006 struct pnv_phb *phb = pe->phb;
3007 struct pci_bus_region region;
3008 int index;
3009 int64_t rc;
3010
3011 if (!res || !res->flags || res->start > res->end)
3012 return;
3013
3014 if (res->flags & IORESOURCE_IO) {
3015 region.start = res->start - phb->ioda.io_pci_base;
3016 region.end = res->end - phb->ioda.io_pci_base;
3017 index = region.start / phb->ioda.io_segsize;
3018
3019 while (index < phb->ioda.total_pe_num &&
3020 region.start <= region.end) {
3021 phb->ioda.io_segmap[index] = pe->pe_number;
3022 rc = opal_pci_map_pe_mmio_window(phb->opal_id,
3023 pe->pe_number, OPAL_IO_WINDOW_TYPE, 0, index);
3024 if (rc != OPAL_SUCCESS) {
3025 pr_err("%s: Error %lld mapping IO segment#%d to PE#%x\n",
3026 __func__, rc, index, pe->pe_number);
3027 break;
3028 }
3029
3030 region.start += phb->ioda.io_segsize;
3031 index++;
3032 }
3033 } else if ((res->flags & IORESOURCE_MEM) &&
3034 !pnv_pci_is_m64(phb, res)) {
3035 region.start = res->start -
3036 phb->hose->mem_offset[0] -
3037 phb->ioda.m32_pci_base;
3038 region.end = res->end -
3039 phb->hose->mem_offset[0] -
3040 phb->ioda.m32_pci_base;
3041 index = region.start / phb->ioda.m32_segsize;
3042
3043 while (index < phb->ioda.total_pe_num &&
3044 region.start <= region.end) {
3045 phb->ioda.m32_segmap[index] = pe->pe_number;
3046 rc = opal_pci_map_pe_mmio_window(phb->opal_id,
3047 pe->pe_number, OPAL_M32_WINDOW_TYPE, 0, index);
3048 if (rc != OPAL_SUCCESS) {
3049 pr_err("%s: Error %lld mapping M32 segment#%d to PE#%x",
3050 __func__, rc, index, pe->pe_number);
3051 break;
3052 }
3053
3054 region.start += phb->ioda.m32_segsize;
3055 index++;
3056 }
3057 }
3058 }
3059
3060
3061
3062
3063
3064
3065 static void pnv_ioda_setup_pe_seg(struct pnv_ioda_pe *pe)
3066 {
3067 struct pci_dev *pdev;
3068 int i;
3069
3070
3071
3072
3073
3074
3075 BUG_ON(!(pe->flags & (PNV_IODA_PE_BUS | PNV_IODA_PE_BUS_ALL)));
3076
3077 list_for_each_entry(pdev, &pe->pbus->devices, bus_list) {
3078 for (i = 0; i <= PCI_ROM_RESOURCE; i++)
3079 pnv_ioda_setup_pe_res(pe, &pdev->resource[i]);
3080
3081
3082
3083
3084
3085
3086 if (!(pe->flags & PNV_IODA_PE_BUS_ALL) || !pci_is_bridge(pdev))
3087 continue;
3088 for (i = 0; i < PCI_BRIDGE_RESOURCE_NUM; i++)
3089 pnv_ioda_setup_pe_res(pe,
3090 &pdev->resource[PCI_BRIDGE_RESOURCES + i]);
3091 }
3092 }
3093
3094 #ifdef CONFIG_DEBUG_FS
3095 static int pnv_pci_diag_data_set(void *data, u64 val)
3096 {
3097 struct pci_controller *hose;
3098 struct pnv_phb *phb;
3099 s64 ret;
3100
3101 if (val != 1ULL)
3102 return -EINVAL;
3103
3104 hose = (struct pci_controller *)data;
3105 if (!hose || !hose->private_data)
3106 return -ENODEV;
3107
3108 phb = hose->private_data;
3109
3110
3111 ret = opal_pci_get_phb_diag_data2(phb->opal_id, phb->diag_data,
3112 phb->diag_data_size);
3113 if (ret != OPAL_SUCCESS)
3114 return -EIO;
3115
3116
3117 pnv_pci_dump_phb_diag_data(phb->hose, phb->diag_data);
3118 return 0;
3119 }
3120
3121 DEFINE_SIMPLE_ATTRIBUTE(pnv_pci_diag_data_fops, NULL,
3122 pnv_pci_diag_data_set, "%llu\n");
3123
3124 #endif
3125
3126 static void pnv_pci_ioda_create_dbgfs(void)
3127 {
3128 #ifdef CONFIG_DEBUG_FS
3129 struct pci_controller *hose, *tmp;
3130 struct pnv_phb *phb;
3131 char name[16];
3132
3133 list_for_each_entry_safe(hose, tmp, &hose_list, list_node) {
3134 phb = hose->private_data;
3135
3136
3137 phb->initialized = 1;
3138
3139 sprintf(name, "PCI%04x", hose->global_number);
3140 phb->dbgfs = debugfs_create_dir(name, powerpc_debugfs_root);
3141 if (!phb->dbgfs) {
3142 pr_warn("%s: Error on creating debugfs on PHB#%x\n",
3143 __func__, hose->global_number);
3144 continue;
3145 }
3146
3147 debugfs_create_file("dump_diag_regs", 0200, phb->dbgfs, hose,
3148 &pnv_pci_diag_data_fops);
3149 }
3150 #endif
3151 }
3152
3153 static void pnv_pci_enable_bridge(struct pci_bus *bus)
3154 {
3155 struct pci_dev *dev = bus->self;
3156 struct pci_bus *child;
3157
3158
3159 if (list_empty(&bus->devices))
3160 return;
3161
3162
3163
3164
3165
3166
3167
3168 if (dev) {
3169 int rc = pci_enable_device(dev);
3170 if (rc)
3171 pci_err(dev, "Error enabling bridge (%d)\n", rc);
3172 pci_set_master(dev);
3173 }
3174
3175
3176 list_for_each_entry(child, &bus->children, node)
3177 pnv_pci_enable_bridge(child);
3178 }
3179
3180 static void pnv_pci_enable_bridges(void)
3181 {
3182 struct pci_controller *hose;
3183
3184 list_for_each_entry(hose, &hose_list, list_node)
3185 pnv_pci_enable_bridge(hose->bus);
3186 }
3187
3188 static void pnv_pci_ioda_fixup(void)
3189 {
3190 pnv_pci_ioda_setup_PEs();
3191 pnv_pci_ioda_setup_iommu_api();
3192 pnv_pci_ioda_create_dbgfs();
3193
3194 pnv_pci_enable_bridges();
3195
3196 #ifdef CONFIG_EEH
3197 pnv_eeh_post_init();
3198 #endif
3199 }
3200
3201
3202
3203
3204
3205
3206
3207
3208
3209
3210
3211
3212
3213 static resource_size_t pnv_pci_window_alignment(struct pci_bus *bus,
3214 unsigned long type)
3215 {
3216 struct pci_dev *bridge;
3217 struct pci_controller *hose = pci_bus_to_host(bus);
3218 struct pnv_phb *phb = hose->private_data;
3219 int num_pci_bridges = 0;
3220
3221 bridge = bus->self;
3222 while (bridge) {
3223 if (pci_pcie_type(bridge) == PCI_EXP_TYPE_PCI_BRIDGE) {
3224 num_pci_bridges++;
3225 if (num_pci_bridges >= 2)
3226 return 1;
3227 }
3228
3229 bridge = bridge->bus->self;
3230 }
3231
3232
3233
3234
3235
3236
3237 if (phb->ioda.m64_segsize && pnv_pci_is_m64_flags(type))
3238 return phb->ioda.m64_segsize;
3239 if (type & IORESOURCE_MEM)
3240 return phb->ioda.m32_segsize;
3241
3242 return phb->ioda.io_segsize;
3243 }
3244
3245
3246
3247
3248
3249
3250
3251
3252
3253 static void pnv_pci_fixup_bridge_resources(struct pci_bus *bus,
3254 unsigned long type)
3255 {
3256 struct pci_controller *hose = pci_bus_to_host(bus);
3257 struct pnv_phb *phb = hose->private_data;
3258 struct pci_dev *bridge = bus->self;
3259 struct resource *r, *w;
3260 bool msi_region = false;
3261 int i;
3262
3263
3264 if (!pci_is_root_bus(bridge->bus) &&
3265 !pci_is_root_bus(bridge->bus->self->bus))
3266 return;
3267
3268
3269 for (i = 0; i < PCI_BRIDGE_RESOURCE_NUM; i++) {
3270 r = &bridge->resource[PCI_BRIDGE_RESOURCES + i];
3271 if (!r->flags || !r->parent)
3272 continue;
3273
3274 w = NULL;
3275 if (r->flags & type & IORESOURCE_IO)
3276 w = &hose->io_resource;
3277 else if (pnv_pci_is_m64(phb, r) &&
3278 (type & IORESOURCE_PREFETCH) &&
3279 phb->ioda.m64_segsize)
3280 w = &hose->mem_resources[1];
3281 else if (r->flags & type & IORESOURCE_MEM) {
3282 w = &hose->mem_resources[0];
3283 msi_region = true;
3284 }
3285
3286 r->start = w->start;
3287 r->end = w->end;
3288
3289
3290
3291
3292
3293
3294
3295
3296 if (msi_region) {
3297 r->end += 0x10000;
3298 r->end -= 0x100000;
3299 }
3300 }
3301 }
3302
3303 static void pnv_pci_setup_bridge(struct pci_bus *bus, unsigned long type)
3304 {
3305 struct pci_controller *hose = pci_bus_to_host(bus);
3306 struct pnv_phb *phb = hose->private_data;
3307 struct pci_dev *bridge = bus->self;
3308 struct pnv_ioda_pe *pe;
3309 bool all = (pci_pcie_type(bridge) == PCI_EXP_TYPE_PCI_BRIDGE);
3310
3311
3312 pnv_pci_fixup_bridge_resources(bus, type);
3313
3314
3315 if (!phb->ioda.root_pe_populated) {
3316 pe = pnv_ioda_setup_bus_PE(phb->hose->bus, false);
3317 if (pe) {
3318 phb->ioda.root_pe_idx = pe->pe_number;
3319 phb->ioda.root_pe_populated = true;
3320 }
3321 }
3322
3323
3324 if (list_empty(&bus->devices))
3325 return;
3326
3327
3328 pnv_ioda_reserve_m64_pe(bus, NULL, all);
3329
3330
3331
3332
3333
3334
3335 pe = pnv_ioda_setup_bus_PE(bus, all);
3336 if (!pe)
3337 return;
3338
3339 pnv_ioda_setup_pe_seg(pe);
3340 switch (phb->type) {
3341 case PNV_PHB_IODA1:
3342 pnv_pci_ioda1_setup_dma_pe(phb, pe);
3343 break;
3344 case PNV_PHB_IODA2:
3345 pnv_pci_ioda2_setup_dma_pe(phb, pe);
3346 break;
3347 default:
3348 pr_warn("%s: No DMA for PHB#%x (type %d)\n",
3349 __func__, phb->hose->global_number, phb->type);
3350 }
3351 }
3352
3353 static resource_size_t pnv_pci_default_alignment(void)
3354 {
3355 return PAGE_SIZE;
3356 }
3357
3358 #ifdef CONFIG_PCI_IOV
3359 static resource_size_t pnv_pci_iov_resource_alignment(struct pci_dev *pdev,
3360 int resno)
3361 {
3362 struct pci_controller *hose = pci_bus_to_host(pdev->bus);
3363 struct pnv_phb *phb = hose->private_data;
3364 struct pci_dn *pdn = pci_get_pdn(pdev);
3365 resource_size_t align;
3366
3367
3368
3369
3370
3371
3372
3373
3374
3375
3376
3377
3378
3379
3380
3381
3382
3383
3384 align = pci_iov_resource_size(pdev, resno);
3385 if (!pdn->vfs_expanded)
3386 return align;
3387 if (pdn->m64_single_mode)
3388 return max(align, (resource_size_t)phb->ioda.m64_segsize);
3389
3390 return pdn->vfs_expanded * align;
3391 }
3392 #endif
3393
3394
3395
3396
3397 static bool pnv_pci_enable_device_hook(struct pci_dev *dev)
3398 {
3399 struct pci_controller *hose = pci_bus_to_host(dev->bus);
3400 struct pnv_phb *phb = hose->private_data;
3401 struct pci_dn *pdn;
3402
3403
3404
3405
3406
3407
3408 if (!phb->initialized)
3409 return true;
3410
3411 pdn = pci_get_pdn(dev);
3412 if (!pdn || pdn->pe_number == IODA_INVALID_PE)
3413 return false;
3414
3415 return true;
3416 }
3417
3418 static long pnv_pci_ioda1_unset_window(struct iommu_table_group *table_group,
3419 int num)
3420 {
3421 struct pnv_ioda_pe *pe = container_of(table_group,
3422 struct pnv_ioda_pe, table_group);
3423 struct pnv_phb *phb = pe->phb;
3424 unsigned int idx;
3425 long rc;
3426
3427 pe_info(pe, "Removing DMA window #%d\n", num);
3428 for (idx = 0; idx < phb->ioda.dma32_count; idx++) {
3429 if (phb->ioda.dma32_segmap[idx] != pe->pe_number)
3430 continue;
3431
3432 rc = opal_pci_map_pe_dma_window(phb->opal_id, pe->pe_number,
3433 idx, 0, 0ul, 0ul, 0ul);
3434 if (rc != OPAL_SUCCESS) {
3435 pe_warn(pe, "Failure %ld unmapping DMA32 segment#%d\n",
3436 rc, idx);
3437 return rc;
3438 }
3439
3440 phb->ioda.dma32_segmap[idx] = IODA_INVALID_PE;
3441 }
3442
3443 pnv_pci_unlink_table_and_group(table_group->tables[num], table_group);
3444 return OPAL_SUCCESS;
3445 }
3446
3447 static void pnv_pci_ioda1_release_pe_dma(struct pnv_ioda_pe *pe)
3448 {
3449 unsigned int weight = pnv_pci_ioda_pe_dma_weight(pe);
3450 struct iommu_table *tbl = pe->table_group.tables[0];
3451 int64_t rc;
3452
3453 if (!weight)
3454 return;
3455
3456 rc = pnv_pci_ioda1_unset_window(&pe->table_group, 0);
3457 if (rc != OPAL_SUCCESS)
3458 return;
3459
3460 pnv_pci_p7ioc_tce_invalidate(tbl, tbl->it_offset, tbl->it_size, false);
3461 if (pe->table_group.group) {
3462 iommu_group_put(pe->table_group.group);
3463 WARN_ON(pe->table_group.group);
3464 }
3465
3466 free_pages(tbl->it_base, get_order(tbl->it_size << 3));
3467 iommu_tce_table_put(tbl);
3468 }
3469
3470 static void pnv_pci_ioda2_release_pe_dma(struct pnv_ioda_pe *pe)
3471 {
3472 struct iommu_table *tbl = pe->table_group.tables[0];
3473 unsigned int weight = pnv_pci_ioda_pe_dma_weight(pe);
3474 #ifdef CONFIG_IOMMU_API
3475 int64_t rc;
3476 #endif
3477
3478 if (!weight)
3479 return;
3480
3481 #ifdef CONFIG_IOMMU_API
3482 rc = pnv_pci_ioda2_unset_window(&pe->table_group, 0);
3483 if (rc)
3484 pe_warn(pe, "OPAL error %lld release DMA window\n", rc);
3485 #endif
3486
3487 pnv_pci_ioda2_set_bypass(pe, false);
3488 if (pe->table_group.group) {
3489 iommu_group_put(pe->table_group.group);
3490 WARN_ON(pe->table_group.group);
3491 }
3492
3493 iommu_tce_table_put(tbl);
3494 }
3495
3496 static void pnv_ioda_free_pe_seg(struct pnv_ioda_pe *pe,
3497 unsigned short win,
3498 unsigned int *map)
3499 {
3500 struct pnv_phb *phb = pe->phb;
3501 int idx;
3502 int64_t rc;
3503
3504 for (idx = 0; idx < phb->ioda.total_pe_num; idx++) {
3505 if (map[idx] != pe->pe_number)
3506 continue;
3507
3508 if (win == OPAL_M64_WINDOW_TYPE)
3509 rc = opal_pci_map_pe_mmio_window(phb->opal_id,
3510 phb->ioda.reserved_pe_idx, win,
3511 idx / PNV_IODA1_M64_SEGS,
3512 idx % PNV_IODA1_M64_SEGS);
3513 else
3514 rc = opal_pci_map_pe_mmio_window(phb->opal_id,
3515 phb->ioda.reserved_pe_idx, win, 0, idx);
3516
3517 if (rc != OPAL_SUCCESS)
3518 pe_warn(pe, "Error %lld unmapping (%d) segment#%d\n",
3519 rc, win, idx);
3520
3521 map[idx] = IODA_INVALID_PE;
3522 }
3523 }
3524
3525 static void pnv_ioda_release_pe_seg(struct pnv_ioda_pe *pe)
3526 {
3527 struct pnv_phb *phb = pe->phb;
3528
3529 if (phb->type == PNV_PHB_IODA1) {
3530 pnv_ioda_free_pe_seg(pe, OPAL_IO_WINDOW_TYPE,
3531 phb->ioda.io_segmap);
3532 pnv_ioda_free_pe_seg(pe, OPAL_M32_WINDOW_TYPE,
3533 phb->ioda.m32_segmap);
3534 pnv_ioda_free_pe_seg(pe, OPAL_M64_WINDOW_TYPE,
3535 phb->ioda.m64_segmap);
3536 } else if (phb->type == PNV_PHB_IODA2) {
3537 pnv_ioda_free_pe_seg(pe, OPAL_M32_WINDOW_TYPE,
3538 phb->ioda.m32_segmap);
3539 }
3540 }
3541
3542 static void pnv_ioda_release_pe(struct pnv_ioda_pe *pe)
3543 {
3544 struct pnv_phb *phb = pe->phb;
3545 struct pnv_ioda_pe *slave, *tmp;
3546
3547 list_del(&pe->list);
3548 switch (phb->type) {
3549 case PNV_PHB_IODA1:
3550 pnv_pci_ioda1_release_pe_dma(pe);
3551 break;
3552 case PNV_PHB_IODA2:
3553 pnv_pci_ioda2_release_pe_dma(pe);
3554 break;
3555 default:
3556 WARN_ON(1);
3557 }
3558
3559 pnv_ioda_release_pe_seg(pe);
3560 pnv_ioda_deconfigure_pe(pe->phb, pe);
3561
3562
3563 if (pe->flags & PNV_IODA_PE_MASTER) {
3564 list_for_each_entry_safe(slave, tmp, &pe->slaves, list) {
3565 list_del(&slave->list);
3566 pnv_ioda_free_pe(slave);
3567 }
3568 }
3569
3570
3571
3572
3573
3574
3575
3576 if (phb->ioda.root_pe_populated &&
3577 phb->ioda.root_pe_idx == pe->pe_number)
3578 phb->ioda.root_pe_populated = false;
3579 else
3580 pnv_ioda_free_pe(pe);
3581 }
3582
3583 static void pnv_pci_release_device(struct pci_dev *pdev)
3584 {
3585 struct pci_controller *hose = pci_bus_to_host(pdev->bus);
3586 struct pnv_phb *phb = hose->private_data;
3587 struct pci_dn *pdn = pci_get_pdn(pdev);
3588 struct pnv_ioda_pe *pe;
3589
3590 if (pdev->is_virtfn)
3591 return;
3592
3593 if (!pdn || pdn->pe_number == IODA_INVALID_PE)
3594 return;
3595
3596
3597
3598
3599
3600
3601
3602
3603
3604 pe = &phb->ioda.pe_array[pdn->pe_number];
3605 pdn->pe_number = IODA_INVALID_PE;
3606
3607 WARN_ON(--pe->device_count < 0);
3608 if (pe->device_count == 0)
3609 pnv_ioda_release_pe(pe);
3610 }
3611
3612 static void pnv_npu_disable_device(struct pci_dev *pdev)
3613 {
3614 struct eeh_dev *edev = pci_dev_to_eeh_dev(pdev);
3615 struct eeh_pe *eehpe = edev ? edev->pe : NULL;
3616
3617 if (eehpe && eeh_ops && eeh_ops->reset)
3618 eeh_ops->reset(eehpe, EEH_RESET_HOT);
3619 }
3620
3621 static void pnv_pci_ioda_shutdown(struct pci_controller *hose)
3622 {
3623 struct pnv_phb *phb = hose->private_data;
3624
3625 opal_pci_reset(phb->opal_id, OPAL_RESET_PCI_IODA_TABLE,
3626 OPAL_ASSERT_RESET);
3627 }
3628
3629 static const struct pci_controller_ops pnv_pci_ioda_controller_ops = {
3630 .dma_dev_setup = pnv_pci_dma_dev_setup,
3631 .dma_bus_setup = pnv_pci_dma_bus_setup,
3632 .iommu_bypass_supported = pnv_pci_ioda_iommu_bypass_supported,
3633 .setup_msi_irqs = pnv_setup_msi_irqs,
3634 .teardown_msi_irqs = pnv_teardown_msi_irqs,
3635 .enable_device_hook = pnv_pci_enable_device_hook,
3636 .release_device = pnv_pci_release_device,
3637 .window_alignment = pnv_pci_window_alignment,
3638 .setup_bridge = pnv_pci_setup_bridge,
3639 .reset_secondary_bus = pnv_pci_reset_secondary_bus,
3640 .shutdown = pnv_pci_ioda_shutdown,
3641 };
3642
3643 static const struct pci_controller_ops pnv_npu_ioda_controller_ops = {
3644 .dma_dev_setup = pnv_pci_dma_dev_setup,
3645 .setup_msi_irqs = pnv_setup_msi_irqs,
3646 .teardown_msi_irqs = pnv_teardown_msi_irqs,
3647 .enable_device_hook = pnv_pci_enable_device_hook,
3648 .window_alignment = pnv_pci_window_alignment,
3649 .reset_secondary_bus = pnv_pci_reset_secondary_bus,
3650 .shutdown = pnv_pci_ioda_shutdown,
3651 .disable_device = pnv_npu_disable_device,
3652 };
3653
3654 static const struct pci_controller_ops pnv_npu_ocapi_ioda_controller_ops = {
3655 .enable_device_hook = pnv_pci_enable_device_hook,
3656 .window_alignment = pnv_pci_window_alignment,
3657 .reset_secondary_bus = pnv_pci_reset_secondary_bus,
3658 .shutdown = pnv_pci_ioda_shutdown,
3659 };
3660
3661 static void __init pnv_pci_init_ioda_phb(struct device_node *np,
3662 u64 hub_id, int ioda_type)
3663 {
3664 struct pci_controller *hose;
3665 struct pnv_phb *phb;
3666 unsigned long size, m64map_off, m32map_off, pemap_off;
3667 unsigned long iomap_off = 0, dma32map_off = 0;
3668 struct resource r;
3669 const __be64 *prop64;
3670 const __be32 *prop32;
3671 int len;
3672 unsigned int segno;
3673 u64 phb_id;
3674 void *aux;
3675 long rc;
3676
3677 if (!of_device_is_available(np))
3678 return;
3679
3680 pr_info("Initializing %s PHB (%pOF)\n", pnv_phb_names[ioda_type], np);
3681
3682 prop64 = of_get_property(np, "ibm,opal-phbid", NULL);
3683 if (!prop64) {
3684 pr_err(" Missing \"ibm,opal-phbid\" property !\n");
3685 return;
3686 }
3687 phb_id = be64_to_cpup(prop64);
3688 pr_debug(" PHB-ID : 0x%016llx\n", phb_id);
3689
3690 phb = memblock_alloc(sizeof(*phb), SMP_CACHE_BYTES);
3691 if (!phb)
3692 panic("%s: Failed to allocate %zu bytes\n", __func__,
3693 sizeof(*phb));
3694
3695
3696 phb->hose = hose = pcibios_alloc_controller(np);
3697 if (!phb->hose) {
3698 pr_err(" Can't allocate PCI controller for %pOF\n",
3699 np);
3700 memblock_free(__pa(phb), sizeof(struct pnv_phb));
3701 return;
3702 }
3703
3704 spin_lock_init(&phb->lock);
3705 prop32 = of_get_property(np, "bus-range", &len);
3706 if (prop32 && len == 8) {
3707 hose->first_busno = be32_to_cpu(prop32[0]);
3708 hose->last_busno = be32_to_cpu(prop32[1]);
3709 } else {
3710 pr_warn(" Broken <bus-range> on %pOF\n", np);
3711 hose->first_busno = 0;
3712 hose->last_busno = 0xff;
3713 }
3714 hose->private_data = phb;
3715 phb->hub_id = hub_id;
3716 phb->opal_id = phb_id;
3717 phb->type = ioda_type;
3718 mutex_init(&phb->ioda.pe_alloc_mutex);
3719
3720
3721 if (of_device_is_compatible(np, "ibm,p7ioc-pciex"))
3722 phb->model = PNV_PHB_MODEL_P7IOC;
3723 else if (of_device_is_compatible(np, "ibm,power8-pciex"))
3724 phb->model = PNV_PHB_MODEL_PHB3;
3725 else if (of_device_is_compatible(np, "ibm,power8-npu-pciex"))
3726 phb->model = PNV_PHB_MODEL_NPU;
3727 else if (of_device_is_compatible(np, "ibm,power9-npu-pciex"))
3728 phb->model = PNV_PHB_MODEL_NPU2;
3729 else
3730 phb->model = PNV_PHB_MODEL_UNKNOWN;
3731
3732
3733 prop32 = of_get_property(np, "ibm,phb-diag-data-size", NULL);
3734 if (prop32)
3735 phb->diag_data_size = be32_to_cpup(prop32);
3736 else
3737 phb->diag_data_size = PNV_PCI_DIAG_BUF_SIZE;
3738
3739 phb->diag_data = memblock_alloc(phb->diag_data_size, SMP_CACHE_BYTES);
3740 if (!phb->diag_data)
3741 panic("%s: Failed to allocate %u bytes\n", __func__,
3742 phb->diag_data_size);
3743
3744
3745 pci_process_bridge_OF_ranges(hose, np, !hose->global_number);
3746
3747
3748 if (!of_address_to_resource(np, 0, &r)) {
3749 phb->regs_phys = r.start;
3750 phb->regs = ioremap(r.start, resource_size(&r));
3751 if (phb->regs == NULL)
3752 pr_err(" Failed to map registers !\n");
3753 }
3754
3755
3756 phb->ioda.total_pe_num = 1;
3757 prop32 = of_get_property(np, "ibm,opal-num-pes", NULL);
3758 if (prop32)
3759 phb->ioda.total_pe_num = be32_to_cpup(prop32);
3760 prop32 = of_get_property(np, "ibm,opal-reserved-pe", NULL);
3761 if (prop32)
3762 phb->ioda.reserved_pe_idx = be32_to_cpup(prop32);
3763
3764
3765 for (segno = 0; segno < ARRAY_SIZE(phb->ioda.pe_rmap); segno++)
3766 phb->ioda.pe_rmap[segno] = IODA_INVALID_PE;
3767
3768
3769 pnv_ioda_parse_m64_window(phb);
3770
3771 phb->ioda.m32_size = resource_size(&hose->mem_resources[0]);
3772
3773 phb->ioda.m32_size += 0x10000;
3774
3775 phb->ioda.m32_segsize = phb->ioda.m32_size / phb->ioda.total_pe_num;
3776 phb->ioda.m32_pci_base = hose->mem_resources[0].start - hose->mem_offset[0];
3777 phb->ioda.io_size = hose->pci_io_size;
3778 phb->ioda.io_segsize = phb->ioda.io_size / phb->ioda.total_pe_num;
3779 phb->ioda.io_pci_base = 0;
3780
3781
3782 phb->ioda.dma32_count = phb->ioda.m32_pci_base /
3783 PNV_IODA1_DMA32_SEGSIZE;
3784
3785
3786 size = _ALIGN_UP(max_t(unsigned, phb->ioda.total_pe_num, 8) / 8,
3787 sizeof(unsigned long));
3788 m64map_off = size;
3789 size += phb->ioda.total_pe_num * sizeof(phb->ioda.m64_segmap[0]);
3790 m32map_off = size;
3791 size += phb->ioda.total_pe_num * sizeof(phb->ioda.m32_segmap[0]);
3792 if (phb->type == PNV_PHB_IODA1) {
3793 iomap_off = size;
3794 size += phb->ioda.total_pe_num * sizeof(phb->ioda.io_segmap[0]);
3795 dma32map_off = size;
3796 size += phb->ioda.dma32_count *
3797 sizeof(phb->ioda.dma32_segmap[0]);
3798 }
3799 pemap_off = size;
3800 size += phb->ioda.total_pe_num * sizeof(struct pnv_ioda_pe);
3801 aux = memblock_alloc(size, SMP_CACHE_BYTES);
3802 if (!aux)
3803 panic("%s: Failed to allocate %lu bytes\n", __func__, size);
3804 phb->ioda.pe_alloc = aux;
3805 phb->ioda.m64_segmap = aux + m64map_off;
3806 phb->ioda.m32_segmap = aux + m32map_off;
3807 for (segno = 0; segno < phb->ioda.total_pe_num; segno++) {
3808 phb->ioda.m64_segmap[segno] = IODA_INVALID_PE;
3809 phb->ioda.m32_segmap[segno] = IODA_INVALID_PE;
3810 }
3811 if (phb->type == PNV_PHB_IODA1) {
3812 phb->ioda.io_segmap = aux + iomap_off;
3813 for (segno = 0; segno < phb->ioda.total_pe_num; segno++)
3814 phb->ioda.io_segmap[segno] = IODA_INVALID_PE;
3815
3816 phb->ioda.dma32_segmap = aux + dma32map_off;
3817 for (segno = 0; segno < phb->ioda.dma32_count; segno++)
3818 phb->ioda.dma32_segmap[segno] = IODA_INVALID_PE;
3819 }
3820 phb->ioda.pe_array = aux + pemap_off;
3821
3822
3823
3824
3825
3826
3827 pnv_ioda_reserve_pe(phb, phb->ioda.reserved_pe_idx);
3828 if (phb->ioda.reserved_pe_idx == 0) {
3829 phb->ioda.root_pe_idx = 1;
3830 pnv_ioda_reserve_pe(phb, phb->ioda.root_pe_idx);
3831 } else if (phb->ioda.reserved_pe_idx == (phb->ioda.total_pe_num - 1)) {
3832 phb->ioda.root_pe_idx = phb->ioda.reserved_pe_idx - 1;
3833 pnv_ioda_reserve_pe(phb, phb->ioda.root_pe_idx);
3834 } else {
3835 phb->ioda.root_pe_idx = IODA_INVALID_PE;
3836 }
3837
3838 INIT_LIST_HEAD(&phb->ioda.pe_list);
3839 mutex_init(&phb->ioda.pe_list_mutex);
3840
3841
3842 phb->ioda.dma32_count = phb->ioda.m32_pci_base /
3843 PNV_IODA1_DMA32_SEGSIZE;
3844
3845 #if 0
3846 rc = opal_pci_set_phb_mem_window(opal->phb_id,
3847 window_type,
3848 window_num,
3849 starting_real_address,
3850 starting_pci_address,
3851 segment_size);
3852 #endif
3853
3854 pr_info(" %03d (%03d) PE's M32: 0x%x [segment=0x%x]\n",
3855 phb->ioda.total_pe_num, phb->ioda.reserved_pe_idx,
3856 phb->ioda.m32_size, phb->ioda.m32_segsize);
3857 if (phb->ioda.m64_size)
3858 pr_info(" M64: 0x%lx [segment=0x%lx]\n",
3859 phb->ioda.m64_size, phb->ioda.m64_segsize);
3860 if (phb->ioda.io_size)
3861 pr_info(" IO: 0x%x [segment=0x%x]\n",
3862 phb->ioda.io_size, phb->ioda.io_segsize);
3863
3864
3865 phb->hose->ops = &pnv_pci_ops;
3866 phb->get_pe_state = pnv_ioda_get_pe_state;
3867 phb->freeze_pe = pnv_ioda_freeze_pe;
3868 phb->unfreeze_pe = pnv_ioda_unfreeze_pe;
3869
3870
3871 pnv_pci_init_ioda_msis(phb);
3872
3873
3874
3875
3876
3877
3878
3879
3880 ppc_md.pcibios_fixup = pnv_pci_ioda_fixup;
3881
3882 switch (phb->type) {
3883 case PNV_PHB_NPU_NVLINK:
3884 hose->controller_ops = pnv_npu_ioda_controller_ops;
3885 break;
3886 case PNV_PHB_NPU_OCAPI:
3887 hose->controller_ops = pnv_npu_ocapi_ioda_controller_ops;
3888 break;
3889 default:
3890 phb->dma_dev_setup = pnv_pci_ioda_dma_dev_setup;
3891 hose->controller_ops = pnv_pci_ioda_controller_ops;
3892 }
3893
3894 ppc_md.pcibios_default_alignment = pnv_pci_default_alignment;
3895
3896 #ifdef CONFIG_PCI_IOV
3897 ppc_md.pcibios_fixup_sriov = pnv_pci_ioda_fixup_iov;
3898 ppc_md.pcibios_iov_resource_alignment = pnv_pci_iov_resource_alignment;
3899 ppc_md.pcibios_sriov_enable = pnv_pcibios_sriov_enable;
3900 ppc_md.pcibios_sriov_disable = pnv_pcibios_sriov_disable;
3901 #endif
3902
3903 pci_add_flags(PCI_REASSIGN_ALL_RSRC);
3904
3905
3906 rc = opal_pci_reset(phb_id, OPAL_RESET_PCI_IODA_TABLE, OPAL_ASSERT_RESET);
3907 if (rc)
3908 pr_warn(" OPAL Error %ld performing IODA table reset !\n", rc);
3909
3910
3911
3912
3913
3914
3915
3916
3917
3918
3919
3920 if (is_kdump_kernel() || pci_reset_phbs || rc) {
3921 pr_info(" Issue PHB reset ...\n");
3922 pnv_eeh_phb_reset(hose, EEH_RESET_FUNDAMENTAL);
3923 pnv_eeh_phb_reset(hose, EEH_RESET_DEACTIVATE);
3924 }
3925
3926
3927 if (!phb->init_m64 || phb->init_m64(phb))
3928 hose->mem_resources[1].flags = 0;
3929 }
3930
3931 void __init pnv_pci_init_ioda2_phb(struct device_node *np)
3932 {
3933 pnv_pci_init_ioda_phb(np, 0, PNV_PHB_IODA2);
3934 }
3935
3936 void __init pnv_pci_init_npu_phb(struct device_node *np)
3937 {
3938 pnv_pci_init_ioda_phb(np, 0, PNV_PHB_NPU_NVLINK);
3939 }
3940
3941 void __init pnv_pci_init_npu2_opencapi_phb(struct device_node *np)
3942 {
3943 pnv_pci_init_ioda_phb(np, 0, PNV_PHB_NPU_OCAPI);
3944 }
3945
3946 static void pnv_npu2_opencapi_cfg_size_fixup(struct pci_dev *dev)
3947 {
3948 struct pci_controller *hose = pci_bus_to_host(dev->bus);
3949 struct pnv_phb *phb = hose->private_data;
3950
3951 if (!machine_is(powernv))
3952 return;
3953
3954 if (phb->type == PNV_PHB_NPU_OCAPI)
3955 dev->cfg_size = PCI_CFG_SPACE_EXP_SIZE;
3956 }
3957 DECLARE_PCI_FIXUP_EARLY(PCI_ANY_ID, PCI_ANY_ID, pnv_npu2_opencapi_cfg_size_fixup);
3958
3959 void __init pnv_pci_init_ioda_hub(struct device_node *np)
3960 {
3961 struct device_node *phbn;
3962 const __be64 *prop64;
3963 u64 hub_id;
3964
3965 pr_info("Probing IODA IO-Hub %pOF\n", np);
3966
3967 prop64 = of_get_property(np, "ibm,opal-hubid", NULL);
3968 if (!prop64) {
3969 pr_err(" Missing \"ibm,opal-hubid\" property !\n");
3970 return;
3971 }
3972 hub_id = be64_to_cpup(prop64);
3973 pr_devel(" HUB-ID : 0x%016llx\n", hub_id);
3974
3975
3976 for_each_child_of_node(np, phbn) {
3977
3978 if (of_device_is_compatible(phbn, "ibm,ioda-phb"))
3979 pnv_pci_init_ioda_phb(phbn, hub_id, PNV_PHB_IODA1);
3980 }
3981 }