root/arch/powerpc/platforms/powernv/pci.h

INCLUDED FROM

   1 /* SPDX-License-Identifier: GPL-2.0 */
   2 #ifndef __POWERNV_PCI_H
   3 #define __POWERNV_PCI_H
   4 
   5 #include <linux/compiler.h>             /* for __printf */
   6 #include <linux/iommu.h>
   7 #include <asm/iommu.h>
   8 #include <asm/msi_bitmap.h>
   9 
  10 struct pci_dn;
  11 
  12 enum pnv_phb_type {
  13         PNV_PHB_IODA1           = 0,
  14         PNV_PHB_IODA2           = 1,
  15         PNV_PHB_NPU_NVLINK      = 2,
  16         PNV_PHB_NPU_OCAPI       = 3,
  17 };
  18 
  19 /* Precise PHB model for error management */
  20 enum pnv_phb_model {
  21         PNV_PHB_MODEL_UNKNOWN,
  22         PNV_PHB_MODEL_P7IOC,
  23         PNV_PHB_MODEL_PHB3,
  24         PNV_PHB_MODEL_NPU,
  25         PNV_PHB_MODEL_NPU2,
  26 };
  27 
  28 #define PNV_PCI_DIAG_BUF_SIZE   8192
  29 #define PNV_IODA_PE_DEV         (1 << 0)        /* PE has single PCI device     */
  30 #define PNV_IODA_PE_BUS         (1 << 1)        /* PE has primary PCI bus       */
  31 #define PNV_IODA_PE_BUS_ALL     (1 << 2)        /* PE has subordinate buses     */
  32 #define PNV_IODA_PE_MASTER      (1 << 3)        /* Master PE in compound case   */
  33 #define PNV_IODA_PE_SLAVE       (1 << 4)        /* Slave PE in compound case    */
  34 #define PNV_IODA_PE_VF          (1 << 5)        /* PE for one VF                */
  35 
  36 /* Indicates operations are frozen for a PE: MMIO in PESTA & DMA in PESTB. */
  37 #define PNV_IODA_STOPPED_STATE  0x8000000000000000
  38 
  39 /* Data associated with a PE, including IOMMU tracking etc.. */
  40 struct pnv_phb;
  41 struct pnv_ioda_pe {
  42         unsigned long           flags;
  43         struct pnv_phb          *phb;
  44         int                     device_count;
  45 
  46         /* A PE can be associated with a single device or an
  47          * entire bus (& children). In the former case, pdev
  48          * is populated, in the later case, pbus is.
  49          */
  50 #ifdef CONFIG_PCI_IOV
  51         struct pci_dev          *parent_dev;
  52 #endif
  53         struct pci_dev          *pdev;
  54         struct pci_bus          *pbus;
  55 
  56         /* Effective RID (device RID for a device PE and base bus
  57          * RID with devfn 0 for a bus PE)
  58          */
  59         unsigned int            rid;
  60 
  61         /* PE number */
  62         unsigned int            pe_number;
  63 
  64         /* "Base" iommu table, ie, 4K TCEs, 32-bit DMA */
  65         struct iommu_table_group table_group;
  66         struct npu_comp         *npucomp;
  67 
  68         /* 64-bit TCE bypass region */
  69         bool                    tce_bypass_enabled;
  70         uint64_t                tce_bypass_base;
  71 
  72         /* MSIs. MVE index is identical for for 32 and 64 bit MSI
  73          * and -1 if not supported. (It's actually identical to the
  74          * PE number)
  75          */
  76         int                     mve_number;
  77 
  78         /* PEs in compound case */
  79         struct pnv_ioda_pe      *master;
  80         struct list_head        slaves;
  81 
  82         /* Link in list of PE#s */
  83         struct list_head        list;
  84 };
  85 
  86 #define PNV_PHB_FLAG_EEH        (1 << 0)
  87 
  88 struct pnv_phb {
  89         struct pci_controller   *hose;
  90         enum pnv_phb_type       type;
  91         enum pnv_phb_model      model;
  92         u64                     hub_id;
  93         u64                     opal_id;
  94         int                     flags;
  95         void __iomem            *regs;
  96         u64                     regs_phys;
  97         int                     initialized;
  98         spinlock_t              lock;
  99 
 100 #ifdef CONFIG_DEBUG_FS
 101         int                     has_dbgfs;
 102         struct dentry           *dbgfs;
 103 #endif
 104 
 105         unsigned int            msi_base;
 106         unsigned int            msi32_support;
 107         struct msi_bitmap       msi_bmp;
 108         int (*msi_setup)(struct pnv_phb *phb, struct pci_dev *dev,
 109                          unsigned int hwirq, unsigned int virq,
 110                          unsigned int is_64, struct msi_msg *msg);
 111         void (*dma_dev_setup)(struct pnv_phb *phb, struct pci_dev *pdev);
 112         int (*init_m64)(struct pnv_phb *phb);
 113         int (*get_pe_state)(struct pnv_phb *phb, int pe_no);
 114         void (*freeze_pe)(struct pnv_phb *phb, int pe_no);
 115         int (*unfreeze_pe)(struct pnv_phb *phb, int pe_no, int opt);
 116 
 117         struct {
 118                 /* Global bridge info */
 119                 unsigned int            total_pe_num;
 120                 unsigned int            reserved_pe_idx;
 121                 unsigned int            root_pe_idx;
 122                 bool                    root_pe_populated;
 123 
 124                 /* 32-bit MMIO window */
 125                 unsigned int            m32_size;
 126                 unsigned int            m32_segsize;
 127                 unsigned int            m32_pci_base;
 128 
 129                 /* 64-bit MMIO window */
 130                 unsigned int            m64_bar_idx;
 131                 unsigned long           m64_size;
 132                 unsigned long           m64_segsize;
 133                 unsigned long           m64_base;
 134                 unsigned long           m64_bar_alloc;
 135 
 136                 /* IO ports */
 137                 unsigned int            io_size;
 138                 unsigned int            io_segsize;
 139                 unsigned int            io_pci_base;
 140 
 141                 /* PE allocation */
 142                 struct mutex            pe_alloc_mutex;
 143                 unsigned long           *pe_alloc;
 144                 struct pnv_ioda_pe      *pe_array;
 145 
 146                 /* M32 & IO segment maps */
 147                 unsigned int            *m64_segmap;
 148                 unsigned int            *m32_segmap;
 149                 unsigned int            *io_segmap;
 150 
 151                 /* DMA32 segment maps - IODA1 only */
 152                 unsigned int            dma32_count;
 153                 unsigned int            *dma32_segmap;
 154 
 155                 /* IRQ chip */
 156                 int                     irq_chip_init;
 157                 struct irq_chip         irq_chip;
 158 
 159                 /* Sorted list of used PE's based
 160                  * on the sequence of creation
 161                  */
 162                 struct list_head        pe_list;
 163                 struct mutex            pe_list_mutex;
 164 
 165                 /* Reverse map of PEs, indexed by {bus, devfn} */
 166                 unsigned int            pe_rmap[0x10000];
 167         } ioda;
 168 
 169         /* PHB and hub diagnostics */
 170         unsigned int            diag_data_size;
 171         u8                      *diag_data;
 172 };
 173 
 174 extern struct pci_ops pnv_pci_ops;
 175 
 176 void pnv_pci_dump_phb_diag_data(struct pci_controller *hose,
 177                                 unsigned char *log_buff);
 178 int pnv_pci_cfg_read(struct pci_dn *pdn,
 179                      int where, int size, u32 *val);
 180 int pnv_pci_cfg_write(struct pci_dn *pdn,
 181                       int where, int size, u32 val);
 182 extern struct iommu_table *pnv_pci_table_alloc(int nid);
 183 
 184 extern void pnv_pci_init_ioda_hub(struct device_node *np);
 185 extern void pnv_pci_init_ioda2_phb(struct device_node *np);
 186 extern void pnv_pci_init_npu_phb(struct device_node *np);
 187 extern void pnv_pci_init_npu2_opencapi_phb(struct device_node *np);
 188 extern void pnv_npu2_map_lpar(struct pnv_ioda_pe *gpe, unsigned long msr);
 189 extern void pnv_pci_reset_secondary_bus(struct pci_dev *dev);
 190 extern int pnv_eeh_phb_reset(struct pci_controller *hose, int option);
 191 
 192 extern void pnv_pci_dma_dev_setup(struct pci_dev *pdev);
 193 extern void pnv_pci_dma_bus_setup(struct pci_bus *bus);
 194 extern int pnv_setup_msi_irqs(struct pci_dev *pdev, int nvec, int type);
 195 extern void pnv_teardown_msi_irqs(struct pci_dev *pdev);
 196 extern struct pnv_ioda_pe *pnv_ioda_get_pe(struct pci_dev *dev);
 197 extern void pnv_set_msi_irq_chip(struct pnv_phb *phb, unsigned int virq);
 198 extern unsigned long pnv_pci_ioda2_get_table_size(__u32 page_shift,
 199                 __u64 window_size, __u32 levels);
 200 extern int pnv_eeh_post_init(void);
 201 
 202 __printf(3, 4)
 203 extern void pe_level_printk(const struct pnv_ioda_pe *pe, const char *level,
 204                             const char *fmt, ...);
 205 #define pe_err(pe, fmt, ...)                                    \
 206         pe_level_printk(pe, KERN_ERR, fmt, ##__VA_ARGS__)
 207 #define pe_warn(pe, fmt, ...)                                   \
 208         pe_level_printk(pe, KERN_WARNING, fmt, ##__VA_ARGS__)
 209 #define pe_info(pe, fmt, ...)                                   \
 210         pe_level_printk(pe, KERN_INFO, fmt, ##__VA_ARGS__)
 211 
 212 /* Nvlink functions */
 213 extern void pnv_npu_try_dma_set_bypass(struct pci_dev *gpdev, bool bypass);
 214 extern void pnv_pci_ioda2_tce_invalidate_entire(struct pnv_phb *phb, bool rm);
 215 extern struct pnv_ioda_pe *pnv_pci_npu_setup_iommu(struct pnv_ioda_pe *npe);
 216 extern struct iommu_table_group *pnv_try_setup_npu_table_group(
 217                 struct pnv_ioda_pe *pe);
 218 extern struct iommu_table_group *pnv_npu_compound_attach(
 219                 struct pnv_ioda_pe *pe);
 220 
 221 /* pci-ioda-tce.c */
 222 #define POWERNV_IOMMU_DEFAULT_LEVELS    2
 223 #define POWERNV_IOMMU_MAX_LEVELS        5
 224 
 225 extern int pnv_tce_build(struct iommu_table *tbl, long index, long npages,
 226                 unsigned long uaddr, enum dma_data_direction direction,
 227                 unsigned long attrs);
 228 extern void pnv_tce_free(struct iommu_table *tbl, long index, long npages);
 229 extern int pnv_tce_xchg(struct iommu_table *tbl, long index,
 230                 unsigned long *hpa, enum dma_data_direction *direction,
 231                 bool alloc);
 232 extern __be64 *pnv_tce_useraddrptr(struct iommu_table *tbl, long index,
 233                 bool alloc);
 234 extern unsigned long pnv_tce_get(struct iommu_table *tbl, long index);
 235 
 236 extern long pnv_pci_ioda2_table_alloc_pages(int nid, __u64 bus_offset,
 237                 __u32 page_shift, __u64 window_size, __u32 levels,
 238                 bool alloc_userspace_copy, struct iommu_table *tbl);
 239 extern void pnv_pci_ioda2_table_free_pages(struct iommu_table *tbl);
 240 
 241 extern long pnv_pci_link_table_and_group(int node, int num,
 242                 struct iommu_table *tbl,
 243                 struct iommu_table_group *table_group);
 244 extern void pnv_pci_unlink_table_and_group(struct iommu_table *tbl,
 245                 struct iommu_table_group *table_group);
 246 extern void pnv_pci_setup_iommu_table(struct iommu_table *tbl,
 247                 void *tce_mem, u64 tce_size,
 248                 u64 dma_offset, unsigned int page_shift);
 249 
 250 #endif /* __POWERNV_PCI_H */