root/arch/powerpc/platforms/44x/fsp2.h

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INCLUDED FROM

   1 #ifndef _ASM_POWERPC_FSP_DCR_H_
   2 #define _ASM_POWERPC_FSP_DCR_H_
   3 #ifdef __KERNEL__
   4 #include <asm/dcr.h>
   5 
   6 #define DCRN_CMU_ADDR           0x00C   /* Chip management unic addr */
   7 #define DCRN_CMU_DATA           0x00D   /* Chip management unic data */
   8 
   9 /* PLB4 Arbiter */
  10 #define DCRN_PLB4_PCBI          0x010   /* PLB Crossbar ID/Rev Register */
  11 #define DCRN_PLB4_P0ACR         0x011   /* PLB0 Arbiter Control Register */
  12 #define DCRN_PLB4_P0ESRL        0x012   /* PLB0 Error Status Register Low */
  13 #define DCRN_PLB4_P0ESRH        0x013   /* PLB0 Error Status Register High */
  14 #define DCRN_PLB4_P0EARL        0x014   /* PLB0 Error Address Register Low */
  15 #define DCRN_PLB4_P0EARH        0x015   /* PLB0 Error Address Register High */
  16 #define DCRN_PLB4_P0ESRLS       0x016   /* PLB0 Error Status Register Low Set*/
  17 #define DCRN_PLB4_P0ESRHS       0x017   /* PLB0 Error Status Register High */
  18 #define DCRN_PLB4_PCBC          0x018   /* PLB Crossbar Control Register */
  19 #define DCRN_PLB4_P1ACR         0x019   /* PLB1 Arbiter Control Register */
  20 #define DCRN_PLB4_P1ESRL        0x01A   /* PLB1 Error Status Register Low */
  21 #define DCRN_PLB4_P1ESRH        0x01B   /* PLB1 Error Status Register High */
  22 #define DCRN_PLB4_P1EARL        0x01C   /* PLB1 Error Address Register Low */
  23 #define DCRN_PLB4_P1EARH        0x01D   /* PLB1 Error Address Register High */
  24 #define DCRN_PLB4_P1ESRLS       0x01E   /* PLB1 Error Status Register Low Set*/
  25 #define DCRN_PLB4_P1ESRHS       0x01F   /*PLB1 Error Status Register High Set*/
  26 
  27 /* PLB4/OPB bridge 0, 1, 2, 3 */
  28 #define DCRN_PLB4OPB0_BASE      0x020
  29 #define DCRN_PLB4OPB1_BASE      0x030
  30 #define DCRN_PLB4OPB2_BASE      0x040
  31 #define DCRN_PLB4OPB3_BASE      0x050
  32 
  33 #define PLB4OPB_GESR0           0x0     /* Error status 0: Master Dev 0-3 */
  34 #define PLB4OPB_GEAR            0x2     /* Error Address Register */
  35 #define PLB4OPB_GEARU           0x3     /* Error Upper Address Register */
  36 #define PLB4OPB_GESR1           0x4     /* Error Status 1: Master Dev 4-7 */
  37 #define PLB4OPB_GESR2           0xC     /* Error Status 2: Master Dev 8-11 */
  38 
  39 /* PLB4-to-AHB Bridge */
  40 #define DCRN_PLB4AHB_BASE       0x400
  41 #define DCRN_PLB4AHB_SEUAR      (DCRN_PLB4AHB_BASE + 1)
  42 #define DCRN_PLB4AHB_SELAR      (DCRN_PLB4AHB_BASE + 2)
  43 #define DCRN_PLB4AHB_ESR        (DCRN_PLB4AHB_BASE + 3)
  44 #define DCRN_AHBPLB4_ESR        (DCRN_PLB4AHB_BASE + 8)
  45 #define DCRN_AHBPLB4_EAR        (DCRN_PLB4AHB_BASE + 9)
  46 
  47 /* PLB6 Controller */
  48 #define DCRN_PLB6_BASE          0x11111300
  49 #define DCRN_PLB6_CR0           (DCRN_PLB6_BASE)
  50 #define DCRN_PLB6_ERR           (DCRN_PLB6_BASE + 0x0B)
  51 #define DCRN_PLB6_HD            (DCRN_PLB6_BASE + 0x0E)
  52 #define DCRN_PLB6_SHD           (DCRN_PLB6_BASE + 0x10)
  53 
  54 /* PLB4-to-PLB6 Bridge */
  55 #define DCRN_PLB4PLB6_BASE      0x11111320
  56 #define DCRN_PLB4PLB6_ESR       (DCRN_PLB4PLB6_BASE + 1)
  57 #define DCRN_PLB4PLB6_EARH      (DCRN_PLB4PLB6_BASE + 3)
  58 #define DCRN_PLB4PLB6_EARL      (DCRN_PLB4PLB6_BASE + 4)
  59 
  60 /* PLB6-to-PLB4 Bridge */
  61 #define DCRN_PLB6PLB4_BASE      0x11111350
  62 #define DCRN_PLB6PLB4_ESR       (DCRN_PLB6PLB4_BASE + 1)
  63 #define DCRN_PLB6PLB4_EARH      (DCRN_PLB6PLB4_BASE + 3)
  64 #define DCRN_PLB6PLB4_EARL      (DCRN_PLB6PLB4_BASE + 4)
  65 
  66 /* PLB6-to-MCIF Bridge */
  67 #define DCRN_PLB6MCIF_BASE      0x11111380
  68 #define DCRN_PLB6MCIF_BESR0     (DCRN_PLB6MCIF_BASE + 0)
  69 #define DCRN_PLB6MCIF_BESR1     (DCRN_PLB6MCIF_BASE + 1)
  70 #define DCRN_PLB6MCIF_BEARL     (DCRN_PLB6MCIF_BASE + 2)
  71 #define DCRN_PLB6MCIF_BEARH     (DCRN_PLB6MCIF_BASE + 3)
  72 
  73 /* Configuration Logic Registers */
  74 #define DCRN_CONF_BASE          0x11111400
  75 #define DCRN_CONF_FIR_RWC       (DCRN_CONF_BASE + 0x3A)
  76 #define DCRN_CONF_EIR_RS        (DCRN_CONF_BASE + 0x3E)
  77 #define DCRN_CONF_RPERR0        (DCRN_CONF_BASE + 0x4D)
  78 #define DCRN_CONF_RPERR1        (DCRN_CONF_BASE + 0x4E)
  79 
  80 #define DCRN_L2CDCRAI           0x11111100
  81 #define DCRN_L2CDCRDI           0x11111104
  82 /* L2 indirect addresses */
  83 #define L2MCK           0x120
  84 #define L2MCKEN         0x130
  85 #define L2INT           0x150
  86 #define L2INTEN         0x160
  87 #define L2LOG0          0x180
  88 #define L2LOG1          0x184
  89 #define L2LOG2          0x188
  90 #define L2LOG3          0x18C
  91 #define L2LOG4          0x190
  92 #define L2LOG5          0x194
  93 #define L2PLBSTAT0      0x300
  94 #define L2PLBSTAT1      0x304
  95 #define L2PLBMCKEN0     0x330
  96 #define L2PLBMCKEN1     0x334
  97 #define L2PLBINTEN0     0x360
  98 #define L2PLBINTEN1     0x364
  99 #define L2ARRSTAT0      0x500
 100 #define L2ARRSTAT1      0x504
 101 #define L2ARRSTAT2      0x508
 102 #define L2ARRMCKEN0     0x530
 103 #define L2ARRMCKEN1     0x534
 104 #define L2ARRMCKEN2     0x538
 105 #define L2ARRINTEN0     0x560
 106 #define L2ARRINTEN1     0x564
 107 #define L2ARRINTEN2     0x568
 108 #define L2CPUSTAT       0x700
 109 #define L2CPUMCKEN      0x730
 110 #define L2CPUINTEN      0x760
 111 #define L2RACSTAT0      0x900
 112 #define L2RACMCKEN0     0x930
 113 #define L2RACINTEN0     0x960
 114 #define L2WACSTAT0      0xD00
 115 #define L2WACSTAT1      0xD04
 116 #define L2WACSTAT2      0xD08
 117 #define L2WACMCKEN0     0xD30
 118 #define L2WACMCKEN1     0xD34
 119 #define L2WACMCKEN2     0xD38
 120 #define L2WACINTEN0     0xD60
 121 #define L2WACINTEN1     0xD64
 122 #define L2WACINTEN2     0xD68
 123 #define L2WDFSTAT       0xF00
 124 #define L2WDFMCKEN      0xF30
 125 #define L2WDFINTEN      0xF60
 126 
 127 /* DDR3/4 Memory Controller */
 128 #define DCRN_DDR34_BASE                 0x11120000
 129 #define DCRN_DDR34_MCSTAT               0x10
 130 #define DCRN_DDR34_MCOPT1               0x20
 131 #define DCRN_DDR34_MCOPT2               0x21
 132 #define DCRN_DDR34_PHYSTAT              0x32
 133 #define DCRN_DDR34_CFGR0                0x40
 134 #define DCRN_DDR34_CFGR1                0x41
 135 #define DCRN_DDR34_CFGR2                0x42
 136 #define DCRN_DDR34_CFGR3                0x43
 137 #define DCRN_DDR34_SCRUB_CNTL           0xAA
 138 #define DCRN_DDR34_SCRUB_INT            0xAB
 139 #define DCRN_DDR34_SCRUB_START_ADDR     0xB0
 140 #define DCRN_DDR34_SCRUB_END_ADDR       0xD0
 141 #define DCRN_DDR34_ECCERR_ADDR_PORT0    0xE0
 142 #define DCRN_DDR34_ECCERR_ADDR_PORT1    0xE1
 143 #define DCRN_DDR34_ECCERR_ADDR_PORT2    0xE2
 144 #define DCRN_DDR34_ECCERR_ADDR_PORT3    0xE3
 145 #define DCRN_DDR34_ECCERR_COUNT_PORT0   0xE4
 146 #define DCRN_DDR34_ECCERR_COUNT_PORT1   0xE5
 147 #define DCRN_DDR34_ECCERR_COUNT_PORT2   0xE6
 148 #define DCRN_DDR34_ECCERR_COUNT_PORT3   0xE7
 149 #define DCRN_DDR34_ECCERR_PORT0         0xF0
 150 #define DCRN_DDR34_ECCERR_PORT1         0xF2
 151 #define DCRN_DDR34_ECCERR_PORT2         0xF4
 152 #define DCRN_DDR34_ECCERR_PORT3         0xF6
 153 #define DCRN_DDR34_ECC_CHECK_PORT0      0xF8
 154 #define DCRN_DDR34_ECC_CHECK_PORT1      0xF9
 155 #define DCRN_DDR34_ECC_CHECK_PORT2      0xF9
 156 #define DCRN_DDR34_ECC_CHECK_PORT3      0xFB
 157 
 158 #define DDR34_SCRUB_CNTL_STOP           0x00000000
 159 #define DDR34_SCRUB_CNTL_SCRUB          0x80000000
 160 #define DDR34_SCRUB_CNTL_UE_STOP        0x20000000
 161 #define DDR34_SCRUB_CNTL_CE_STOP        0x10000000
 162 #define DDR34_SCRUB_CNTL_RANK_EN        0x00008000
 163 
 164 /* PLB-Attached DDR3/4 Core Wrapper */
 165 #define DCRN_CW_BASE                    0x11111800
 166 #define DCRN_CW_MCER0                   0x00
 167 #define DCRN_CW_MCER1                   0x01
 168 #define DCRN_CW_MCER_AND0               0x02
 169 #define DCRN_CW_MCER_AND1               0x03
 170 #define DCRN_CW_MCER_OR0                0x04
 171 #define DCRN_CW_MCER_OR1                0x05
 172 #define DCRN_CW_MCER_MASK0              0x06
 173 #define DCRN_CW_MCER_MASK1              0x07
 174 #define DCRN_CW_MCER_MASK_AND0          0x08
 175 #define DCRN_CW_MCER_MASK_AND1          0x09
 176 #define DCRN_CW_MCER_MASK_OR0           0x0A
 177 #define DCRN_CW_MCER_MASK_OR1           0x0B
 178 #define DCRN_CW_MCER_ACTION0            0x0C
 179 #define DCRN_CW_MCER_ACTION1            0x0D
 180 #define DCRN_CW_MCER_WOF0               0x0E
 181 #define DCRN_CW_MCER_WOF1               0x0F
 182 #define DCRN_CW_LFIR                    0x10
 183 #define DCRN_CW_LFIR_AND                0x11
 184 #define DCRN_CW_LFIR_OR                 0x12
 185 #define DCRN_CW_LFIR_MASK               0x13
 186 #define DCRN_CW_LFIR_MASK_AND           0x14
 187 #define DCRN_CW_LFIR_MASK_OR            0x15
 188 
 189 #define CW_MCER0_MEM_CE                 0x00020000
 190 /* CMU addresses */
 191 #define CMUN_CRCS               0x00 /* Chip Reset Control/Status */
 192 #define CMUN_CONFFIR0           0x20 /* Config Reg Parity FIR 0 */
 193 #define CMUN_CONFFIR1           0x21 /* Config Reg Parity FIR 1 */
 194 #define CMUN_CONFFIR2           0x22 /* Config Reg Parity FIR 2 */
 195 #define CMUN_CONFFIR3           0x23 /* Config Reg Parity FIR 3 */
 196 #define CMUN_URCR3_RS           0x24 /* Unit Reset Control Reg 3 Set */
 197 #define CMUN_URCR3_C            0x25 /* Unit Reset Control Reg 3 Clear */
 198 #define CMUN_URCR3_P            0x26 /* Unit Reset Control Reg 3 Pulse */
 199 #define CMUN_PW0                0x2C /* Pulse Width Register */
 200 #define CMUN_URCR0_P            0x2D /* Unit Reset Control Reg 0 Pulse */
 201 #define CMUN_URCR1_P            0x2E /* Unit Reset Control Reg 1 Pulse */
 202 #define CMUN_URCR2_P            0x2F /* Unit Reset Control Reg 2 Pulse */
 203 #define CMUN_CLS_RW             0x30 /* Code Load Status (Read/Write) */
 204 #define CMUN_CLS_S              0x31 /* Code Load Status (Set) */
 205 #define CMUN_CLS_C              0x32 /* Code Load Status (Clear */
 206 #define CMUN_URCR2_RS           0x33 /* Unit Reset Control Reg 2 Set */
 207 #define CMUN_URCR2_C            0x34 /* Unit Reset Control Reg 2 Clear */
 208 #define CMUN_CLKEN0             0x35 /* Clock Enable 0 */
 209 #define CMUN_CLKEN1             0x36 /* Clock Enable 1 */
 210 #define CMUN_PCD0               0x37 /* PSI clock divider 0 */
 211 #define CMUN_PCD1               0x38 /* PSI clock divider 1 */
 212 #define CMUN_TMR0               0x39 /* Reset Timer */
 213 #define CMUN_TVS0               0x3A /* TV Sense Reg 0 */
 214 #define CMUN_TVS1               0x3B /* TV Sense Reg 1 */
 215 #define CMUN_MCCR               0x3C /* DRAM Configuration Reg */
 216 #define CMUN_FIR0               0x3D /* Fault Isolation Reg 0 */
 217 #define CMUN_FMR0               0x3E /* FIR Mask Reg 0 */
 218 #define CMUN_ETDRB              0x3F /* ETDR Backdoor */
 219 
 220 /* CRCS bit fields */
 221 #define CRCS_STAT_MASK          0xF0000000
 222 #define CRCS_STAT_POR           0x10000000
 223 #define CRCS_STAT_PHR           0x20000000
 224 #define CRCS_STAT_PCIE          0x30000000
 225 #define CRCS_STAT_CRCS_SYS      0x40000000
 226 #define CRCS_STAT_DBCR_SYS      0x50000000
 227 #define CRCS_STAT_HOST_SYS      0x60000000
 228 #define CRCS_STAT_CHIP_RST_B    0x70000000
 229 #define CRCS_STAT_CRCS_CHIP     0x80000000
 230 #define CRCS_STAT_DBCR_CHIP     0x90000000
 231 #define CRCS_STAT_HOST_CHIP     0xA0000000
 232 #define CRCS_STAT_PSI_CHIP      0xB0000000
 233 #define CRCS_STAT_CRCS_CORE     0xC0000000
 234 #define CRCS_STAT_DBCR_CORE     0xD0000000
 235 #define CRCS_STAT_HOST_CORE     0xE0000000
 236 #define CRCS_STAT_PCIE_HOT      0xF0000000
 237 #define CRCS_STAT_SELF_CORE     0x40000000
 238 #define CRCS_STAT_SELF_CHIP     0x50000000
 239 #define CRCS_WATCHE             0x08000000
 240 #define CRCS_CORE               0x04000000 /* Reset PPC440 core */
 241 #define CRCS_CHIP               0x02000000 /* Chip Reset */
 242 #define CRCS_SYS                0x01000000 /* System Reset */
 243 #define CRCS_WRCR               0x00800000 /* Watchdog reset on core reset */
 244 #define CRCS_EXTCR              0x00080000 /* CHIP_RST_B triggers chip reset */
 245 #define CRCS_PLOCK              0x00000002 /* PLL Locked */
 246 
 247 #define mtcmu(reg, data)                \
 248 do {                                    \
 249         mtdcr(DCRN_CMU_ADDR, reg);      \
 250         mtdcr(DCRN_CMU_DATA, data);     \
 251 } while (0)
 252 
 253 #define mfcmu(reg)\
 254         ({u32 data;                     \
 255         mtdcr(DCRN_CMU_ADDR, reg);      \
 256         data = mfdcr(DCRN_CMU_DATA);    \
 257         data; })
 258 
 259 #define mtl2(reg, data)                 \
 260 do {                                    \
 261         mtdcr(DCRN_L2CDCRAI, reg);      \
 262         mtdcr(DCRN_L2CDCRDI, data);     \
 263 } while (0)
 264 
 265 #define mfl2(reg)                       \
 266         ({u32 data;                     \
 267         mtdcr(DCRN_L2CDCRAI, reg);      \
 268         data = mfdcr(DCRN_L2CDCRDI);    \
 269         data; })
 270 
 271 #endif /* __KERNEL__ */
 272 #endif /* _ASM_POWERPC_FSP2_DCR_H_ */
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