This source file includes following definitions.
- spufs_handle_event
- spufs_handle_class0
- spufs_handle_class1
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9 #include <linux/sched/signal.h>
10 #include <linux/mm.h>
11
12 #include <asm/spu.h>
13 #include <asm/spu_csa.h>
14
15 #include "spufs.h"
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22
23 static void spufs_handle_event(struct spu_context *ctx,
24 unsigned long ea, int type)
25 {
26 if (ctx->flags & SPU_CREATE_EVENTS_ENABLED) {
27 ctx->event_return |= type;
28 wake_up_all(&ctx->stop_wq);
29 return;
30 }
31
32 switch (type) {
33 case SPE_EVENT_INVALID_DMA:
34 force_sig_fault(SIGBUS, BUS_OBJERR, NULL);
35 break;
36 case SPE_EVENT_SPE_DATA_STORAGE:
37 ctx->ops->restart_dma(ctx);
38 force_sig_fault(SIGSEGV, SEGV_ACCERR, (void __user *)ea);
39 break;
40 case SPE_EVENT_DMA_ALIGNMENT:
41
42 force_sig_fault(SIGBUS, BUS_ADRALN, NULL);
43 break;
44 case SPE_EVENT_SPE_ERROR:
45 force_sig_fault(
46 SIGILL, ILL_ILLOPC,
47 (void __user *)(unsigned long)
48 ctx->ops->npc_read(ctx) - 4);
49 break;
50 }
51 }
52
53 int spufs_handle_class0(struct spu_context *ctx)
54 {
55 unsigned long stat = ctx->csa.class_0_pending & CLASS0_INTR_MASK;
56
57 if (likely(!stat))
58 return 0;
59
60 if (stat & CLASS0_DMA_ALIGNMENT_INTR)
61 spufs_handle_event(ctx, ctx->csa.class_0_dar,
62 SPE_EVENT_DMA_ALIGNMENT);
63
64 if (stat & CLASS0_INVALID_DMA_COMMAND_INTR)
65 spufs_handle_event(ctx, ctx->csa.class_0_dar,
66 SPE_EVENT_INVALID_DMA);
67
68 if (stat & CLASS0_SPU_ERROR_INTR)
69 spufs_handle_event(ctx, ctx->csa.class_0_dar,
70 SPE_EVENT_SPE_ERROR);
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72 ctx->csa.class_0_pending = 0;
73
74 return -EIO;
75 }
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86 int spufs_handle_class1(struct spu_context *ctx)
87 {
88 u64 ea, dsisr, access;
89 unsigned long flags;
90 vm_fault_t flt = 0;
91 int ret;
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102 ea = ctx->csa.class_1_dar;
103 dsisr = ctx->csa.class_1_dsisr;
104
105 if (!(dsisr & (MFC_DSISR_PTE_NOT_FOUND | MFC_DSISR_ACCESS_DENIED)))
106 return 0;
107
108 spuctx_switch_state(ctx, SPU_UTIL_IOWAIT);
109
110 pr_debug("ctx %p: ea %016llx, dsisr %016llx state %d\n", ctx, ea,
111 dsisr, ctx->state);
112
113 ctx->stats.hash_flt++;
114 if (ctx->state == SPU_STATE_RUNNABLE)
115 ctx->spu->stats.hash_flt++;
116
117
118 spu_release(ctx);
119
120 access = (_PAGE_PRESENT | _PAGE_READ);
121 access |= (dsisr & MFC_DSISR_ACCESS_PUT) ? _PAGE_WRITE : 0UL;
122 local_irq_save(flags);
123 ret = hash_page(ea, access, 0x300, dsisr);
124 local_irq_restore(flags);
125
126
127 if (ret)
128 ret = copro_handle_mm_fault(current->mm, ea, dsisr, &flt);
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134 mutex_lock(&ctx->state_mutex);
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141 ctx->csa.class_1_dar = ctx->csa.class_1_dsisr = 0;
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148 if (!ret) {
149 if (flt & VM_FAULT_MAJOR)
150 ctx->stats.maj_flt++;
151 else
152 ctx->stats.min_flt++;
153 if (ctx->state == SPU_STATE_RUNNABLE) {
154 if (flt & VM_FAULT_MAJOR)
155 ctx->spu->stats.maj_flt++;
156 else
157 ctx->spu->stats.min_flt++;
158 }
159
160 if (ctx->spu)
161 ctx->ops->restart_dma(ctx);
162 } else
163 spufs_handle_event(ctx, ea, SPE_EVENT_SPE_DATA_STORAGE);
164
165 spuctx_switch_state(ctx, SPU_UTIL_SYSTEM);
166 return ret;
167 }