root/arch/powerpc/platforms/cell/spufs/spu_restore_crt0.S

   1 /* SPDX-License-Identifier: GPL-2.0-or-later */
   2 /*
   3  * crt0_r.S: Entry function for SPU-side context restore.
   4  *
   5  * Copyright (C) 2005 IBM
   6  *
   7  * Entry and exit function for SPU-side of the context restore
   8  * sequence.  Sets up an initial stack frame, then branches to
   9  * 'main'.  On return, restores all 128 registers from the LSCSA
  10  * and exits.
  11  */
  12 
  13 #include <asm/spu_csa.h>
  14 
  15 .data
  16 .align 7
  17 .globl regs_spill
  18 regs_spill:
  19 .space SIZEOF_SPU_SPILL_REGS, 0x0
  20 
  21 .text
  22 .global _start
  23 _start:
  24         /* Initialize the stack pointer to point to 16368
  25          * (16kb-16). The back chain pointer is initialized
  26          * to NULL.
  27          */
  28         il      $0, 0
  29         il      $SP, 16368
  30         stqd    $0, 0($SP)
  31 
  32         /* Allocate a minimum stack frame for the called main.
  33          * This is needed so that main has a place to save the
  34          * link register when it calls another function.
  35          */
  36         stqd    $SP, -160($SP)
  37         ai      $SP, $SP, -160
  38 
  39         /* Call the program's main function. */
  40         brsl    $0, main
  41 
  42 .global exit
  43 .global _exit
  44 exit:
  45 _exit:
  46         /* SPU Context Restore, Step 5: Restore the remaining 112 GPRs. */
  47         ila     $3, regs_spill + 256
  48 restore_regs:
  49         lqr     $4, restore_reg_insts
  50 restore_reg_loop:
  51         ai      $4, $4, 4
  52         .balignl 16, 0x40200000
  53 restore_reg_insts:       /* must be quad-word aligned. */
  54         lqd     $16, 0($3)
  55         lqd     $17, 16($3)
  56         lqd     $18, 32($3)
  57         lqd     $19, 48($3)
  58         andi    $5, $4, 0x7F
  59         stqr    $4, restore_reg_insts
  60         ai      $3, $3, 64
  61         brnz    $5, restore_reg_loop
  62 
  63         /* SPU Context Restore Step 17: Restore the first 16 GPRs. */
  64         lqa $0, regs_spill + 0
  65         lqa $1, regs_spill + 16
  66         lqa $2, regs_spill + 32
  67         lqa $3, regs_spill + 48
  68         lqa $4, regs_spill + 64
  69         lqa $5, regs_spill + 80
  70         lqa $6, regs_spill + 96
  71         lqa $7, regs_spill + 112
  72         lqa $8, regs_spill + 128
  73         lqa $9, regs_spill + 144
  74         lqa $10, regs_spill + 160
  75         lqa $11, regs_spill + 176
  76         lqa $12, regs_spill + 192
  77         lqa $13, regs_spill + 208
  78         lqa $14, regs_spill + 224
  79         lqa $15, regs_spill + 240
  80 
  81         /* Under normal circumstances, the 'exit' function
  82          * terminates with 'stop SPU_RESTORE_COMPLETE',
  83          * indicating that the SPU-side restore code has
  84          * completed.
  85          *
  86          * However it is possible that instructions immediately
  87          * following the 'stop 0x3ffc' have been modified at run
  88          * time so as to recreate the exact SPU_Status settings
  89          * from the application, e.g. illegal instruciton, halt,
  90          * etc.
  91          */
  92 .global exit_fini
  93 .global _exit_fini
  94 exit_fini:
  95 _exit_fini:
  96         stop    SPU_RESTORE_COMPLETE
  97         stop    0
  98         stop    0
  99         stop    0
 100 
 101         /* Pad the size of this crt0.o to be multiple of 16 bytes. */
 102 .balignl 16, 0x0