arch/powerpc/platforms/86xx/gef

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This source file includes following definitions.
gef_ppc9a_init_irq
gef_ppc9a_setup_arch
gef_ppc9a_get_pcb_rev
gef_ppc9a_get_board_rev
gef_ppc9a_get_fpga_rev
gef_ppc9a_get_vme_geo_addr
gef_ppc9a_get_vme_is_syscon
gef_ppc9a_show_cpuinfo
gef_ppc9a_nec_fixup
gef_ppc9a_probe
define_machine
   1 // SPDX-License-Identifier: GPL-2.0-or-later
   2 /*
   3  * GE PPC9A board support
   4  *
   5  * Author: Martyn Welch <martyn.welch@ge.com>
   6  *
   7  * Copyright 2008 GE Intelligent Platforms Embedded Systems, Inc.
   8  *
   9  * Based on: mpc86xx_hpcn.c (MPC86xx HPCN board specific routines)
  10  * Copyright 2006 Freescale Semiconductor Inc.
  11  *
  12  * NEC fixup adapted from arch/mips/pci/fixup-lm2e.c
  13  */
  14 
  15 #include <linux/stddef.h>
  16 #include <linux/kernel.h>
  17 #include <linux/pci.h>
  18 #include <linux/kdev_t.h>
  19 #include <linux/delay.h>
  20 #include <linux/seq_file.h>
  21 #include <linux/of_platform.h>
  22 
  23 #include <asm/time.h>
  24 #include <asm/machdep.h>
  25 #include <asm/pci-bridge.h>
  26 #include <asm/prom.h>
  27 #include <mm/mmu_decl.h>
  28 #include <asm/udbg.h>
  29 
  30 #include <asm/mpic.h>
  31 #include <asm/nvram.h>
  32 
  33 #include <sysdev/fsl_pci.h>
  34 #include <sysdev/fsl_soc.h>
  35 #include <sysdev/ge/ge_pic.h>
  36 
  37 #include "mpc86xx.h"
  38 
  39 #undef DEBUG
  40 
  41 #ifdef DEBUG
  42 #define DBG (fmt...) do { printk(KERN_ERR "PPC9A: " fmt); } while (0)
  43 #else
  44 #define DBG (fmt...) do { } while (0)
  45 #endif
  46 
  47 void __iomem *ppc9a_regs;
  48 
  49 static void __init gef_ppc9a_init_irq(void)
  50 {
  51         struct device_node *cascade_node = NULL;
  52 
  53         mpc86xx_init_irq();
  54 
  55         /*
  56          * There is a simple interrupt handler in the main FPGA, this needs
  57          * to be cascaded into the MPIC
  58          */
  59         cascade_node = of_find_compatible_node(NULL, NULL, "gef,fpga-pic-1.00");
  60         if (!cascade_node) {
  61                 printk(KERN_WARNING "PPC9A: No FPGA PIC\n");
  62                 return;
  63         }
  64 
  65         gef_pic_init(cascade_node);
  66         of_node_put(cascade_node);
  67 }
  68 
  69 static void __init gef_ppc9a_setup_arch(void)
  70 {
  71         struct device_node *regs;
  72 
  73         printk(KERN_INFO "GE Intelligent Platforms PPC9A 6U VME SBC\n");
  74 
  75 #ifdef CONFIG_SMP
  76         mpc86xx_smp_init();
  77 #endif
  78 
  79         fsl_pci_assign_primary();
  80 
  81         /* Remap basic board registers */
  82         regs = of_find_compatible_node(NULL, NULL, "gef,ppc9a-fpga-regs");
  83         if (regs) {
  84                 ppc9a_regs = of_iomap(regs, 0);
  85                 if (ppc9a_regs == NULL)
  86                         printk(KERN_WARNING "Unable to map board registers\n");
  87                 of_node_put(regs);
  88         }
  89 
  90 #if defined(CONFIG_MMIO_NVRAM)
  91         mmio_nvram_init();
  92 #endif
  93 }
  94 
  95 /* Return the PCB revision */
  96 static unsigned int gef_ppc9a_get_pcb_rev(void)
  97 {
  98         unsigned int reg;
  99 
 100         reg = ioread32be(ppc9a_regs);
 101         return (reg >> 16) & 0xff;
 102 }
 103 
 104 /* Return the board (software) revision */
 105 static unsigned int gef_ppc9a_get_board_rev(void)
 106 {
 107         unsigned int reg;
 108 
 109         reg = ioread32be(ppc9a_regs);
 110         return (reg >> 8) & 0xff;
 111 }
 112 
 113 /* Return the FPGA revision */
 114 static unsigned int gef_ppc9a_get_fpga_rev(void)
 115 {
 116         unsigned int reg;
 117 
 118         reg = ioread32be(ppc9a_regs);
 119         return reg & 0xf;
 120 }
 121 
 122 /* Return VME Geographical Address */
 123 static unsigned int gef_ppc9a_get_vme_geo_addr(void)
 124 {
 125         unsigned int reg;
 126 
 127         reg = ioread32be(ppc9a_regs + 0x4);
 128         return reg & 0x1f;
 129 }
 130 
 131 /* Return VME System Controller Status */
 132 static unsigned int gef_ppc9a_get_vme_is_syscon(void)
 133 {
 134         unsigned int reg;
 135 
 136         reg = ioread32be(ppc9a_regs + 0x4);
 137         return (reg >> 9) & 0x1;
 138 }
 139 
 140 static void gef_ppc9a_show_cpuinfo(struct seq_file *m)
 141 {
 142         uint svid = mfspr(SPRN_SVR);
 143 
 144         seq_printf(m, "Vendor\t\t: GE Intelligent Platforms\n");
 145 
 146         seq_printf(m, "Revision\t: %u%c\n", gef_ppc9a_get_pcb_rev(),
 147                 ('A' + gef_ppc9a_get_board_rev()));
 148         seq_printf(m, "FPGA Revision\t: %u\n", gef_ppc9a_get_fpga_rev());
 149 
 150         seq_printf(m, "SVR\t\t: 0x%x\n", svid);
 151 
 152         seq_printf(m, "VME geo. addr\t: %u\n", gef_ppc9a_get_vme_geo_addr());
 153 
 154         seq_printf(m, "VME syscon\t: %s\n",
 155                 gef_ppc9a_get_vme_is_syscon() ? "yes" : "no");
 156 }
 157 
 158 static void gef_ppc9a_nec_fixup(struct pci_dev *pdev)
 159 {
 160         unsigned int val;
 161 
 162         /* Do not do the fixup on other platforms! */
 163         if (!machine_is(gef_ppc9a))
 164                 return;
 165 
 166         printk(KERN_INFO "Running NEC uPD720101 Fixup\n");
 167 
 168         /* Ensure ports 1, 2, 3, 4 & 5 are enabled */
 169         pci_read_config_dword(pdev, 0xe0, &val);
 170         pci_write_config_dword(pdev, 0xe0, (val & ~7) | 0x5);
 171 
 172         /* System clock is 48-MHz Oscillator and EHCI Enabled. */
 173         pci_write_config_dword(pdev, 0xe4, 1 << 5);
 174 }
 175 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NEC, PCI_DEVICE_ID_NEC_USB,
 176         gef_ppc9a_nec_fixup);
 177 
 178 /*
 179  * Called very early, device-tree isn't unflattened
 180  *
 181  * This function is called to determine whether the BSP is compatible with the
 182  * supplied device-tree, which is assumed to be the correct one for the actual
 183  * board. It is expected thati, in the future, a kernel may support multiple
 184  * boards.
 185  */
 186 static int __init gef_ppc9a_probe(void)
 187 {
 188         if (of_machine_is_compatible("gef,ppc9a"))
 189                 return 1;
 190 
 191         return 0;
 192 }
 193 
 194 machine_arch_initcall(gef_ppc9a, mpc86xx_common_publish_devices);
 195 
 196 define_machine(gef_ppc9a) {
 197         .name                   = "GE PPC9A",
 198         .probe                  = gef_ppc9a_probe,
 199         .setup_arch             = gef_ppc9a_setup_arch,
 200         .init_IRQ               = gef_ppc9a_init_irq,
 201         .show_cpuinfo           = gef_ppc9a_show_cpuinfo,
 202         .get_irq                = mpic_get_irq,
 203         .time_init              = mpc86xx_time_init,
 204         .calibrate_decr         = generic_calibrate_decr,
 205         .progress               = udbg_progress,
 206 #ifdef CONFIG_PCI
 207         .pcibios_fixup_bus      = fsl_pcibios_fixup_bus,
 208 #endif
 209 };
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root/arch/powerpc/platforms/86xx/gef_ppc9a.c

DEFINITIONS
