root/arch/powerpc/kernel/setup_64.c

DEFINITIONS

1. setup_tlb_core_data
2. check_smt_enabled
3. early_smt_enabled
4. fixup_boot_paca
5. configure_exceptions
6. cpu_ready_for_interrupts
7. record_spr_defaults
8. early_setup
9. early_setup_secondary
10. panic_smp_self_stop
11. use_spinloop
12. smp_release_cpus
13. init_cache_info
14. parse_cache_info
15. initialize_cache_info
16. ppc64_bolted_size
17. alloc_stack
18. irqstack_early_init
19. exc_lvl_early_init
20. emergency_stack_init
21. pcpu_fc_alloc
22. pcpu_fc_free
23. pcpu_cpu_distance
24. setup_per_cpu_areas
25. memory_block_size_bytes
26. hw_nmi_get_sample_period
27. disable_hardlockup_detector
28. handle_no_rfi_flush
29. handle_no_pti
30. do_nothing
31. rfi_flush_enable
32. init_fallback_flush
33. setup_rfi_flush
34. rfi_flush_set
35. rfi_flush_get
36. rfi_flush_debugfs_init

   1 // SPDX-License-Identifier: GPL-2.0-or-later
   2 /*
   3  * 
   4  * Common boot and setup code.
   5  *
   6  * Copyright (C) 2001 PPC64 Team, IBM Corp
   7  */
   8 
   9 #include <linux/export.h>
  10 #include <linux/string.h>
  11 #include <linux/sched.h>
  12 #include <linux/init.h>
  13 #include <linux/kernel.h>
  14 #include <linux/reboot.h>
  15 #include <linux/delay.h>
  16 #include <linux/initrd.h>
  17 #include <linux/seq_file.h>
  18 #include <linux/ioport.h>
  19 #include <linux/console.h>
  20 #include <linux/utsname.h>
  21 #include <linux/tty.h>
  22 #include <linux/root_dev.h>
  23 #include <linux/notifier.h>
  24 #include <linux/cpu.h>
  25 #include <linux/unistd.h>
  26 #include <linux/serial.h>
  27 #include <linux/serial_8250.h>
  28 #include <linux/memblock.h>
  29 #include <linux/pci.h>
  30 #include <linux/lockdep.h>
  31 #include <linux/memory.h>
  32 #include <linux/nmi.h>
  33 
  34 #include <asm/debugfs.h>
  35 #include <asm/io.h>
  36 #include <asm/kdump.h>
  37 #include <asm/prom.h>
  38 #include <asm/processor.h>
  39 #include <asm/pgtable.h>
  40 #include <asm/smp.h>
  41 #include <asm/elf.h>
  42 #include <asm/machdep.h>
  43 #include <asm/paca.h>
  44 #include <asm/time.h>
  45 #include <asm/cputable.h>
  46 #include <asm/dt_cpu_ftrs.h>
  47 #include <asm/sections.h>
  48 #include <asm/btext.h>
  49 #include <asm/nvram.h>
  50 #include <asm/setup.h>
  51 #include <asm/rtas.h>
  52 #include <asm/iommu.h>
  53 #include <asm/serial.h>
  54 #include <asm/cache.h>
  55 #include <asm/page.h>
  56 #include <asm/mmu.h>
  57 #include <asm/firmware.h>
  58 #include <asm/xmon.h>
  59 #include <asm/udbg.h>
  60 #include <asm/kexec.h>
  61 #include <asm/code-patching.h>
  62 #include <asm/livepatch.h>
  63 #include <asm/opal.h>
  64 #include <asm/cputhreads.h>
  65 #include <asm/hw_irq.h>
  66 #include <asm/feature-fixups.h>
  67 #include <asm/kup.h>
  68 
  69 #include "setup.h"
  70 
  71 #ifdef DEBUG
  72 #define DBG(fmt...) udbg_printf(fmt)
  73 #else
  74 #define DBG(fmt...)
  75 #endif
  76 
  77 int spinning_secondaries;
  78 u64 ppc64_pft_size;
  79 
  80 struct ppc64_caches ppc64_caches = {
  81         .l1d = {
  82                 .block_size = 0x40,
  83                 .log_block_size = 6,
  84         },
  85         .l1i = {
  86                 .block_size = 0x40,
  87                 .log_block_size = 6
  88         },
  89 };
  90 EXPORT_SYMBOL_GPL(ppc64_caches);
  91 
  92 #if defined(CONFIG_PPC_BOOK3E) && defined(CONFIG_SMP)
  93 void __init setup_tlb_core_data(void)
  94 {
  95         int cpu;
  96 
  97         BUILD_BUG_ON(offsetof(struct tlb_core_data, lock) != 0);
  98 
  99         for_each_possible_cpu(cpu) {
 100                 int first = cpu_first_thread_sibling(cpu);
 101 
 102                 /*
 103                  * If we boot via kdump on a non-primary thread,
 104                  * make sure we point at the thread that actually
 105                  * set up this TLB.
 106                  */
 107                 if (cpu_first_thread_sibling(boot_cpuid) == first)
 108                         first = boot_cpuid;
 109 
 110                 paca_ptrs[cpu]->tcd_ptr = &paca_ptrs[first]->tcd;
 111 
 112                 /*
 113                  * If we have threads, we need either tlbsrx.
 114                  * or e6500 tablewalk mode, or else TLB handlers
 115                  * will be racy and could produce duplicate entries.
 116                  * Should we panic instead?
 117                  */
 118                 WARN_ONCE(smt_enabled_at_boot >= 2 &&
 119                           !mmu_has_feature(MMU_FTR_USE_TLBRSRV) &&
 120                           book3e_htw_mode != PPC_HTW_E6500,
 121                           "%s: unsupported MMU configuration\n", __func__);
 122         }
 123 }
 124 #endif
 125 
 126 #ifdef CONFIG_SMP
 127 
 128 static char *smt_enabled_cmdline;
 129 
 130 /* Look for ibm,smt-enabled OF option */
 131 void __init check_smt_enabled(void)
 132 {
 133         struct device_node *dn;
 134         const char *smt_option;
 135 
 136         /* Default to enabling all threads */
 137         smt_enabled_at_boot = threads_per_core;
 138 
 139         /* Allow the command line to overrule the OF option */
 140         if (smt_enabled_cmdline) {
 141                 if (!strcmp(smt_enabled_cmdline, "on"))
 142                         smt_enabled_at_boot = threads_per_core;
 143                 else if (!strcmp(smt_enabled_cmdline, "off"))
 144                         smt_enabled_at_boot = 0;
 145                 else {
 146                         int smt;
 147                         int rc;
 148 
 149                         rc = kstrtoint(smt_enabled_cmdline, 10, &smt);
 150                         if (!rc)
 151                                 smt_enabled_at_boot =
 152                                         min(threads_per_core, smt);
 153                 }
 154         } else {
 155                 dn = of_find_node_by_path("/options");
 156                 if (dn) {
 157                         smt_option = of_get_property(dn, "ibm,smt-enabled",
 158                                                      NULL);
 159 
 160                         if (smt_option) {
 161                                 if (!strcmp(smt_option, "on"))
 162                                         smt_enabled_at_boot = threads_per_core;
 163                                 else if (!strcmp(smt_option, "off"))
 164                                         smt_enabled_at_boot = 0;
 165                         }
 166 
 167                         of_node_put(dn);
 168                 }
 169         }
 170 }
 171 
 172 /* Look for smt-enabled= cmdline option */
 173 static int __init early_smt_enabled(char *p)
 174 {
 175         smt_enabled_cmdline = p;
 176         return 0;
 177 }
 178 early_param("smt-enabled", early_smt_enabled);
 179 
 180 #endif /* CONFIG_SMP */
 181 
 182 /** Fix up paca fields required for the boot cpu */
 183 static void __init fixup_boot_paca(void)
 184 {
 185         /* The boot cpu is started */
 186         get_paca()->cpu_start = 1;
 187         /* Allow percpu accesses to work until we setup percpu data */
 188         get_paca()->data_offset = 0;
 189         /* Mark interrupts disabled in PACA */
 190         irq_soft_mask_set(IRQS_DISABLED);
 191 }
 192 
 193 static void __init configure_exceptions(void)
 194 {
 195         /*
 196          * Setup the trampolines from the lowmem exception vectors
 197          * to the kdump kernel when not using a relocatable kernel.
 198          */
 199         setup_kdump_trampoline();
 200 
 201         /* Under a PAPR hypervisor, we need hypercalls */
 202         if (firmware_has_feature(FW_FEATURE_SET_MODE)) {
 203                 /* Enable AIL if possible */
 204                 pseries_enable_reloc_on_exc();
 205 
 206                 /*
 207                  * Tell the hypervisor that we want our exceptions to
 208                  * be taken in little endian mode.
 209                  *
 210                  * We don't call this for big endian as our calling convention
 211                  * makes us always enter in BE, and the call may fail under
 212                  * some circumstances with kdump.
 213                  */
 214 #ifdef __LITTLE_ENDIAN__
 215                 pseries_little_endian_exceptions();
 216 #endif
 217         } else {
 218                 /* Set endian mode using OPAL */
 219                 if (firmware_has_feature(FW_FEATURE_OPAL))
 220                         opal_configure_cores();
 221 
 222                 /* AIL on native is done in cpu_ready_for_interrupts() */
 223         }
 224 }
 225 
 226 static void cpu_ready_for_interrupts(void)
 227 {
 228         /*
 229          * Enable AIL if supported, and we are in hypervisor mode. This
 230          * is called once for every processor.
 231          *
 232          * If we are not in hypervisor mode the job is done once for
 233          * the whole partition in configure_exceptions().
 234          */
 235         if (cpu_has_feature(CPU_FTR_HVMODE) &&
 236             cpu_has_feature(CPU_FTR_ARCH_207S)) {
 237                 unsigned long lpcr = mfspr(SPRN_LPCR);
 238                 mtspr(SPRN_LPCR, lpcr | LPCR_AIL_3);
 239         }
 240 
 241         /*
 242          * Set HFSCR:TM based on CPU features:
 243          * In the special case of TM no suspend (P9N DD2.1), Linux is
 244          * told TM is off via the dt-ftrs but told to (partially) use
 245          * it via OPAL_REINIT_CPUS_TM_SUSPEND_DISABLED. So HFSCR[TM]
 246          * will be off from dt-ftrs but we need to turn it on for the
 247          * no suspend case.
 248          */
 249         if (cpu_has_feature(CPU_FTR_HVMODE)) {
 250                 if (cpu_has_feature(CPU_FTR_TM_COMP))
 251                         mtspr(SPRN_HFSCR, mfspr(SPRN_HFSCR) | HFSCR_TM);
 252                 else
 253                         mtspr(SPRN_HFSCR, mfspr(SPRN_HFSCR) & ~HFSCR_TM);
 254         }
 255 
 256         /* Set IR and DR in PACA MSR */
 257         get_paca()->kernel_msr = MSR_KERNEL;
 258 }
 259 
 260 unsigned long spr_default_dscr = 0;
 261 
 262 void __init record_spr_defaults(void)
 263 {
 264         if (early_cpu_has_feature(CPU_FTR_DSCR))
 265                 spr_default_dscr = mfspr(SPRN_DSCR);
 266 }
 267 
 268 /*
 269  * Early initialization entry point. This is called by head.S
 270  * with MMU translation disabled. We rely on the "feature" of
 271  * the CPU that ignores the top 2 bits of the address in real
 272  * mode so we can access kernel globals normally provided we
 273  * only toy with things in the RMO region. From here, we do
 274  * some early parsing of the device-tree to setup out MEMBLOCK
 275  * data structures, and allocate & initialize the hash table
 276  * and segment tables so we can start running with translation
 277  * enabled.
 278  *
 279  * It is this function which will call the probe() callback of
 280  * the various platform types and copy the matching one to the
 281  * global ppc_md structure. Your platform can eventually do
 282  * some very early initializations from the probe() routine, but
 283  * this is not recommended, be very careful as, for example, the
 284  * device-tree is not accessible via normal means at this point.
 285  */
 286 
 287 void __init __nostackprotector early_setup(unsigned long dt_ptr)
 288 {
 289         static __initdata struct paca_struct boot_paca;
 290 
 291         /* -------- printk is _NOT_ safe to use here ! ------- */
 292 
 293         /*
 294          * Assume we're on cpu 0 for now.
 295          *
 296          * We need to load a PACA very early for a few reasons.
 297          *
 298          * The stack protector canary is stored in the paca, so as soon as we
 299          * call any stack protected code we need r13 pointing somewhere valid.
 300          *
 301          * If we are using kcov it will call in_task() in its instrumentation,
 302          * which relies on the current task from the PACA.
 303          *
 304          * dt_cpu_ftrs_init() calls into generic OF/fdt code, as well as
 305          * printk(), which can trigger both stack protector and kcov.
 306          *
 307          * percpu variables and spin locks also use the paca.
 308          *
 309          * So set up a temporary paca. It will be replaced below once we know
 310          * what CPU we are on.
 311          */
 312         initialise_paca(&boot_paca, 0);
 313         setup_paca(&boot_paca);
 314         fixup_boot_paca();
 315 
 316         /* -------- printk is now safe to use ------- */
 317 
 318         /* Try new device tree based feature discovery ... */
 319         if (!dt_cpu_ftrs_init(__va(dt_ptr)))
 320                 /* Otherwise use the old style CPU table */
 321                 identify_cpu(0, mfspr(SPRN_PVR));
 322 
 323         /* Enable early debugging if any specified (see udbg.h) */
 324         udbg_early_init();
 325 
 326         DBG(" -> early_setup(), dt_ptr: 0x%lx\n", dt_ptr);
 327 
 328         /*
 329          * Do early initialization using the flattened device
 330          * tree, such as retrieving the physical memory map or
 331          * calculating/retrieving the hash table size.
 332          */
 333         early_init_devtree(__va(dt_ptr));
 334 
 335         /* Now we know the logical id of our boot cpu, setup the paca. */
 336         if (boot_cpuid != 0) {
 337                 /* Poison paca_ptrs[0] again if it's not the boot cpu */
 338                 memset(&paca_ptrs[0], 0x88, sizeof(paca_ptrs[0]));
 339         }
 340         setup_paca(paca_ptrs[boot_cpuid]);
 341         fixup_boot_paca();
 342 
 343         /*
 344          * Configure exception handlers. This include setting up trampolines
 345          * if needed, setting exception endian mode, etc...
 346          */
 347         configure_exceptions();
 348 
 349         /*
 350          * Configure Kernel Userspace Protection. This needs to happen before
 351          * feature fixups for platforms that implement this using features.
 352          */
 353         setup_kup();
 354 
 355         /* Apply all the dynamic patching */
 356         apply_feature_fixups();
 357         setup_feature_keys();
 358 
 359         /* Initialize the hash table or TLB handling */
 360         early_init_mmu();
 361 
 362         /*
 363          * After firmware and early platform setup code has set things up,
 364          * we note the SPR values for configurable control/performance
 365          * registers, and use those as initial defaults.
 366          */
 367         record_spr_defaults();
 368 
 369         /*
 370          * At this point, we can let interrupts switch to virtual mode
 371          * (the MMU has been setup), so adjust the MSR in the PACA to
 372          * have IR and DR set and enable AIL if it exists
 373          */
 374         cpu_ready_for_interrupts();
 375 
 376         /*
 377          * We enable ftrace here, but since we only support DYNAMIC_FTRACE, it
 378          * will only actually get enabled on the boot cpu much later once
 379          * ftrace itself has been initialized.
 380          */
 381         this_cpu_enable_ftrace();
 382 
 383         DBG(" <- early_setup()\n");
 384 
 385 #ifdef CONFIG_PPC_EARLY_DEBUG_BOOTX
 386         /*
 387          * This needs to be done *last* (after the above DBG() even)
 388          *
 389          * Right after we return from this function, we turn on the MMU
 390          * which means the real-mode access trick that btext does will
 391          * no longer work, it needs to switch to using a real MMU
 392          * mapping. This call will ensure that it does
 393          */
 394         btext_map();
 395 #endif /* CONFIG_PPC_EARLY_DEBUG_BOOTX */
 396 }
 397 
 398 #ifdef CONFIG_SMP
 399 void early_setup_secondary(void)
 400 {
 401         /* Mark interrupts disabled in PACA */
 402         irq_soft_mask_set(IRQS_DISABLED);
 403 
 404         /* Initialize the hash table or TLB handling */
 405         early_init_mmu_secondary();
 406 
 407         /* Perform any KUP setup that is per-cpu */
 408         setup_kup();
 409 
 410         /*
 411          * At this point, we can let interrupts switch to virtual mode
 412          * (the MMU has been setup), so adjust the MSR in the PACA to
 413          * have IR and DR set.
 414          */
 415         cpu_ready_for_interrupts();
 416 }
 417 
 418 #endif /* CONFIG_SMP */
 419 
 420 void panic_smp_self_stop(void)
 421 {
 422         hard_irq_disable();
 423         spin_begin();
 424         while (1)
 425                 spin_cpu_relax();
 426 }
 427 
 428 #if defined(CONFIG_SMP) || defined(CONFIG_KEXEC_CORE)
 429 static bool use_spinloop(void)
 430 {
 431         if (IS_ENABLED(CONFIG_PPC_BOOK3S)) {
 432                 /*
 433                  * See comments in head_64.S -- not all platforms insert
 434                  * secondaries at __secondary_hold and wait at the spin
 435                  * loop.
 436                  */
 437                 if (firmware_has_feature(FW_FEATURE_OPAL))
 438                         return false;
 439                 return true;
 440         }
 441 
 442         /*
 443          * When book3e boots from kexec, the ePAPR spin table does
 444          * not get used.
 445          */
 446         return of_property_read_bool(of_chosen, "linux,booted-from-kexec");
 447 }
 448 
 449 void smp_release_cpus(void)
 450 {
 451         unsigned long *ptr;
 452         int i;
 453 
 454         if (!use_spinloop())
 455                 return;
 456 
 457         DBG(" -> smp_release_cpus()\n");
 458 
 459         /* All secondary cpus are spinning on a common spinloop, release them
 460          * all now so they can start to spin on their individual paca
 461          * spinloops. For non SMP kernels, the secondary cpus never get out
 462          * of the common spinloop.
 463          */
 464 
 465         ptr  = (unsigned long *)((unsigned long)&__secondary_hold_spinloop
 466                         - PHYSICAL_START);
 467         *ptr = ppc_function_entry(generic_secondary_smp_init);
 468 
 469         /* And wait a bit for them to catch up */
 470         for (i = 0; i < 100000; i++) {
 471                 mb();
 472                 HMT_low();
 473                 if (spinning_secondaries == 0)
 474                         break;
 475                 udelay(1);
 476         }
 477         DBG("spinning_secondaries = %d\n", spinning_secondaries);
 478 
 479         DBG(" <- smp_release_cpus()\n");
 480 }
 481 #endif /* CONFIG_SMP || CONFIG_KEXEC_CORE */
 482 
 483 /*
 484  * Initialize some remaining members of the ppc64_caches and systemcfg
 485  * structures
 486  * (at least until we get rid of them completely). This is mostly some
 487  * cache informations about the CPU that will be used by cache flush
 488  * routines and/or provided to userland
 489  */
 490 
 491 static void init_cache_info(struct ppc_cache_info *info, u32 size, u32 lsize,
 492                             u32 bsize, u32 sets)
 493 {
 494         info->size = size;
 495         info->sets = sets;
 496         info->line_size = lsize;
 497         info->block_size = bsize;
 498         info->log_block_size = __ilog2(bsize);
 499         if (bsize)
 500                 info->blocks_per_page = PAGE_SIZE / bsize;
 501         else
 502                 info->blocks_per_page = 0;
 503 
 504         if (sets == 0)
 505                 info->assoc = 0xffff;
 506         else
 507                 info->assoc = size / (sets * lsize);
 508 }
 509 
 510 static bool __init parse_cache_info(struct device_node *np,
 511                                     bool icache,
 512                                     struct ppc_cache_info *info)
 513 {
 514         static const char *ipropnames[] __initdata = {
 515                 "i-cache-size",
 516                 "i-cache-sets",
 517                 "i-cache-block-size",
 518                 "i-cache-line-size",
 519         };
 520         static const char *dpropnames[] __initdata = {
 521                 "d-cache-size",
 522                 "d-cache-sets",
 523                 "d-cache-block-size",
 524                 "d-cache-line-size",
 525         };
 526         const char **propnames = icache ? ipropnames : dpropnames;
 527         const __be32 *sizep, *lsizep, *bsizep, *setsp;
 528         u32 size, lsize, bsize, sets;
 529         bool success = true;
 530 
 531         size = 0;
 532         sets = -1u;
 533         lsize = bsize = cur_cpu_spec->dcache_bsize;
 534         sizep = of_get_property(np, propnames[0], NULL);
 535         if (sizep != NULL)
 536                 size = be32_to_cpu(*sizep);
 537         setsp = of_get_property(np, propnames[1], NULL);
 538         if (setsp != NULL)
 539                 sets = be32_to_cpu(*setsp);
 540         bsizep = of_get_property(np, propnames[2], NULL);
 541         lsizep = of_get_property(np, propnames[3], NULL);
 542         if (bsizep == NULL)
 543                 bsizep = lsizep;
 544         if (lsizep == NULL)
 545                 lsizep = bsizep;
 546         if (lsizep != NULL)
 547                 lsize = be32_to_cpu(*lsizep);
 548         if (bsizep != NULL)
 549                 bsize = be32_to_cpu(*bsizep);
 550         if (sizep == NULL || bsizep == NULL || lsizep == NULL)
 551                 success = false;
 552 
 553         /*
 554          * OF is weird .. it represents fully associative caches
 555          * as "1 way" which doesn't make much sense and doesn't
 556          * leave room for direct mapped. We'll assume that 0
 557          * in OF means direct mapped for that reason.
 558          */
 559         if (sets == 1)
 560                 sets = 0;
 561         else if (sets == 0)
 562                 sets = 1;
 563 
 564         init_cache_info(info, size, lsize, bsize, sets);
 565 
 566         return success;
 567 }
 568 
 569 void __init initialize_cache_info(void)
 570 {
 571         struct device_node *cpu = NULL, *l2, *l3 = NULL;
 572         u32 pvr;
 573 
 574         DBG(" -> initialize_cache_info()\n");
 575 
 576         /*
 577          * All shipping POWER8 machines have a firmware bug that
 578          * puts incorrect information in the device-tree. This will
 579          * be (hopefully) fixed for future chips but for now hard
 580          * code the values if we are running on one of these
 581          */
 582         pvr = PVR_VER(mfspr(SPRN_PVR));
 583         if (pvr == PVR_POWER8 || pvr == PVR_POWER8E ||
 584             pvr == PVR_POWER8NVL) {
 585                                                 /* size    lsize   blk  sets */
 586                 init_cache_info(&ppc64_caches.l1i, 0x8000,   128,  128, 32);
 587                 init_cache_info(&ppc64_caches.l1d, 0x10000,  128,  128, 64);
 588                 init_cache_info(&ppc64_caches.l2,  0x80000,  128,  0,   512);
 589                 init_cache_info(&ppc64_caches.l3,  0x800000, 128,  0,   8192);
 590         } else
 591                 cpu = of_find_node_by_type(NULL, "cpu");
 592 
 593         /*
 594          * We're assuming *all* of the CPUs have the same
 595          * d-cache and i-cache sizes... -Peter
 596          */
 597         if (cpu) {
 598                 if (!parse_cache_info(cpu, false, &ppc64_caches.l1d))
 599                         DBG("Argh, can't find dcache properties !\n");
 600 
 601                 if (!parse_cache_info(cpu, true, &ppc64_caches.l1i))
 602                         DBG("Argh, can't find icache properties !\n");
 603 
 604                 /*
 605                  * Try to find the L2 and L3 if any. Assume they are
 606                  * unified and use the D-side properties.
 607                  */
 608                 l2 = of_find_next_cache_node(cpu);
 609                 of_node_put(cpu);
 610                 if (l2) {
 611                         parse_cache_info(l2, false, &ppc64_caches.l2);
 612                         l3 = of_find_next_cache_node(l2);
 613                         of_node_put(l2);
 614                 }
 615                 if (l3) {
 616                         parse_cache_info(l3, false, &ppc64_caches.l3);
 617                         of_node_put(l3);
 618                 }
 619         }
 620 
 621         /* For use by binfmt_elf */
 622         dcache_bsize = ppc64_caches.l1d.block_size;
 623         icache_bsize = ppc64_caches.l1i.block_size;
 624 
 625         cur_cpu_spec->dcache_bsize = dcache_bsize;
 626         cur_cpu_spec->icache_bsize = icache_bsize;
 627 
 628         DBG(" <- initialize_cache_info()\n");
 629 }
 630 
 631 /*
 632  * This returns the limit below which memory accesses to the linear
 633  * mapping are guarnateed not to cause an architectural exception (e.g.,
 634  * TLB or SLB miss fault).
 635  *
 636  * This is used to allocate PACAs and various interrupt stacks that
 637  * that are accessed early in interrupt handlers that must not cause
 638  * re-entrant interrupts.
 639  */
 640 __init u64 ppc64_bolted_size(void)
 641 {
 642 #ifdef CONFIG_PPC_BOOK3E
 643         /* Freescale BookE bolts the entire linear mapping */
 644         /* XXX: BookE ppc64_rma_limit setup seems to disagree? */
 645         if (early_mmu_has_feature(MMU_FTR_TYPE_FSL_E))
 646                 return linear_map_top;
 647         /* Other BookE, we assume the first GB is bolted */
 648         return 1ul << 30;
 649 #else
 650         /* BookS radix, does not take faults on linear mapping */
 651         if (early_radix_enabled())
 652                 return ULONG_MAX;
 653 
 654         /* BookS hash, the first segment is bolted */
 655         if (early_mmu_has_feature(MMU_FTR_1T_SEGMENT))
 656                 return 1UL << SID_SHIFT_1T;
 657         return 1UL << SID_SHIFT;
 658 #endif
 659 }
 660 
 661 static void *__init alloc_stack(unsigned long limit, int cpu)
 662 {
 663         void *ptr;
 664 
 665         BUILD_BUG_ON(STACK_INT_FRAME_SIZE % 16);
 666 
 667         ptr = memblock_alloc_try_nid(THREAD_SIZE, THREAD_SIZE,
 668                                      MEMBLOCK_LOW_LIMIT, limit,
 669                                      early_cpu_to_node(cpu));
 670         if (!ptr)
 671                 panic("cannot allocate stacks");
 672 
 673         return ptr;
 674 }
 675 
 676 void __init irqstack_early_init(void)
 677 {
 678         u64 limit = ppc64_bolted_size();
 679         unsigned int i;
 680 
 681         /*
 682          * Interrupt stacks must be in the first segment since we
 683          * cannot afford to take SLB misses on them. They are not
 684          * accessed in realmode.
 685          */
 686         for_each_possible_cpu(i) {
 687                 softirq_ctx[i] = alloc_stack(limit, i);
 688                 hardirq_ctx[i] = alloc_stack(limit, i);
 689         }
 690 }
 691 
 692 #ifdef CONFIG_PPC_BOOK3E
 693 void __init exc_lvl_early_init(void)
 694 {
 695         unsigned int i;
 696 
 697         for_each_possible_cpu(i) {
 698                 void *sp;
 699 
 700                 sp = alloc_stack(ULONG_MAX, i);
 701                 critirq_ctx[i] = sp;
 702                 paca_ptrs[i]->crit_kstack = sp + THREAD_SIZE;
 703 
 704                 sp = alloc_stack(ULONG_MAX, i);
 705                 dbgirq_ctx[i] = sp;
 706                 paca_ptrs[i]->dbg_kstack = sp + THREAD_SIZE;
 707 
 708                 sp = alloc_stack(ULONG_MAX, i);
 709                 mcheckirq_ctx[i] = sp;
 710                 paca_ptrs[i]->mc_kstack = sp + THREAD_SIZE;
 711         }
 712 
 713         if (cpu_has_feature(CPU_FTR_DEBUG_LVL_EXC))
 714                 patch_exception(0x040, exc_debug_debug_book3e);
 715 }
 716 #endif
 717 
 718 /*
 719  * Stack space used when we detect a bad kernel stack pointer, and
 720  * early in SMP boots before relocation is enabled. Exclusive emergency
 721  * stack for machine checks.
 722  */
 723 void __init emergency_stack_init(void)
 724 {
 725         u64 limit;
 726         unsigned int i;
 727 
 728         /*
 729          * Emergency stacks must be under 256MB, we cannot afford to take
 730          * SLB misses on them. The ABI also requires them to be 128-byte
 731          * aligned.
 732          *
 733          * Since we use these as temporary stacks during secondary CPU
 734          * bringup, machine check, system reset, and HMI, we need to get
 735          * at them in real mode. This means they must also be within the RMO
 736          * region.
 737          *
 738          * The IRQ stacks allocated elsewhere in this file are zeroed and
 739          * initialized in kernel/irq.c. These are initialized here in order
 740          * to have emergency stacks available as early as possible.
 741          */
 742         limit = min(ppc64_bolted_size(), ppc64_rma_size);
 743 
 744         for_each_possible_cpu(i) {
 745                 paca_ptrs[i]->emergency_sp = alloc_stack(limit, i) + THREAD_SIZE;
 746 
 747 #ifdef CONFIG_PPC_BOOK3S_64
 748                 /* emergency stack for NMI exception handling. */
 749                 paca_ptrs[i]->nmi_emergency_sp = alloc_stack(limit, i) + THREAD_SIZE;
 750 
 751                 /* emergency stack for machine check exception handling. */
 752                 paca_ptrs[i]->mc_emergency_sp = alloc_stack(limit, i) + THREAD_SIZE;
 753 #endif
 754         }
 755 }
 756 
 757 #ifdef CONFIG_SMP
 758 #define PCPU_DYN_SIZE           ()
 759 
 760 static void * __init pcpu_fc_alloc(unsigned int cpu, size_t size, size_t align)
 761 {
 762         return memblock_alloc_try_nid(size, align, __pa(MAX_DMA_ADDRESS),
 763                                       MEMBLOCK_ALLOC_ACCESSIBLE,
 764                                       early_cpu_to_node(cpu));
 765 
 766 }
 767 
 768 static void __init pcpu_fc_free(void *ptr, size_t size)
 769 {
 770         memblock_free(__pa(ptr), size);
 771 }
 772 
 773 static int pcpu_cpu_distance(unsigned int from, unsigned int to)
 774 {
 775         if (early_cpu_to_node(from) == early_cpu_to_node(to))
 776                 return LOCAL_DISTANCE;
 777         else
 778                 return REMOTE_DISTANCE;
 779 }
 780 
 781 unsigned long __per_cpu_offset[NR_CPUS] __read_mostly;
 782 EXPORT_SYMBOL(__per_cpu_offset);
 783 
 784 void __init setup_per_cpu_areas(void)
 785 {
 786         const size_t dyn_size = PERCPU_MODULE_RESERVE + PERCPU_DYNAMIC_RESERVE;
 787         size_t atom_size;
 788         unsigned long delta;
 789         unsigned int cpu;
 790         int rc;
 791 
 792         /*
 793          * Linear mapping is one of 4K, 1M and 16M.  For 4K, no need
 794          * to group units.  For larger mappings, use 1M atom which
 795          * should be large enough to contain a number of units.
 796          */
 797         if (mmu_linear_psize == MMU_PAGE_4K)
 798                 atom_size = PAGE_SIZE;
 799         else
 800                 atom_size = 1 << 20;
 801 
 802         rc = pcpu_embed_first_chunk(0, dyn_size, atom_size, pcpu_cpu_distance,
 803                                     pcpu_fc_alloc, pcpu_fc_free);
 804         if (rc < 0)
 805                 panic("cannot initialize percpu area (err=%d)", rc);
 806 
 807         delta = (unsigned long)pcpu_base_addr - (unsigned long)__per_cpu_start;
 808         for_each_possible_cpu(cpu) {
 809                 __per_cpu_offset[cpu] = delta + pcpu_unit_offsets[cpu];
 810                 paca_ptrs[cpu]->data_offset = __per_cpu_offset[cpu];
 811         }
 812 }
 813 #endif
 814 
 815 #ifdef CONFIG_MEMORY_HOTPLUG_SPARSE
 816 unsigned long memory_block_size_bytes(void)
 817 {
 818         if (ppc_md.memory_block_size)
 819                 return ppc_md.memory_block_size();
 820 
 821         return MIN_MEMORY_BLOCK_SIZE;
 822 }
 823 #endif
 824 
 825 #if defined(CONFIG_PPC_INDIRECT_PIO) || defined(CONFIG_PPC_INDIRECT_MMIO)
 826 struct ppc_pci_io ppc_pci_io;
 827 EXPORT_SYMBOL(ppc_pci_io);
 828 #endif
 829 
 830 #ifdef CONFIG_HARDLOCKUP_DETECTOR_PERF
 831 u64 hw_nmi_get_sample_period(int watchdog_thresh)
 832 {
 833         return ppc_proc_freq * watchdog_thresh;
 834 }
 835 #endif
 836 
 837 /*
 838  * The perf based hardlockup detector breaks PMU event based branches, so
 839  * disable it by default. Book3S has a soft-nmi hardlockup detector based
 840  * on the decrementer interrupt, so it does not suffer from this problem.
 841  *
 842  * It is likely to get false positives in VM guests, so disable it there
 843  * by default too.
 844  */
 845 static int __init disable_hardlockup_detector(void)
 846 {
 847 #ifdef CONFIG_HARDLOCKUP_DETECTOR_PERF
 848         hardlockup_detector_disable();
 849 #else
 850         if (firmware_has_feature(FW_FEATURE_LPAR))
 851                 hardlockup_detector_disable();
 852 #endif
 853 
 854         return 0;
 855 }
 856 early_initcall(disable_hardlockup_detector);
 857 
 858 #ifdef CONFIG_PPC_BOOK3S_64
 859 static enum l1d_flush_type enabled_flush_types;
 860 static void *l1d_flush_fallback_area;
 861 static bool no_rfi_flush;
 862 bool rfi_flush;
 863 
 864 static int __init handle_no_rfi_flush(char *p)
 865 {
 866         pr_info("rfi-flush: disabled on command line.");
 867         no_rfi_flush = true;
 868         return 0;
 869 }
 870 early_param("no_rfi_flush", handle_no_rfi_flush);
 871 
 872 /*
 873  * The RFI flush is not KPTI, but because users will see doco that says to use
 874  * nopti we hijack that option here to also disable the RFI flush.
 875  */
 876 static int __init handle_no_pti(char *p)
 877 {
 878         pr_info("rfi-flush: disabling due to 'nopti' on command line.\n");
 879         handle_no_rfi_flush(NULL);
 880         return 0;
 881 }
 882 early_param("nopti", handle_no_pti);
 883 
 884 static void do_nothing(void *unused)
 885 {
 886         /*
 887          * We don't need to do the flush explicitly, just enter+exit kernel is
 888          * sufficient, the RFI exit handlers will do the right thing.
 889          */
 890 }
 891 
 892 void rfi_flush_enable(bool enable)
 893 {
 894         if (enable) {
 895                 do_rfi_flush_fixups(enabled_flush_types);
 896                 on_each_cpu(do_nothing, NULL, 1);
 897         } else
 898                 do_rfi_flush_fixups(L1D_FLUSH_NONE);
 899 
 900         rfi_flush = enable;
 901 }
 902 
 903 static void __ref init_fallback_flush(void)
 904 {
 905         u64 l1d_size, limit;
 906         int cpu;
 907 
 908         /* Only allocate the fallback flush area once (at boot time). */
 909         if (l1d_flush_fallback_area)
 910                 return;
 911 
 912         l1d_size = ppc64_caches.l1d.size;
 913 
 914         /*
 915          * If there is no d-cache-size property in the device tree, l1d_size
 916          * could be zero. That leads to the loop in the asm wrapping around to
 917          * 2^64-1, and then walking off the end of the fallback area and
 918          * eventually causing a page fault which is fatal. Just default to
 919          * something vaguely sane.
 920          */
 921         if (!l1d_size)
 922                 l1d_size = (64 * 1024);
 923 
 924         limit = min(ppc64_bolted_size(), ppc64_rma_size);
 925 
 926         /*
 927          * Align to L1d size, and size it at 2x L1d size, to catch possible
 928          * hardware prefetch runoff. We don't have a recipe for load patterns to
 929          * reliably avoid the prefetcher.
 930          */
 931         l1d_flush_fallback_area = memblock_alloc_try_nid(l1d_size * 2,
 932                                                 l1d_size, MEMBLOCK_LOW_LIMIT,
 933                                                 limit, NUMA_NO_NODE);
 934         if (!l1d_flush_fallback_area)
 935                 panic("%s: Failed to allocate %llu bytes align=0x%llx max_addr=%pa\n",
 936                       __func__, l1d_size * 2, l1d_size, &limit);
 937 
 938 
 939         for_each_possible_cpu(cpu) {
 940                 struct paca_struct *paca = paca_ptrs[cpu];
 941                 paca->rfi_flush_fallback_area = l1d_flush_fallback_area;
 942                 paca->l1d_flush_size = l1d_size;
 943         }
 944 }
 945 
 946 void setup_rfi_flush(enum l1d_flush_type types, bool enable)
 947 {
 948         if (types & L1D_FLUSH_FALLBACK) {
 949                 pr_info("rfi-flush: fallback displacement flush available\n");
 950                 init_fallback_flush();
 951         }
 952 
 953         if (types & L1D_FLUSH_ORI)
 954                 pr_info("rfi-flush: ori type flush available\n");
 955 
 956         if (types & L1D_FLUSH_MTTRIG)
 957                 pr_info("rfi-flush: mttrig type flush available\n");
 958 
 959         enabled_flush_types = types;
 960 
 961         if (!no_rfi_flush && !cpu_mitigations_off())
 962                 rfi_flush_enable(enable);
 963 }
 964 
 965 #ifdef CONFIG_DEBUG_FS
 966 static int rfi_flush_set(void *data, u64 val)
 967 {
 968         bool enable;
 969 
 970         if (val == 1)
 971                 enable = true;
 972         else if (val == 0)
 973                 enable = false;
 974         else
 975                 return -EINVAL;
 976 
 977         /* Only do anything if we're changing state */
 978         if (enable != rfi_flush)
 979                 rfi_flush_enable(enable);
 980 
 981         return 0;
 982 }
 983 
 984 static int rfi_flush_get(void *data, u64 *val)
 985 {
 986         *val = rfi_flush ? 1 : 0;
 987         return 0;
 988 }
 989 
 990 DEFINE_SIMPLE_ATTRIBUTE(fops_rfi_flush, rfi_flush_get, rfi_flush_set, "%llu\n");
 991 
 992 static __init int rfi_flush_debugfs_init(void)
 993 {
 994         debugfs_create_file("rfi_flush", 0600, powerpc_debugfs_root, NULL, &fops_rfi_flush);
 995         return 0;
 996 }
 997 device_initcall(rfi_flush_debugfs_init);
 998 #endif
 999 #endif /* CONFIG_PPC_BOOK3S_64 */