root/arch/powerpc/kernel/vdso64/sigtramp.S

   1 /* SPDX-License-Identifier: GPL-2.0-or-later */
   2 /*
   3  * Signal trampoline for 64 bits processes in a ppc64 kernel for
   4  * use in the vDSO
   5  *
   6  * Copyright (C) 2004 Benjamin Herrenschmuidt (benh@kernel.crashing.org), IBM Corp.
   7  * Copyright (C) 2004 Alan Modra (amodra@au.ibm.com)), IBM Corp.
   8  */
   9 #include <asm/processor.h>
  10 #include <asm/ppc_asm.h>
  11 #include <asm/unistd.h>
  12 #include <asm/vdso.h>
  13 #include <asm/ptrace.h>         /* XXX for __SIGNAL_FRAMESIZE */
  14 
  15         .text
  16 
  17 /* The nop here is a hack.  The dwarf2 unwind routines subtract 1 from
  18    the return address to get an address in the middle of the presumed
  19    call instruction.  Since we don't have a call here, we artificially
  20    extend the range covered by the unwind info by padding before the
  21    real start.  */
  22         nop
  23         .balign 8
  24 V_FUNCTION_BEGIN(__kernel_sigtramp_rt64)
  25 .Lsigrt_start = . - 4
  26         addi    r1, r1, __SIGNAL_FRAMESIZE
  27         li      r0,__NR_rt_sigreturn
  28         sc
  29 .Lsigrt_end:
  30 V_FUNCTION_END(__kernel_sigtramp_rt64)
  31 /* The ".balign 8" above and the following zeros mimic the old stack
  32    trampoline layout.  The last magic value is the ucontext pointer,
  33    chosen in such a way that older libgcc unwind code returns a zero
  34    for a sigcontext pointer.  */
  35         .long 0,0,0
  36         .quad 0,-21*8
  37 
  38 /* Register r1 can be found at offset 8 of a pt_regs structure.
  39    A pointer to the pt_regs is stored in memory at the old sp plus PTREGS.  */
  40 #define cfa_save \
  41   .byte 0x0f;                   /* DW_CFA_def_cfa_expression */         \
  42   .uleb128 9f - 1f;             /*   length */                          \
  43 1:                                                                      \
  44   .byte 0x71; .sleb128 PTREGS;  /*     DW_OP_breg1 */                   \
  45   .byte 0x06;                   /*     DW_OP_deref */                   \
  46   .byte 0x23; .uleb128 RSIZE;   /*     DW_OP_plus_uconst */             \
  47   .byte 0x06;                   /*     DW_OP_deref */                   \
  48 9:
  49 
  50 /* Register REGNO can be found at offset OFS of a pt_regs structure.
  51    A pointer to the pt_regs is stored in memory at the old sp plus PTREGS.  */
  52 #define rsave(regno, ofs) \
  53   .byte 0x10;                   /* DW_CFA_expression */                 \
  54   .uleb128 regno;               /*   regno */                           \
  55   .uleb128 9f - 1f;             /*   length */                          \
  56 1:                                                                      \
  57   .byte 0x71; .sleb128 PTREGS;  /*     DW_OP_breg1 */                   \
  58   .byte 0x06;                   /*     DW_OP_deref */                   \
  59   .ifne ofs;                                                            \
  60     .byte 0x23; .uleb128 ofs;   /*     DW_OP_plus_uconst */             \
  61   .endif;                                                               \
  62 9:
  63 
  64 /* If msr bit 1<<25 is set, then VMX register REGNO is at offset REGNO*16
  65    of the VMX reg struct.  A pointer to the VMX reg struct is at VREGS in
  66    the pt_regs struct.  This macro is for REGNO == 0, and contains
  67    'subroutines' that the other macros jump to.  */
  68 #define vsave_msr0(regno) \
  69   .byte 0x10;                   /* DW_CFA_expression */                 \
  70   .uleb128 regno + 77;          /*   regno */                           \
  71   .uleb128 9f - 1f;             /*   length */                          \
  72 1:                                                                      \
  73   .byte 0x30 + regno;           /*     DW_OP_lit0 */                    \
  74 2:                                                                      \
  75   .byte 0x40;                   /*     DW_OP_lit16 */                   \
  76   .byte 0x1e;                   /*     DW_OP_mul */                     \
  77 3:                                                                      \
  78   .byte 0x71; .sleb128 PTREGS;  /*     DW_OP_breg1 */                   \
  79   .byte 0x06;                   /*     DW_OP_deref */                   \
  80   .byte 0x12;                   /*     DW_OP_dup */                     \
  81   .byte 0x23;                   /*     DW_OP_plus_uconst */             \
  82     .uleb128 33*RSIZE;          /*       msr offset */                  \
  83   .byte 0x06;                   /*     DW_OP_deref */                   \
  84   .byte 0x0c; .long 1 << 25;    /*     DW_OP_const4u */                 \
  85   .byte 0x1a;                   /*     DW_OP_and */                     \
  86   .byte 0x12;                   /*     DW_OP_dup, ret 0 if bra taken */ \
  87   .byte 0x30;                   /*     DW_OP_lit0 */                    \
  88   .byte 0x29;                   /*     DW_OP_eq */                      \
  89   .byte 0x28; .short 0x7fff;    /*     DW_OP_bra to end */              \
  90   .byte 0x13;                   /*     DW_OP_drop, pop the 0 */         \
  91   .byte 0x23; .uleb128 VREGS;   /*     DW_OP_plus_uconst */             \
  92   .byte 0x06;                   /*     DW_OP_deref */                   \
  93   .byte 0x22;                   /*     DW_OP_plus */                    \
  94   .byte 0x2f; .short 0x7fff;    /*     DW_OP_skip to end */             \
  95 9:
  96 
  97 /* If msr bit 1<<25 is set, then VMX register REGNO is at offset REGNO*16
  98    of the VMX reg struct.  REGNO is 1 thru 31.  */
  99 #define vsave_msr1(regno) \
 100   .byte 0x10;                   /* DW_CFA_expression */                 \
 101   .uleb128 regno + 77;          /*   regno */                           \
 102   .uleb128 9f - 1f;             /*   length */                          \
 103 1:                                                                      \
 104   .byte 0x30 + regno;           /*     DW_OP_lit n */                   \
 105   .byte 0x2f; .short 2b - 9f;   /*     DW_OP_skip */                    \
 106 9:
 107 
 108 /* If msr bit 1<<25 is set, then VMX register REGNO is at offset OFS of
 109    the VMX save block.  */
 110 #define vsave_msr2(regno, ofs) \
 111   .byte 0x10;                   /* DW_CFA_expression */                 \
 112   .uleb128 regno + 77;          /*   regno */                           \
 113   .uleb128 9f - 1f;             /*   length */                          \
 114 1:                                                                      \
 115   .byte 0x0a; .short ofs;       /*     DW_OP_const2u */                 \
 116   .byte 0x2f; .short 3b - 9f;   /*     DW_OP_skip */                    \
 117 9:
 118 
 119 /* VMX register REGNO is at offset OFS of the VMX save area.  */
 120 #define vsave(regno, ofs) \
 121   .byte 0x10;                   /* DW_CFA_expression */                 \
 122   .uleb128 regno + 77;          /*   regno */                           \
 123   .uleb128 9f - 1f;             /*   length */                          \
 124 1:                                                                      \
 125   .byte 0x71; .sleb128 PTREGS;  /*     DW_OP_breg1 */                   \
 126   .byte 0x06;                   /*     DW_OP_deref */                   \
 127   .byte 0x23; .uleb128 VREGS;   /*     DW_OP_plus_uconst */             \
 128   .byte 0x06;                   /*     DW_OP_deref */                   \
 129   .byte 0x23; .uleb128 ofs;     /*     DW_OP_plus_uconst */             \
 130 9:
 131 
 132 /* This is where the pt_regs pointer can be found on the stack.  */
 133 #define PTREGS  128+168+56
 134 
 135 /* Size of regs.  */
 136 #define RSIZE   8
 137 
 138 /* Size of CR reg in DWARF unwind info. */
 139 #define CRSIZE  4
 140 
 141 /* Offset of CR reg within a full word. */
 142 #ifdef __LITTLE_ENDIAN__
 143 #define CROFF 0
 144 #else
 145 #define CROFF (RSIZE - CRSIZE)
 146 #endif
 147 
 148 /* This is the offset of the VMX reg pointer.  */
 149 #define VREGS   48*RSIZE+33*8
 150 
 151 /* Describe where general purpose regs are saved.  */
 152 #define EH_FRAME_GEN \
 153   cfa_save;                                                             \
 154   rsave ( 0,  0*RSIZE);                                                 \
 155   rsave ( 2,  2*RSIZE);                                                 \
 156   rsave ( 3,  3*RSIZE);                                                 \
 157   rsave ( 4,  4*RSIZE);                                                 \
 158   rsave ( 5,  5*RSIZE);                                                 \
 159   rsave ( 6,  6*RSIZE);                                                 \
 160   rsave ( 7,  7*RSIZE);                                                 \
 161   rsave ( 8,  8*RSIZE);                                                 \
 162   rsave ( 9,  9*RSIZE);                                                 \
 163   rsave (10, 10*RSIZE);                                                 \
 164   rsave (11, 11*RSIZE);                                                 \
 165   rsave (12, 12*RSIZE);                                                 \
 166   rsave (13, 13*RSIZE);                                                 \
 167   rsave (14, 14*RSIZE);                                                 \
 168   rsave (15, 15*RSIZE);                                                 \
 169   rsave (16, 16*RSIZE);                                                 \
 170   rsave (17, 17*RSIZE);                                                 \
 171   rsave (18, 18*RSIZE);                                                 \
 172   rsave (19, 19*RSIZE);                                                 \
 173   rsave (20, 20*RSIZE);                                                 \
 174   rsave (21, 21*RSIZE);                                                 \
 175   rsave (22, 22*RSIZE);                                                 \
 176   rsave (23, 23*RSIZE);                                                 \
 177   rsave (24, 24*RSIZE);                                                 \
 178   rsave (25, 25*RSIZE);                                                 \
 179   rsave (26, 26*RSIZE);                                                 \
 180   rsave (27, 27*RSIZE);                                                 \
 181   rsave (28, 28*RSIZE);                                                 \
 182   rsave (29, 29*RSIZE);                                                 \
 183   rsave (30, 30*RSIZE);                                                 \
 184   rsave (31, 31*RSIZE);                                                 \
 185   rsave (67, 32*RSIZE);         /* ap, used as temp for nip */          \
 186   rsave (65, 36*RSIZE);         /* lr */                                \
 187   rsave (68, 38*RSIZE + CROFF); /* cr fields */                         \
 188   rsave (69, 38*RSIZE + CROFF);                                         \
 189   rsave (70, 38*RSIZE + CROFF);                                         \
 190   rsave (71, 38*RSIZE + CROFF);                                         \
 191   rsave (72, 38*RSIZE + CROFF);                                         \
 192   rsave (73, 38*RSIZE + CROFF);                                         \
 193   rsave (74, 38*RSIZE + CROFF);                                         \
 194   rsave (75, 38*RSIZE + CROFF)
 195 
 196 /* Describe where the FP regs are saved.  */
 197 #define EH_FRAME_FP \
 198   rsave (32, 48*RSIZE +  0*8);                                          \
 199   rsave (33, 48*RSIZE +  1*8);                                          \
 200   rsave (34, 48*RSIZE +  2*8);                                          \
 201   rsave (35, 48*RSIZE +  3*8);                                          \
 202   rsave (36, 48*RSIZE +  4*8);                                          \
 203   rsave (37, 48*RSIZE +  5*8);                                          \
 204   rsave (38, 48*RSIZE +  6*8);                                          \
 205   rsave (39, 48*RSIZE +  7*8);                                          \
 206   rsave (40, 48*RSIZE +  8*8);                                          \
 207   rsave (41, 48*RSIZE +  9*8);                                          \
 208   rsave (42, 48*RSIZE + 10*8);                                          \
 209   rsave (43, 48*RSIZE + 11*8);                                          \
 210   rsave (44, 48*RSIZE + 12*8);                                          \
 211   rsave (45, 48*RSIZE + 13*8);                                          \
 212   rsave (46, 48*RSIZE + 14*8);                                          \
 213   rsave (47, 48*RSIZE + 15*8);                                          \
 214   rsave (48, 48*RSIZE + 16*8);                                          \
 215   rsave (49, 48*RSIZE + 17*8);                                          \
 216   rsave (50, 48*RSIZE + 18*8);                                          \
 217   rsave (51, 48*RSIZE + 19*8);                                          \
 218   rsave (52, 48*RSIZE + 20*8);                                          \
 219   rsave (53, 48*RSIZE + 21*8);                                          \
 220   rsave (54, 48*RSIZE + 22*8);                                          \
 221   rsave (55, 48*RSIZE + 23*8);                                          \
 222   rsave (56, 48*RSIZE + 24*8);                                          \
 223   rsave (57, 48*RSIZE + 25*8);                                          \
 224   rsave (58, 48*RSIZE + 26*8);                                          \
 225   rsave (59, 48*RSIZE + 27*8);                                          \
 226   rsave (60, 48*RSIZE + 28*8);                                          \
 227   rsave (61, 48*RSIZE + 29*8);                                          \
 228   rsave (62, 48*RSIZE + 30*8);                                          \
 229   rsave (63, 48*RSIZE + 31*8)
 230 
 231 /* Describe where the VMX regs are saved.  */
 232 #ifdef CONFIG_ALTIVEC
 233 #define EH_FRAME_VMX \
 234   vsave_msr0 ( 0);                                                      \
 235   vsave_msr1 ( 1);                                                      \
 236   vsave_msr1 ( 2);                                                      \
 237   vsave_msr1 ( 3);                                                      \
 238   vsave_msr1 ( 4);                                                      \
 239   vsave_msr1 ( 5);                                                      \
 240   vsave_msr1 ( 6);                                                      \
 241   vsave_msr1 ( 7);                                                      \
 242   vsave_msr1 ( 8);                                                      \
 243   vsave_msr1 ( 9);                                                      \
 244   vsave_msr1 (10);                                                      \
 245   vsave_msr1 (11);                                                      \
 246   vsave_msr1 (12);                                                      \
 247   vsave_msr1 (13);                                                      \
 248   vsave_msr1 (14);                                                      \
 249   vsave_msr1 (15);                                                      \
 250   vsave_msr1 (16);                                                      \
 251   vsave_msr1 (17);                                                      \
 252   vsave_msr1 (18);                                                      \
 253   vsave_msr1 (19);                                                      \
 254   vsave_msr1 (20);                                                      \
 255   vsave_msr1 (21);                                                      \
 256   vsave_msr1 (22);                                                      \
 257   vsave_msr1 (23);                                                      \
 258   vsave_msr1 (24);                                                      \
 259   vsave_msr1 (25);                                                      \
 260   vsave_msr1 (26);                                                      \
 261   vsave_msr1 (27);                                                      \
 262   vsave_msr1 (28);                                                      \
 263   vsave_msr1 (29);                                                      \
 264   vsave_msr1 (30);                                                      \
 265   vsave_msr1 (31);                                                      \
 266   vsave_msr2 (33, 32*16+12);                                            \
 267   vsave      (32, 33*16)
 268 #else
 269 #define EH_FRAME_VMX
 270 #endif
 271 
 272         .section .eh_frame,"a",@progbits
 273 .Lcie:
 274         .long .Lcie_end - .Lcie_start
 275 .Lcie_start:
 276         .long 0                 /* CIE ID */
 277         .byte 1                 /* Version number */
 278         .string "zRS"           /* NUL-terminated augmentation string */
 279         .uleb128 4              /* Code alignment factor */
 280         .sleb128 -8             /* Data alignment factor */
 281         .byte 67                /* Return address register column, ap */
 282         .uleb128 1              /* Augmentation value length */
 283         .byte 0x14              /* DW_EH_PE_pcrel | DW_EH_PE_udata8. */
 284         .byte 0x0c,1,0          /* DW_CFA_def_cfa: r1 ofs 0 */
 285         .balign 8
 286 .Lcie_end:
 287 
 288         .long .Lfde0_end - .Lfde0_start
 289 .Lfde0_start:
 290         .long .Lfde0_start - .Lcie      /* CIE pointer. */
 291         .quad .Lsigrt_start - .         /* PC start, length */
 292         .quad .Lsigrt_end - .Lsigrt_start
 293         .uleb128 0                      /* Augmentation */
 294         EH_FRAME_GEN
 295         EH_FRAME_FP
 296         EH_FRAME_VMX
 297 # Do we really need to describe the frame at this point?  ie. will
 298 # we ever have some call chain that returns somewhere past the addi?
 299 # I don't think so, since gcc doesn't support async signals.
 300 #       .byte 0x41              /* DW_CFA_advance_loc 1*4 */
 301 #undef PTREGS
 302 #define PTREGS 168+56
 303 #       EH_FRAME_GEN
 304 #       EH_FRAME_FP
 305 #       EH_FRAME_VMX
 306         .balign 8
 307 .Lfde0_end: