root/arch/powerpc/kernel/exceptions-64e.S

   1 /* SPDX-License-Identifier: GPL-2.0-or-later */
   2 /*
   3  *  Boot code and exception vectors for Book3E processors
   4  *
   5  *  Copyright (C) 2007 Ben. Herrenschmidt (benh@kernel.crashing.org), IBM Corp.
   6  */
   7 
   8 #include <linux/threads.h>
   9 #include <asm/reg.h>
  10 #include <asm/page.h>
  11 #include <asm/ppc_asm.h>
  12 #include <asm/asm-offsets.h>
  13 #include <asm/cputable.h>
  14 #include <asm/setup.h>
  15 #include <asm/thread_info.h>
  16 #include <asm/reg_a2.h>
  17 #include <asm/exception-64e.h>
  18 #include <asm/bug.h>
  19 #include <asm/irqflags.h>
  20 #include <asm/ptrace.h>
  21 #include <asm/ppc-opcode.h>
  22 #include <asm/mmu.h>
  23 #include <asm/hw_irq.h>
  24 #include <asm/kvm_asm.h>
  25 #include <asm/kvm_booke_hv_asm.h>
  26 #include <asm/feature-fixups.h>
  27 
  28 /* XXX This will ultimately add space for a special exception save
  29  *     structure used to save things like SRR0/SRR1, SPRGs, MAS, etc...
  30  *     when taking special interrupts. For now we don't support that,
  31  *     special interrupts from within a non-standard level will probably
  32  *     blow you up
  33  */
  34 #define SPECIAL_EXC_SRR0        0
  35 #define SPECIAL_EXC_SRR1        1
  36 #define SPECIAL_EXC_SPRG_GEN    2
  37 #define SPECIAL_EXC_SPRG_TLB    3
  38 #define SPECIAL_EXC_MAS0        4
  39 #define SPECIAL_EXC_MAS1        5
  40 #define SPECIAL_EXC_MAS2        6
  41 #define SPECIAL_EXC_MAS3        7
  42 #define SPECIAL_EXC_MAS6        8
  43 #define SPECIAL_EXC_MAS7        9
  44 #define SPECIAL_EXC_MAS5        10      /* E.HV only */
  45 #define SPECIAL_EXC_MAS8        11      /* E.HV only */
  46 #define SPECIAL_EXC_IRQHAPPENED 12
  47 #define SPECIAL_EXC_DEAR        13
  48 #define SPECIAL_EXC_ESR         14
  49 #define SPECIAL_EXC_SOFTE       15
  50 #define SPECIAL_EXC_CSRR0       16
  51 #define SPECIAL_EXC_CSRR1       17
  52 /* must be even to keep 16-byte stack alignment */
  53 #define SPECIAL_EXC_END         18
  54 
  55 #define SPECIAL_EXC_FRAME_SIZE  (INT_FRAME_SIZE + SPECIAL_EXC_END * 8)
  56 #define SPECIAL_EXC_FRAME_OFFS  (INT_FRAME_SIZE - 288)
  57 
  58 #define SPECIAL_EXC_STORE(reg, name) \
  59         std     reg, (SPECIAL_EXC_##name * 8 + SPECIAL_EXC_FRAME_OFFS)(r1)
  60 
  61 #define SPECIAL_EXC_LOAD(reg, name) \
  62         ld      reg, (SPECIAL_EXC_##name * 8 + SPECIAL_EXC_FRAME_OFFS)(r1)
  63 
  64 special_reg_save:
  65         lbz     r9,PACAIRQHAPPENED(r13)
  66         RECONCILE_IRQ_STATE(r3,r4)
  67 
  68         /*
  69          * We only need (or have stack space) to save this stuff if
  70          * we interrupted the kernel.
  71          */
  72         ld      r3,_MSR(r1)
  73         andi.   r3,r3,MSR_PR
  74         bnelr
  75 
  76         /*
  77          * Advance to the next TLB exception frame for handler
  78          * types that don't do it automatically.
  79          */
  80         LOAD_REG_ADDR(r11,extlb_level_exc)
  81         lwz     r12,0(r11)
  82         mfspr   r10,SPRN_SPRG_TLB_EXFRAME
  83         add     r10,r10,r12
  84         mtspr   SPRN_SPRG_TLB_EXFRAME,r10
  85 
  86         /*
  87          * Save registers needed to allow nesting of certain exceptions
  88          * (such as TLB misses) inside special exception levels
  89          */
  90         mfspr   r10,SPRN_SRR0
  91         SPECIAL_EXC_STORE(r10,SRR0)
  92         mfspr   r10,SPRN_SRR1
  93         SPECIAL_EXC_STORE(r10,SRR1)
  94         mfspr   r10,SPRN_SPRG_GEN_SCRATCH
  95         SPECIAL_EXC_STORE(r10,SPRG_GEN)
  96         mfspr   r10,SPRN_SPRG_TLB_SCRATCH
  97         SPECIAL_EXC_STORE(r10,SPRG_TLB)
  98         mfspr   r10,SPRN_MAS0
  99         SPECIAL_EXC_STORE(r10,MAS0)
 100         mfspr   r10,SPRN_MAS1
 101         SPECIAL_EXC_STORE(r10,MAS1)
 102         mfspr   r10,SPRN_MAS2
 103         SPECIAL_EXC_STORE(r10,MAS2)
 104         mfspr   r10,SPRN_MAS3
 105         SPECIAL_EXC_STORE(r10,MAS3)
 106         mfspr   r10,SPRN_MAS6
 107         SPECIAL_EXC_STORE(r10,MAS6)
 108         mfspr   r10,SPRN_MAS7
 109         SPECIAL_EXC_STORE(r10,MAS7)
 110 BEGIN_FTR_SECTION
 111         mfspr   r10,SPRN_MAS5
 112         SPECIAL_EXC_STORE(r10,MAS5)
 113         mfspr   r10,SPRN_MAS8
 114         SPECIAL_EXC_STORE(r10,MAS8)
 115 
 116         /* MAS5/8 could have inappropriate values if we interrupted KVM code */
 117         li      r10,0
 118         mtspr   SPRN_MAS5,r10
 119         mtspr   SPRN_MAS8,r10
 120 END_FTR_SECTION_IFSET(CPU_FTR_EMB_HV)
 121         SPECIAL_EXC_STORE(r9,IRQHAPPENED)
 122 
 123         mfspr   r10,SPRN_DEAR
 124         SPECIAL_EXC_STORE(r10,DEAR)
 125         mfspr   r10,SPRN_ESR
 126         SPECIAL_EXC_STORE(r10,ESR)
 127 
 128         lbz     r10,PACAIRQSOFTMASK(r13)
 129         SPECIAL_EXC_STORE(r10,SOFTE)
 130         ld      r10,_NIP(r1)
 131         SPECIAL_EXC_STORE(r10,CSRR0)
 132         ld      r10,_MSR(r1)
 133         SPECIAL_EXC_STORE(r10,CSRR1)
 134 
 135         blr
 136 
 137 ret_from_level_except:
 138         ld      r3,_MSR(r1)
 139         andi.   r3,r3,MSR_PR
 140         beq     1f
 141         b       ret_from_except
 142 1:
 143 
 144         LOAD_REG_ADDR(r11,extlb_level_exc)
 145         lwz     r12,0(r11)
 146         mfspr   r10,SPRN_SPRG_TLB_EXFRAME
 147         sub     r10,r10,r12
 148         mtspr   SPRN_SPRG_TLB_EXFRAME,r10
 149 
 150         /*
 151          * It's possible that the special level exception interrupted a
 152          * TLB miss handler, and inserted the same entry that the
 153          * interrupted handler was about to insert.  On CPUs without TLB
 154          * write conditional, this can result in a duplicate TLB entry.
 155          * Wipe all non-bolted entries to be safe.
 156          *
 157          * Note that this doesn't protect against any TLB misses
 158          * we may take accessing the stack from here to the end of
 159          * the special level exception.  It's not clear how we can
 160          * reasonably protect against that, but only CPUs with
 161          * neither TLB write conditional nor bolted kernel memory
 162          * are affected.  Do any such CPUs even exist?
 163          */
 164         PPC_TLBILX_ALL(0,R0)
 165 
 166         REST_NVGPRS(r1)
 167 
 168         SPECIAL_EXC_LOAD(r10,SRR0)
 169         mtspr   SPRN_SRR0,r10
 170         SPECIAL_EXC_LOAD(r10,SRR1)
 171         mtspr   SPRN_SRR1,r10
 172         SPECIAL_EXC_LOAD(r10,SPRG_GEN)
 173         mtspr   SPRN_SPRG_GEN_SCRATCH,r10
 174         SPECIAL_EXC_LOAD(r10,SPRG_TLB)
 175         mtspr   SPRN_SPRG_TLB_SCRATCH,r10
 176         SPECIAL_EXC_LOAD(r10,MAS0)
 177         mtspr   SPRN_MAS0,r10
 178         SPECIAL_EXC_LOAD(r10,MAS1)
 179         mtspr   SPRN_MAS1,r10
 180         SPECIAL_EXC_LOAD(r10,MAS2)
 181         mtspr   SPRN_MAS2,r10
 182         SPECIAL_EXC_LOAD(r10,MAS3)
 183         mtspr   SPRN_MAS3,r10
 184         SPECIAL_EXC_LOAD(r10,MAS6)
 185         mtspr   SPRN_MAS6,r10
 186         SPECIAL_EXC_LOAD(r10,MAS7)
 187         mtspr   SPRN_MAS7,r10
 188 BEGIN_FTR_SECTION
 189         SPECIAL_EXC_LOAD(r10,MAS5)
 190         mtspr   SPRN_MAS5,r10
 191         SPECIAL_EXC_LOAD(r10,MAS8)
 192         mtspr   SPRN_MAS8,r10
 193 END_FTR_SECTION_IFSET(CPU_FTR_EMB_HV)
 194 
 195         lbz     r6,PACAIRQSOFTMASK(r13)
 196         ld      r5,SOFTE(r1)
 197 
 198         /* Interrupts had better not already be enabled... */
 199         tweqi   r6,IRQS_ENABLED
 200 
 201         andi.   r6,r5,IRQS_DISABLED
 202         bne     1f
 203 
 204         TRACE_ENABLE_INTS
 205         stb     r5,PACAIRQSOFTMASK(r13)
 206 1:
 207         /*
 208          * Restore PACAIRQHAPPENED rather than setting it based on
 209          * the return MSR[EE], since we could have interrupted
 210          * __check_irq_replay() or other inconsistent transitory
 211          * states that must remain that way.
 212          */
 213         SPECIAL_EXC_LOAD(r10,IRQHAPPENED)
 214         stb     r10,PACAIRQHAPPENED(r13)
 215 
 216         SPECIAL_EXC_LOAD(r10,DEAR)
 217         mtspr   SPRN_DEAR,r10
 218         SPECIAL_EXC_LOAD(r10,ESR)
 219         mtspr   SPRN_ESR,r10
 220 
 221         stdcx.  r0,0,r1         /* to clear the reservation */
 222 
 223         REST_4GPRS(2, r1)
 224         REST_4GPRS(6, r1)
 225 
 226         ld      r10,_CTR(r1)
 227         ld      r11,_XER(r1)
 228         mtctr   r10
 229         mtxer   r11
 230 
 231         blr
 232 
 233 .macro ret_from_level srr0 srr1 paca_ex scratch
 234         bl      ret_from_level_except
 235 
 236         ld      r10,_LINK(r1)
 237         ld      r11,_CCR(r1)
 238         ld      r0,GPR13(r1)
 239         mtlr    r10
 240         mtcr    r11
 241 
 242         ld      r10,GPR10(r1)
 243         ld      r11,GPR11(r1)
 244         ld      r12,GPR12(r1)
 245         mtspr   \scratch,r0
 246 
 247         std     r10,\paca_ex+EX_R10(r13);
 248         std     r11,\paca_ex+EX_R11(r13);
 249         ld      r10,_NIP(r1)
 250         ld      r11,_MSR(r1)
 251         ld      r0,GPR0(r1)
 252         ld      r1,GPR1(r1)
 253         mtspr   \srr0,r10
 254         mtspr   \srr1,r11
 255         ld      r10,\paca_ex+EX_R10(r13)
 256         ld      r11,\paca_ex+EX_R11(r13)
 257         mfspr   r13,\scratch
 258 .endm
 259 
 260 ret_from_crit_except:
 261         ret_from_level SPRN_CSRR0 SPRN_CSRR1 PACA_EXCRIT SPRN_SPRG_CRIT_SCRATCH
 262         rfci
 263 
 264 ret_from_mc_except:
 265         ret_from_level SPRN_MCSRR0 SPRN_MCSRR1 PACA_EXMC SPRN_SPRG_MC_SCRATCH
 266         rfmci
 267 
 268 /* Exception prolog code for all exceptions */
 269 #define EXCEPTION_PROLOG(n, intnum, type, addition)                         \
 270         mtspr   SPRN_SPRG_##type##_SCRATCH,r13; /* get spare registers */   \
 271         mfspr   r13,SPRN_SPRG_PACA;     /* get PACA */                      \
 272         std     r10,PACA_EX##type+EX_R10(r13);                              \
 273         std     r11,PACA_EX##type+EX_R11(r13);                              \
 274         mfcr    r10;                    /* save CR */                       \
 275         mfspr   r11,SPRN_##type##_SRR1;/* what are we coming from */        \
 276         DO_KVM  intnum,SPRN_##type##_SRR1;    /* KVM hook */                \
 277         stw     r10,PACA_EX##type+EX_CR(r13); /* save old CR in the PACA */ \
 278         addition;                       /* additional code for that exc. */ \
 279         std     r1,PACA_EX##type+EX_R1(r13); /* save old r1 in the PACA */  \
 280         type##_SET_KSTACK;              /* get special stack if necessary */\
 281         andi.   r10,r11,MSR_PR;         /* save stack pointer */            \
 282         beq     1f;                     /* branch around if supervisor */   \
 283         ld      r1,PACAKSAVE(r13);      /* get kernel stack coming from usr */\
 284 1:      type##_BTB_FLUSH                \
 285         cmpdi   cr1,r1,0;               /* check if SP makes sense */       \
 286         bge-    cr1,exc_##n##_bad_stack;/* bad stack (TODO: out of line) */ \
 287         mfspr   r10,SPRN_##type##_SRR0; /* read SRR0 before touching stack */
 288 
 289 /* Exception type-specific macros */
 290 #define GEN_SET_KSTACK                                                      \
 291         subi    r1,r1,INT_FRAME_SIZE;   /* alloc frame on kernel stack */
 292 #define SPRN_GEN_SRR0   SPRN_SRR0
 293 #define SPRN_GEN_SRR1   SPRN_SRR1
 294 
 295 #define GDBELL_SET_KSTACK       GEN_SET_KSTACK
 296 #define SPRN_GDBELL_SRR0        SPRN_GSRR0
 297 #define SPRN_GDBELL_SRR1        SPRN_GSRR1
 298 
 299 #define CRIT_SET_KSTACK                                                     \
 300         ld      r1,PACA_CRIT_STACK(r13);                                    \
 301         subi    r1,r1,SPECIAL_EXC_FRAME_SIZE
 302 #define SPRN_CRIT_SRR0  SPRN_CSRR0
 303 #define SPRN_CRIT_SRR1  SPRN_CSRR1
 304 
 305 #define DBG_SET_KSTACK                                                      \
 306         ld      r1,PACA_DBG_STACK(r13);                                     \
 307         subi    r1,r1,SPECIAL_EXC_FRAME_SIZE
 308 #define SPRN_DBG_SRR0   SPRN_DSRR0
 309 #define SPRN_DBG_SRR1   SPRN_DSRR1
 310 
 311 #define MC_SET_KSTACK                                                       \
 312         ld      r1,PACA_MC_STACK(r13);                                      \
 313         subi    r1,r1,SPECIAL_EXC_FRAME_SIZE
 314 #define SPRN_MC_SRR0    SPRN_MCSRR0
 315 #define SPRN_MC_SRR1    SPRN_MCSRR1
 316 
 317 #ifdef CONFIG_PPC_FSL_BOOK3E
 318 #define GEN_BTB_FLUSH                   \
 319         START_BTB_FLUSH_SECTION         \
 320                 beq 1f;                 \
 321                 BTB_FLUSH(r10)                  \
 322                 1:              \
 323         END_BTB_FLUSH_SECTION
 324 
 325 #define CRIT_BTB_FLUSH                  \
 326         START_BTB_FLUSH_SECTION         \
 327                 BTB_FLUSH(r10)          \
 328         END_BTB_FLUSH_SECTION
 329 
 330 #define DBG_BTB_FLUSH CRIT_BTB_FLUSH
 331 #define MC_BTB_FLUSH CRIT_BTB_FLUSH
 332 #define GDBELL_BTB_FLUSH GEN_BTB_FLUSH
 333 #else
 334 #define GEN_BTB_FLUSH
 335 #define CRIT_BTB_FLUSH
 336 #define DBG_BTB_FLUSH
 337 #define MC_BTB_FLUSH
 338 #define GDBELL_BTB_FLUSH
 339 #endif
 340 
 341 #define NORMAL_EXCEPTION_PROLOG(n, intnum, addition)                        \
 342         EXCEPTION_PROLOG(n, intnum, GEN, addition##_GEN(n))
 343 
 344 #define CRIT_EXCEPTION_PROLOG(n, intnum, addition)                          \
 345         EXCEPTION_PROLOG(n, intnum, CRIT, addition##_CRIT(n))
 346 
 347 #define DBG_EXCEPTION_PROLOG(n, intnum, addition)                           \
 348         EXCEPTION_PROLOG(n, intnum, DBG, addition##_DBG(n))
 349 
 350 #define MC_EXCEPTION_PROLOG(n, intnum, addition)                            \
 351         EXCEPTION_PROLOG(n, intnum, MC, addition##_MC(n))
 352 
 353 #define GDBELL_EXCEPTION_PROLOG(n, intnum, addition)                        \
 354         EXCEPTION_PROLOG(n, intnum, GDBELL, addition##_GDBELL(n))
 355 
 356 /* Variants of the "addition" argument for the prolog
 357  */
 358 #define PROLOG_ADDITION_NONE_GEN(n)
 359 #define PROLOG_ADDITION_NONE_GDBELL(n)
 360 #define PROLOG_ADDITION_NONE_CRIT(n)
 361 #define PROLOG_ADDITION_NONE_DBG(n)
 362 #define PROLOG_ADDITION_NONE_MC(n)
 363 
 364 #define PROLOG_ADDITION_MASKABLE_GEN(n)                                     \
 365         lbz     r10,PACAIRQSOFTMASK(r13);       /* are irqs soft-masked? */ \
 366         andi.   r10,r10,IRQS_DISABLED;  /* yes -> go out of line */ \
 367         bne     masked_interrupt_book3e_##n
 368 
 369 #define PROLOG_ADDITION_2REGS_GEN(n)                                        \
 370         std     r14,PACA_EXGEN+EX_R14(r13);                                 \
 371         std     r15,PACA_EXGEN+EX_R15(r13)
 372 
 373 #define PROLOG_ADDITION_1REG_GEN(n)                                         \
 374         std     r14,PACA_EXGEN+EX_R14(r13);
 375 
 376 #define PROLOG_ADDITION_2REGS_CRIT(n)                                       \
 377         std     r14,PACA_EXCRIT+EX_R14(r13);                                \
 378         std     r15,PACA_EXCRIT+EX_R15(r13)
 379 
 380 #define PROLOG_ADDITION_2REGS_DBG(n)                                        \
 381         std     r14,PACA_EXDBG+EX_R14(r13);                                 \
 382         std     r15,PACA_EXDBG+EX_R15(r13)
 383 
 384 #define PROLOG_ADDITION_2REGS_MC(n)                                         \
 385         std     r14,PACA_EXMC+EX_R14(r13);                                  \
 386         std     r15,PACA_EXMC+EX_R15(r13)
 387 
 388 
 389 /* Core exception code for all exceptions except TLB misses. */
 390 #define EXCEPTION_COMMON_LVL(n, scratch, excf)                              \
 391 exc_##n##_common:                                                           \
 392         std     r0,GPR0(r1);            /* save r0 in stackframe */         \
 393         std     r2,GPR2(r1);            /* save r2 in stackframe */         \
 394         SAVE_4GPRS(3, r1);              /* save r3 - r6 in stackframe */    \
 395         SAVE_2GPRS(7, r1);              /* save r7, r8 in stackframe */     \
 396         std     r9,GPR9(r1);            /* save r9 in stackframe */         \
 397         std     r10,_NIP(r1);           /* save SRR0 to stackframe */       \
 398         std     r11,_MSR(r1);           /* save SRR1 to stackframe */       \
 399         beq     2f;                     /* if from kernel mode */           \
 400         ACCOUNT_CPU_USER_ENTRY(r13,r10,r11);/* accounting (uses cr0+eq) */  \
 401 2:      ld      r3,excf+EX_R10(r13);    /* get back r10 */                  \
 402         ld      r4,excf+EX_R11(r13);    /* get back r11 */                  \
 403         mfspr   r5,scratch;             /* get back r13 */                  \
 404         std     r12,GPR12(r1);          /* save r12 in stackframe */        \
 405         ld      r2,PACATOC(r13);        /* get kernel TOC into r2 */        \
 406         mflr    r6;                     /* save LR in stackframe */         \
 407         mfctr   r7;                     /* save CTR in stackframe */        \
 408         mfspr   r8,SPRN_XER;            /* save XER in stackframe */        \
 409         ld      r9,excf+EX_R1(r13);     /* load orig r1 back from PACA */   \
 410         lwz     r10,excf+EX_CR(r13);    /* load orig CR back from PACA  */  \
 411         lbz     r11,PACAIRQSOFTMASK(r13); /* get current IRQ softe */       \
 412         ld      r12,exception_marker@toc(r2);                               \
 413         li      r0,0;                                                       \
 414         std     r3,GPR10(r1);           /* save r10 to stackframe */        \
 415         std     r4,GPR11(r1);           /* save r11 to stackframe */        \
 416         std     r5,GPR13(r1);           /* save it to stackframe */         \
 417         std     r6,_LINK(r1);                                               \
 418         std     r7,_CTR(r1);                                                \
 419         std     r8,_XER(r1);                                                \
 420         li      r3,(n)+1;               /* indicate partial regs in trap */ \
 421         std     r9,0(r1);               /* store stack frame back link */   \
 422         std     r10,_CCR(r1);           /* store orig CR in stackframe */   \
 423         std     r9,GPR1(r1);            /* store stack frame back link */   \
 424         std     r11,SOFTE(r1);          /* and save it to stackframe */     \
 425         std     r12,STACK_FRAME_OVERHEAD-16(r1); /* mark the frame */       \
 426         std     r3,_TRAP(r1);           /* set trap number              */  \
 427         std     r0,RESULT(r1);          /* clear regs->result */
 428 
 429 #define EXCEPTION_COMMON(n) \
 430         EXCEPTION_COMMON_LVL(n, SPRN_SPRG_GEN_SCRATCH, PACA_EXGEN)
 431 #define EXCEPTION_COMMON_CRIT(n) \
 432         EXCEPTION_COMMON_LVL(n, SPRN_SPRG_CRIT_SCRATCH, PACA_EXCRIT)
 433 #define EXCEPTION_COMMON_MC(n) \
 434         EXCEPTION_COMMON_LVL(n, SPRN_SPRG_MC_SCRATCH, PACA_EXMC)
 435 #define EXCEPTION_COMMON_DBG(n) \
 436         EXCEPTION_COMMON_LVL(n, SPRN_SPRG_DBG_SCRATCH, PACA_EXDBG)
 437 
 438 /*
 439  * This is meant for exceptions that don't immediately hard-enable.  We
 440  * set a bit in paca->irq_happened to ensure that a subsequent call to
 441  * arch_local_irq_restore() will properly hard-enable and avoid the
 442  * fast-path, and then reconcile irq state.
 443  */
 444 #define INTS_DISABLE    RECONCILE_IRQ_STATE(r3,r4)
 445 
 446 /*
 447  * This is called by exceptions that don't use INTS_DISABLE (that did not
 448  * touch irq indicators in the PACA).  This will restore MSR:EE to it's
 449  * previous value
 450  *
 451  * XXX In the long run, we may want to open-code it in order to separate the
 452  *     load from the wrtee, thus limiting the latency caused by the dependency
 453  *     but at this point, I'll favor code clarity until we have a near to final
 454  *     implementation
 455  */
 456 #define INTS_RESTORE_HARD                                                   \
 457         ld      r11,_MSR(r1);                                               \
 458         wrtee   r11;
 459 
 460 /* XXX FIXME: Restore r14/r15 when necessary */
 461 #define BAD_STACK_TRAMPOLINE(n)                                             \
 462 exc_##n##_bad_stack:                                                        \
 463         li      r1,(n);                 /* get exception number */          \
 464         sth     r1,PACA_TRAP_SAVE(r13); /* store trap */                    \
 465         b       bad_stack_book3e;       /* bad stack error */
 466 
 467 /* WARNING: If you change the layout of this stub, make sure you check
 468         *   the debug exception handler which handles single stepping
 469         *   into exceptions from userspace, and the MM code in
 470         *   arch/powerpc/mm/tlb_nohash.c which patches the branch here
 471         *   and would need to be updated if that branch is moved
 472         */
 473 #define EXCEPTION_STUB(loc, label)                                      \
 474         . = interrupt_base_book3e + loc;                                \
 475         nop;    /* To make debug interrupts happy */                    \
 476         b       exc_##label##_book3e;
 477 
 478 #define ACK_NONE(r)
 479 #define ACK_DEC(r)                                                      \
 480         lis     r,TSR_DIS@h;                                            \
 481         mtspr   SPRN_TSR,r
 482 #define ACK_FIT(r)                                                      \
 483         lis     r,TSR_FIS@h;                                            \
 484         mtspr   SPRN_TSR,r
 485 
 486 /* Used by asynchronous interrupt that may happen in the idle loop.
 487  *
 488  * This check if the thread was in the idle loop, and if yes, returns
 489  * to the caller rather than the PC. This is to avoid a race if
 490  * interrupts happen before the wait instruction.
 491  */
 492 #define CHECK_NAPPING()                                                 \
 493         ld      r11, PACA_THREAD_INFO(r13);                             \
 494         ld      r10,TI_LOCAL_FLAGS(r11);                                \
 495         andi.   r9,r10,_TLF_NAPPING;                                    \
 496         beq+    1f;                                                     \
 497         ld      r8,_LINK(r1);                                           \
 498         rlwinm  r7,r10,0,~_TLF_NAPPING;                                 \
 499         std     r8,_NIP(r1);                                            \
 500         std     r7,TI_LOCAL_FLAGS(r11);                                 \
 501 1:
 502 
 503 
 504 #define MASKABLE_EXCEPTION(trapnum, intnum, label, hdlr, ack)           \
 505         START_EXCEPTION(label);                                         \
 506         NORMAL_EXCEPTION_PROLOG(trapnum, intnum, PROLOG_ADDITION_MASKABLE)\
 507         EXCEPTION_COMMON(trapnum)                                       \
 508         INTS_DISABLE;                                                   \
 509         ack(r8);                                                        \
 510         CHECK_NAPPING();                                                \
 511         addi    r3,r1,STACK_FRAME_OVERHEAD;                             \
 512         bl      hdlr;                                                   \
 513         b       ret_from_except_lite;
 514 
 515 /* This value is used to mark exception frames on the stack. */
 516         .section        ".toc","aw"
 517 exception_marker:
 518         .tc     ID_EXC_MARKER[TC],STACK_FRAME_REGS_MARKER
 519 
 520 
 521 /*
 522  * And here we have the exception vectors !
 523  */
 524 
 525         .text
 526         .balign 0x1000
 527         .globl interrupt_base_book3e
 528 interrupt_base_book3e:                                  /* fake trap */
 529         EXCEPTION_STUB(0x000, machine_check)
 530         EXCEPTION_STUB(0x020, critical_input)           /* 0x0100 */
 531         EXCEPTION_STUB(0x040, debug_crit)               /* 0x0d00 */
 532         EXCEPTION_STUB(0x060, data_storage)             /* 0x0300 */
 533         EXCEPTION_STUB(0x080, instruction_storage)      /* 0x0400 */
 534         EXCEPTION_STUB(0x0a0, external_input)           /* 0x0500 */
 535         EXCEPTION_STUB(0x0c0, alignment)                /* 0x0600 */
 536         EXCEPTION_STUB(0x0e0, program)                  /* 0x0700 */
 537         EXCEPTION_STUB(0x100, fp_unavailable)           /* 0x0800 */
 538         EXCEPTION_STUB(0x120, system_call)              /* 0x0c00 */
 539         EXCEPTION_STUB(0x140, ap_unavailable)           /* 0x0f20 */
 540         EXCEPTION_STUB(0x160, decrementer)              /* 0x0900 */
 541         EXCEPTION_STUB(0x180, fixed_interval)           /* 0x0980 */
 542         EXCEPTION_STUB(0x1a0, watchdog)                 /* 0x09f0 */
 543         EXCEPTION_STUB(0x1c0, data_tlb_miss)
 544         EXCEPTION_STUB(0x1e0, instruction_tlb_miss)
 545         EXCEPTION_STUB(0x200, altivec_unavailable)
 546         EXCEPTION_STUB(0x220, altivec_assist)
 547         EXCEPTION_STUB(0x260, perfmon)
 548         EXCEPTION_STUB(0x280, doorbell)
 549         EXCEPTION_STUB(0x2a0, doorbell_crit)
 550         EXCEPTION_STUB(0x2c0, guest_doorbell)
 551         EXCEPTION_STUB(0x2e0, guest_doorbell_crit)
 552         EXCEPTION_STUB(0x300, hypercall)
 553         EXCEPTION_STUB(0x320, ehpriv)
 554         EXCEPTION_STUB(0x340, lrat_error)
 555 
 556         .globl __end_interrupts
 557 __end_interrupts:
 558 
 559 /* Critical Input Interrupt */
 560         START_EXCEPTION(critical_input);
 561         CRIT_EXCEPTION_PROLOG(0x100, BOOKE_INTERRUPT_CRITICAL,
 562                               PROLOG_ADDITION_NONE)
 563         EXCEPTION_COMMON_CRIT(0x100)
 564         bl      save_nvgprs
 565         bl      special_reg_save
 566         CHECK_NAPPING();
 567         addi    r3,r1,STACK_FRAME_OVERHEAD
 568         bl      unknown_exception
 569         b       ret_from_crit_except
 570 
 571 /* Machine Check Interrupt */
 572         START_EXCEPTION(machine_check);
 573         MC_EXCEPTION_PROLOG(0x000, BOOKE_INTERRUPT_MACHINE_CHECK,
 574                             PROLOG_ADDITION_NONE)
 575         EXCEPTION_COMMON_MC(0x000)
 576         bl      save_nvgprs
 577         bl      special_reg_save
 578         CHECK_NAPPING();
 579         addi    r3,r1,STACK_FRAME_OVERHEAD
 580         bl      machine_check_exception
 581         b       ret_from_mc_except
 582 
 583 /* Data Storage Interrupt */
 584         START_EXCEPTION(data_storage)
 585         NORMAL_EXCEPTION_PROLOG(0x300, BOOKE_INTERRUPT_DATA_STORAGE,
 586                                 PROLOG_ADDITION_2REGS)
 587         mfspr   r14,SPRN_DEAR
 588         mfspr   r15,SPRN_ESR
 589         EXCEPTION_COMMON(0x300)
 590         INTS_DISABLE
 591         b       storage_fault_common
 592 
 593 /* Instruction Storage Interrupt */
 594         START_EXCEPTION(instruction_storage);
 595         NORMAL_EXCEPTION_PROLOG(0x400, BOOKE_INTERRUPT_INST_STORAGE,
 596                                 PROLOG_ADDITION_2REGS)
 597         li      r15,0
 598         mr      r14,r10
 599         EXCEPTION_COMMON(0x400)
 600         INTS_DISABLE
 601         b       storage_fault_common
 602 
 603 /* External Input Interrupt */
 604         MASKABLE_EXCEPTION(0x500, BOOKE_INTERRUPT_EXTERNAL,
 605                            external_input, do_IRQ, ACK_NONE)
 606 
 607 /* Alignment */
 608         START_EXCEPTION(alignment);
 609         NORMAL_EXCEPTION_PROLOG(0x600, BOOKE_INTERRUPT_ALIGNMENT,
 610                                 PROLOG_ADDITION_2REGS)
 611         mfspr   r14,SPRN_DEAR
 612         mfspr   r15,SPRN_ESR
 613         EXCEPTION_COMMON(0x600)
 614         b       alignment_more  /* no room, go out of line */
 615 
 616 /* Program Interrupt */
 617         START_EXCEPTION(program);
 618         NORMAL_EXCEPTION_PROLOG(0x700, BOOKE_INTERRUPT_PROGRAM,
 619                                 PROLOG_ADDITION_1REG)
 620         mfspr   r14,SPRN_ESR
 621         EXCEPTION_COMMON(0x700)
 622         INTS_DISABLE
 623         std     r14,_DSISR(r1)
 624         addi    r3,r1,STACK_FRAME_OVERHEAD
 625         ld      r14,PACA_EXGEN+EX_R14(r13)
 626         bl      save_nvgprs
 627         bl      program_check_exception
 628         b       ret_from_except
 629 
 630 /* Floating Point Unavailable Interrupt */
 631         START_EXCEPTION(fp_unavailable);
 632         NORMAL_EXCEPTION_PROLOG(0x800, BOOKE_INTERRUPT_FP_UNAVAIL,
 633                                 PROLOG_ADDITION_NONE)
 634         /* we can probably do a shorter exception entry for that one... */
 635         EXCEPTION_COMMON(0x800)
 636         ld      r12,_MSR(r1)
 637         andi.   r0,r12,MSR_PR;
 638         beq-    1f
 639         bl      load_up_fpu
 640         b       fast_exception_return
 641 1:      INTS_DISABLE
 642         bl      save_nvgprs
 643         addi    r3,r1,STACK_FRAME_OVERHEAD
 644         bl      kernel_fp_unavailable_exception
 645         b       ret_from_except
 646 
 647 /* Altivec Unavailable Interrupt */
 648         START_EXCEPTION(altivec_unavailable);
 649         NORMAL_EXCEPTION_PROLOG(0x200, BOOKE_INTERRUPT_ALTIVEC_UNAVAIL,
 650                                 PROLOG_ADDITION_NONE)
 651         /* we can probably do a shorter exception entry for that one... */
 652         EXCEPTION_COMMON(0x200)
 653 #ifdef CONFIG_ALTIVEC
 654 BEGIN_FTR_SECTION
 655         ld      r12,_MSR(r1)
 656         andi.   r0,r12,MSR_PR;
 657         beq-    1f
 658         bl      load_up_altivec
 659         b       fast_exception_return
 660 1:
 661 END_FTR_SECTION_IFSET(CPU_FTR_ALTIVEC)
 662 #endif
 663         INTS_DISABLE
 664         bl      save_nvgprs
 665         addi    r3,r1,STACK_FRAME_OVERHEAD
 666         bl      altivec_unavailable_exception
 667         b       ret_from_except
 668 
 669 /* AltiVec Assist */
 670         START_EXCEPTION(altivec_assist);
 671         NORMAL_EXCEPTION_PROLOG(0x220,
 672                                 BOOKE_INTERRUPT_ALTIVEC_ASSIST,
 673                                 PROLOG_ADDITION_NONE)
 674         EXCEPTION_COMMON(0x220)
 675         INTS_DISABLE
 676         bl      save_nvgprs
 677         addi    r3,r1,STACK_FRAME_OVERHEAD
 678 #ifdef CONFIG_ALTIVEC
 679 BEGIN_FTR_SECTION
 680         bl      altivec_assist_exception
 681 END_FTR_SECTION_IFSET(CPU_FTR_ALTIVEC)
 682 #else
 683         bl      unknown_exception
 684 #endif
 685         b       ret_from_except
 686 
 687 
 688 /* Decrementer Interrupt */
 689         MASKABLE_EXCEPTION(0x900, BOOKE_INTERRUPT_DECREMENTER,
 690                            decrementer, timer_interrupt, ACK_DEC)
 691 
 692 /* Fixed Interval Timer Interrupt */
 693         MASKABLE_EXCEPTION(0x980, BOOKE_INTERRUPT_FIT,
 694                            fixed_interval, unknown_exception, ACK_FIT)
 695 
 696 /* Watchdog Timer Interrupt */
 697         START_EXCEPTION(watchdog);
 698         CRIT_EXCEPTION_PROLOG(0x9f0, BOOKE_INTERRUPT_WATCHDOG,
 699                               PROLOG_ADDITION_NONE)
 700         EXCEPTION_COMMON_CRIT(0x9f0)
 701         bl      save_nvgprs
 702         bl      special_reg_save
 703         CHECK_NAPPING();
 704         addi    r3,r1,STACK_FRAME_OVERHEAD
 705 #ifdef CONFIG_BOOKE_WDT
 706         bl      WatchdogException
 707 #else
 708         bl      unknown_exception
 709 #endif
 710         b       ret_from_crit_except
 711 
 712 /* System Call Interrupt */
 713         START_EXCEPTION(system_call)
 714         mr      r9,r13                  /* keep a copy of userland r13 */
 715         mfspr   r11,SPRN_SRR0           /* get return address */
 716         mfspr   r12,SPRN_SRR1           /* get previous MSR */
 717         mfspr   r13,SPRN_SPRG_PACA      /* get our PACA */
 718         b       system_call_common
 719 
 720 /* Auxiliary Processor Unavailable Interrupt */
 721         START_EXCEPTION(ap_unavailable);
 722         NORMAL_EXCEPTION_PROLOG(0xf20, BOOKE_INTERRUPT_AP_UNAVAIL,
 723                                 PROLOG_ADDITION_NONE)
 724         EXCEPTION_COMMON(0xf20)
 725         INTS_DISABLE
 726         bl      save_nvgprs
 727         addi    r3,r1,STACK_FRAME_OVERHEAD
 728         bl      unknown_exception
 729         b       ret_from_except
 730 
 731 /* Debug exception as a critical interrupt*/
 732         START_EXCEPTION(debug_crit);
 733         CRIT_EXCEPTION_PROLOG(0xd00, BOOKE_INTERRUPT_DEBUG,
 734                               PROLOG_ADDITION_2REGS)
 735 
 736         /*
 737          * If there is a single step or branch-taken exception in an
 738          * exception entry sequence, it was probably meant to apply to
 739          * the code where the exception occurred (since exception entry
 740          * doesn't turn off DE automatically).  We simulate the effect
 741          * of turning off DE on entry to an exception handler by turning
 742          * off DE in the CSRR1 value and clearing the debug status.
 743          */
 744 
 745         mfspr   r14,SPRN_DBSR           /* check single-step/branch taken */
 746         andis.  r15,r14,(DBSR_IC|DBSR_BT)@h
 747         beq+    1f
 748 
 749 #ifdef CONFIG_RELOCATABLE
 750         ld      r15,PACATOC(r13)
 751         ld      r14,interrupt_base_book3e@got(r15)
 752         ld      r15,__end_interrupts@got(r15)
 753         cmpld   cr0,r10,r14
 754         cmpld   cr1,r10,r15
 755 #else
 756         LOAD_REG_IMMEDIATE_SYM(r14, r15, interrupt_base_book3e)
 757         cmpld   cr0, r10, r14
 758         LOAD_REG_IMMEDIATE_SYM(r14, r15, __end_interrupts)
 759         cmpld   cr1, r10, r14
 760 #endif
 761         blt+    cr0,1f
 762         bge+    cr1,1f
 763 
 764         /* here it looks like we got an inappropriate debug exception. */
 765         lis     r14,(DBSR_IC|DBSR_BT)@h         /* clear the event */
 766         rlwinm  r11,r11,0,~MSR_DE       /* clear DE in the CSRR1 value */
 767         mtspr   SPRN_DBSR,r14
 768         mtspr   SPRN_CSRR1,r11
 769         lwz     r10,PACA_EXCRIT+EX_CR(r13)      /* restore registers */
 770         ld      r1,PACA_EXCRIT+EX_R1(r13)
 771         ld      r14,PACA_EXCRIT+EX_R14(r13)
 772         ld      r15,PACA_EXCRIT+EX_R15(r13)
 773         mtcr    r10
 774         ld      r10,PACA_EXCRIT+EX_R10(r13)     /* restore registers */
 775         ld      r11,PACA_EXCRIT+EX_R11(r13)
 776         mfspr   r13,SPRN_SPRG_CRIT_SCRATCH
 777         rfci
 778 
 779         /* Normal debug exception */
 780         /* XXX We only handle coming from userspace for now since we can't
 781          *     quite save properly an interrupted kernel state yet
 782          */
 783 1:      andi.   r14,r11,MSR_PR;         /* check for userspace again */
 784         beq     kernel_dbg_exc;         /* if from kernel mode */
 785 
 786         /* Now we mash up things to make it look like we are coming on a
 787          * normal exception
 788          */
 789         mfspr   r14,SPRN_DBSR
 790         EXCEPTION_COMMON_CRIT(0xd00)
 791         std     r14,_DSISR(r1)
 792         addi    r3,r1,STACK_FRAME_OVERHEAD
 793         mr      r4,r14
 794         ld      r14,PACA_EXCRIT+EX_R14(r13)
 795         ld      r15,PACA_EXCRIT+EX_R15(r13)
 796         bl      save_nvgprs
 797         bl      DebugException
 798         b       ret_from_except
 799 
 800 kernel_dbg_exc:
 801         b       .       /* NYI */
 802 
 803 /* Debug exception as a debug interrupt*/
 804         START_EXCEPTION(debug_debug);
 805         DBG_EXCEPTION_PROLOG(0xd00, BOOKE_INTERRUPT_DEBUG,
 806                                                  PROLOG_ADDITION_2REGS)
 807 
 808         /*
 809          * If there is a single step or branch-taken exception in an
 810          * exception entry sequence, it was probably meant to apply to
 811          * the code where the exception occurred (since exception entry
 812          * doesn't turn off DE automatically).  We simulate the effect
 813          * of turning off DE on entry to an exception handler by turning
 814          * off DE in the DSRR1 value and clearing the debug status.
 815          */
 816 
 817         mfspr   r14,SPRN_DBSR           /* check single-step/branch taken */
 818         andis.  r15,r14,(DBSR_IC|DBSR_BT)@h
 819         beq+    1f
 820 
 821 #ifdef CONFIG_RELOCATABLE
 822         ld      r15,PACATOC(r13)
 823         ld      r14,interrupt_base_book3e@got(r15)
 824         ld      r15,__end_interrupts@got(r15)
 825         cmpld   cr0,r10,r14
 826         cmpld   cr1,r10,r15
 827 #else
 828         LOAD_REG_IMMEDIATE_SYM(r14, r15, interrupt_base_book3e)
 829         cmpld   cr0, r10, r14
 830         LOAD_REG_IMMEDIATE_SYM(r14, r15,__end_interrupts)
 831         cmpld   cr1, r10, r14
 832 #endif
 833         blt+    cr0,1f
 834         bge+    cr1,1f
 835 
 836         /* here it looks like we got an inappropriate debug exception. */
 837         lis     r14,(DBSR_IC|DBSR_BT)@h         /* clear the event */
 838         rlwinm  r11,r11,0,~MSR_DE       /* clear DE in the DSRR1 value */
 839         mtspr   SPRN_DBSR,r14
 840         mtspr   SPRN_DSRR1,r11
 841         lwz     r10,PACA_EXDBG+EX_CR(r13)       /* restore registers */
 842         ld      r1,PACA_EXDBG+EX_R1(r13)
 843         ld      r14,PACA_EXDBG+EX_R14(r13)
 844         ld      r15,PACA_EXDBG+EX_R15(r13)
 845         mtcr    r10
 846         ld      r10,PACA_EXDBG+EX_R10(r13)      /* restore registers */
 847         ld      r11,PACA_EXDBG+EX_R11(r13)
 848         mfspr   r13,SPRN_SPRG_DBG_SCRATCH
 849         rfdi
 850 
 851         /* Normal debug exception */
 852         /* XXX We only handle coming from userspace for now since we can't
 853          *     quite save properly an interrupted kernel state yet
 854          */
 855 1:      andi.   r14,r11,MSR_PR;         /* check for userspace again */
 856         beq     kernel_dbg_exc;         /* if from kernel mode */
 857 
 858         /* Now we mash up things to make it look like we are coming on a
 859          * normal exception
 860          */
 861         mfspr   r14,SPRN_DBSR
 862         EXCEPTION_COMMON_DBG(0xd08)
 863         INTS_DISABLE
 864         std     r14,_DSISR(r1)
 865         addi    r3,r1,STACK_FRAME_OVERHEAD
 866         mr      r4,r14
 867         ld      r14,PACA_EXDBG+EX_R14(r13)
 868         ld      r15,PACA_EXDBG+EX_R15(r13)
 869         bl      save_nvgprs
 870         bl      DebugException
 871         b       ret_from_except
 872 
 873         START_EXCEPTION(perfmon);
 874         NORMAL_EXCEPTION_PROLOG(0x260, BOOKE_INTERRUPT_PERFORMANCE_MONITOR,
 875                                 PROLOG_ADDITION_NONE)
 876         EXCEPTION_COMMON(0x260)
 877         INTS_DISABLE
 878         CHECK_NAPPING()
 879         addi    r3,r1,STACK_FRAME_OVERHEAD
 880         bl      performance_monitor_exception
 881         b       ret_from_except_lite
 882 
 883 /* Doorbell interrupt */
 884         MASKABLE_EXCEPTION(0x280, BOOKE_INTERRUPT_DOORBELL,
 885                            doorbell, doorbell_exception, ACK_NONE)
 886 
 887 /* Doorbell critical Interrupt */
 888         START_EXCEPTION(doorbell_crit);
 889         CRIT_EXCEPTION_PROLOG(0x2a0, BOOKE_INTERRUPT_DOORBELL_CRITICAL,
 890                               PROLOG_ADDITION_NONE)
 891         EXCEPTION_COMMON_CRIT(0x2a0)
 892         bl      save_nvgprs
 893         bl      special_reg_save
 894         CHECK_NAPPING();
 895         addi    r3,r1,STACK_FRAME_OVERHEAD
 896         bl      unknown_exception
 897         b       ret_from_crit_except
 898 
 899 /*
 900  *      Guest doorbell interrupt
 901  *      This general exception use GSRRx save/restore registers
 902  */
 903         START_EXCEPTION(guest_doorbell);
 904         GDBELL_EXCEPTION_PROLOG(0x2c0, BOOKE_INTERRUPT_GUEST_DBELL,
 905                                 PROLOG_ADDITION_NONE)
 906         EXCEPTION_COMMON(0x2c0)
 907         addi    r3,r1,STACK_FRAME_OVERHEAD
 908         bl      save_nvgprs
 909         INTS_RESTORE_HARD
 910         bl      unknown_exception
 911         b       ret_from_except
 912 
 913 /* Guest Doorbell critical Interrupt */
 914         START_EXCEPTION(guest_doorbell_crit);
 915         CRIT_EXCEPTION_PROLOG(0x2e0, BOOKE_INTERRUPT_GUEST_DBELL_CRIT,
 916                               PROLOG_ADDITION_NONE)
 917         EXCEPTION_COMMON_CRIT(0x2e0)
 918         bl      save_nvgprs
 919         bl      special_reg_save
 920         CHECK_NAPPING();
 921         addi    r3,r1,STACK_FRAME_OVERHEAD
 922         bl      unknown_exception
 923         b       ret_from_crit_except
 924 
 925 /* Hypervisor call */
 926         START_EXCEPTION(hypercall);
 927         NORMAL_EXCEPTION_PROLOG(0x310, BOOKE_INTERRUPT_HV_SYSCALL,
 928                                 PROLOG_ADDITION_NONE)
 929         EXCEPTION_COMMON(0x310)
 930         addi    r3,r1,STACK_FRAME_OVERHEAD
 931         bl      save_nvgprs
 932         INTS_RESTORE_HARD
 933         bl      unknown_exception
 934         b       ret_from_except
 935 
 936 /* Embedded Hypervisor priviledged  */
 937         START_EXCEPTION(ehpriv);
 938         NORMAL_EXCEPTION_PROLOG(0x320, BOOKE_INTERRUPT_HV_PRIV,
 939                                 PROLOG_ADDITION_NONE)
 940         EXCEPTION_COMMON(0x320)
 941         addi    r3,r1,STACK_FRAME_OVERHEAD
 942         bl      save_nvgprs
 943         INTS_RESTORE_HARD
 944         bl      unknown_exception
 945         b       ret_from_except
 946 
 947 /* LRAT Error interrupt */
 948         START_EXCEPTION(lrat_error);
 949         NORMAL_EXCEPTION_PROLOG(0x340, BOOKE_INTERRUPT_LRAT_ERROR,
 950                                 PROLOG_ADDITION_NONE)
 951         EXCEPTION_COMMON(0x340)
 952         addi    r3,r1,STACK_FRAME_OVERHEAD
 953         bl      save_nvgprs
 954         INTS_RESTORE_HARD
 955         bl      unknown_exception
 956         b       ret_from_except
 957 
 958 /*
 959  * An interrupt came in while soft-disabled; We mark paca->irq_happened
 960  * accordingly and if the interrupt is level sensitive, we hard disable
 961  * hard disable (full_mask) corresponds to PACA_IRQ_MUST_HARD_MASK, so
 962  * keep these in synch.
 963  */
 964 
 965 .macro masked_interrupt_book3e paca_irq full_mask
 966         lbz     r10,PACAIRQHAPPENED(r13)
 967         .if \full_mask == 1
 968         ori     r10,r10,\paca_irq | PACA_IRQ_HARD_DIS
 969         .else
 970         ori     r10,r10,\paca_irq
 971         .endif
 972         stb     r10,PACAIRQHAPPENED(r13)
 973 
 974         .if \full_mask == 1
 975         rldicl  r10,r11,48,1            /* clear MSR_EE */
 976         rotldi  r11,r10,16
 977         mtspr   SPRN_SRR1,r11
 978         .endif
 979 
 980         lwz     r11,PACA_EXGEN+EX_CR(r13)
 981         mtcr    r11
 982         ld      r10,PACA_EXGEN+EX_R10(r13)
 983         ld      r11,PACA_EXGEN+EX_R11(r13)
 984         mfspr   r13,SPRN_SPRG_GEN_SCRATCH
 985         rfi
 986         b       .
 987 .endm
 988 
 989 masked_interrupt_book3e_0x500:
 990         // XXX When adding support for EPR, use PACA_IRQ_EE_EDGE
 991         masked_interrupt_book3e PACA_IRQ_EE 1
 992 
 993 masked_interrupt_book3e_0x900:
 994         ACK_DEC(r10);
 995         masked_interrupt_book3e PACA_IRQ_DEC 0
 996 
 997 masked_interrupt_book3e_0x980:
 998         ACK_FIT(r10);
 999         masked_interrupt_book3e PACA_IRQ_DEC 0
1000 
1001 masked_interrupt_book3e_0x280:
1002 masked_interrupt_book3e_0x2c0:
1003         masked_interrupt_book3e PACA_IRQ_DBELL 0
1004 
1005 /*
1006  * Called from arch_local_irq_enable when an interrupt needs
1007  * to be resent. r3 contains either 0x500,0x900,0x260 or 0x280
1008  * to indicate the kind of interrupt. MSR:EE is already off.
1009  * We generate a stackframe like if a real interrupt had happened.
1010  *
1011  * Note: While MSR:EE is off, we need to make sure that _MSR
1012  * in the generated frame has EE set to 1 or the exception
1013  * handler will not properly re-enable them.
1014  */
1015 _GLOBAL(__replay_interrupt)
1016         /* We are going to jump to the exception common code which
1017          * will retrieve various register values from the PACA which
1018          * we don't give a damn about.
1019          */
1020         mflr    r10
1021         mfmsr   r11
1022         mfcr    r4
1023         mtspr   SPRN_SPRG_GEN_SCRATCH,r13;
1024         std     r1,PACA_EXGEN+EX_R1(r13);
1025         stw     r4,PACA_EXGEN+EX_CR(r13);
1026         ori     r11,r11,MSR_EE
1027         subi    r1,r1,INT_FRAME_SIZE;
1028         cmpwi   cr0,r3,0x500
1029         beq     exc_0x500_common
1030         cmpwi   cr0,r3,0x900
1031         beq     exc_0x900_common
1032         cmpwi   cr0,r3,0x280
1033         beq     exc_0x280_common
1034         blr
1035 
1036 
1037 /*
1038  * This is called from 0x300 and 0x400 handlers after the prologs with
1039  * r14 and r15 containing the fault address and error code, with the
1040  * original values stashed away in the PACA
1041  */
1042 storage_fault_common:
1043         std     r14,_DAR(r1)
1044         std     r15,_DSISR(r1)
1045         addi    r3,r1,STACK_FRAME_OVERHEAD
1046         mr      r4,r14
1047         mr      r5,r15
1048         ld      r14,PACA_EXGEN+EX_R14(r13)
1049         ld      r15,PACA_EXGEN+EX_R15(r13)
1050         bl      do_page_fault
1051         cmpdi   r3,0
1052         bne-    1f
1053         b       ret_from_except_lite
1054 1:      bl      save_nvgprs
1055         mr      r5,r3
1056         addi    r3,r1,STACK_FRAME_OVERHEAD
1057         ld      r4,_DAR(r1)
1058         bl      bad_page_fault
1059         b       ret_from_except
1060 
1061 /*
1062  * Alignment exception doesn't fit entirely in the 0x100 bytes so it
1063  * continues here.
1064  */
1065 alignment_more:
1066         std     r14,_DAR(r1)
1067         std     r15,_DSISR(r1)
1068         addi    r3,r1,STACK_FRAME_OVERHEAD
1069         ld      r14,PACA_EXGEN+EX_R14(r13)
1070         ld      r15,PACA_EXGEN+EX_R15(r13)
1071         bl      save_nvgprs
1072         INTS_RESTORE_HARD
1073         bl      alignment_exception
1074         b       ret_from_except
1075 
1076 /*
1077  * We branch here from entry_64.S for the last stage of the exception
1078  * return code path. MSR:EE is expected to be off at that point
1079  */
1080 _GLOBAL(exception_return_book3e)
1081         b       1f
1082 
1083 /* This is the return from load_up_fpu fast path which could do with
1084  * less GPR restores in fact, but for now we have a single return path
1085  */
1086         .globl fast_exception_return
1087 fast_exception_return:
1088         wrteei  0
1089 1:      mr      r0,r13
1090         ld      r10,_MSR(r1)
1091         REST_4GPRS(2, r1)
1092         andi.   r6,r10,MSR_PR
1093         REST_2GPRS(6, r1)
1094         beq     1f
1095         ACCOUNT_CPU_USER_EXIT(r13, r10, r11)
1096         ld      r0,GPR13(r1)
1097 
1098 1:      stdcx.  r0,0,r1         /* to clear the reservation */
1099 
1100         ld      r8,_CCR(r1)
1101         ld      r9,_LINK(r1)
1102         ld      r10,_CTR(r1)
1103         ld      r11,_XER(r1)
1104         mtcr    r8
1105         mtlr    r9
1106         mtctr   r10
1107         mtxer   r11
1108         REST_2GPRS(8, r1)
1109         ld      r10,GPR10(r1)
1110         ld      r11,GPR11(r1)
1111         ld      r12,GPR12(r1)
1112         mtspr   SPRN_SPRG_GEN_SCRATCH,r0
1113 
1114         std     r10,PACA_EXGEN+EX_R10(r13);
1115         std     r11,PACA_EXGEN+EX_R11(r13);
1116         ld      r10,_NIP(r1)
1117         ld      r11,_MSR(r1)
1118         ld      r0,GPR0(r1)
1119         ld      r1,GPR1(r1)
1120         mtspr   SPRN_SRR0,r10
1121         mtspr   SPRN_SRR1,r11
1122         ld      r10,PACA_EXGEN+EX_R10(r13)
1123         ld      r11,PACA_EXGEN+EX_R11(r13)
1124         mfspr   r13,SPRN_SPRG_GEN_SCRATCH
1125         rfi
1126 
1127 /*
1128  * Trampolines used when spotting a bad kernel stack pointer in
1129  * the exception entry code.
1130  *
1131  * TODO: move some bits like SRR0 read to trampoline, pass PACA
1132  * index around, etc... to handle crit & mcheck
1133  */
1134 BAD_STACK_TRAMPOLINE(0x000)
1135 BAD_STACK_TRAMPOLINE(0x100)
1136 BAD_STACK_TRAMPOLINE(0x200)
1137 BAD_STACK_TRAMPOLINE(0x220)
1138 BAD_STACK_TRAMPOLINE(0x260)
1139 BAD_STACK_TRAMPOLINE(0x280)
1140 BAD_STACK_TRAMPOLINE(0x2a0)
1141 BAD_STACK_TRAMPOLINE(0x2c0)
1142 BAD_STACK_TRAMPOLINE(0x2e0)
1143 BAD_STACK_TRAMPOLINE(0x300)
1144 BAD_STACK_TRAMPOLINE(0x310)
1145 BAD_STACK_TRAMPOLINE(0x320)
1146 BAD_STACK_TRAMPOLINE(0x340)
1147 BAD_STACK_TRAMPOLINE(0x400)
1148 BAD_STACK_TRAMPOLINE(0x500)
1149 BAD_STACK_TRAMPOLINE(0x600)
1150 BAD_STACK_TRAMPOLINE(0x700)
1151 BAD_STACK_TRAMPOLINE(0x800)
1152 BAD_STACK_TRAMPOLINE(0x900)
1153 BAD_STACK_TRAMPOLINE(0x980)
1154 BAD_STACK_TRAMPOLINE(0x9f0)
1155 BAD_STACK_TRAMPOLINE(0xa00)
1156 BAD_STACK_TRAMPOLINE(0xb00)
1157 BAD_STACK_TRAMPOLINE(0xc00)
1158 BAD_STACK_TRAMPOLINE(0xd00)
1159 BAD_STACK_TRAMPOLINE(0xd08)
1160 BAD_STACK_TRAMPOLINE(0xe00)
1161 BAD_STACK_TRAMPOLINE(0xf00)
1162 BAD_STACK_TRAMPOLINE(0xf20)
1163 
1164         .globl  bad_stack_book3e
1165 bad_stack_book3e:
1166         /* XXX: Needs to make SPRN_SPRG_GEN depend on exception type */
1167         mfspr   r10,SPRN_SRR0;            /* read SRR0 before touching stack */
1168         ld      r1,PACAEMERGSP(r13)
1169         subi    r1,r1,64+INT_FRAME_SIZE
1170         std     r10,_NIP(r1)
1171         std     r11,_MSR(r1)
1172         ld      r10,PACA_EXGEN+EX_R1(r13) /* FIXME for crit & mcheck */
1173         lwz     r11,PACA_EXGEN+EX_CR(r13) /* FIXME for crit & mcheck */
1174         std     r10,GPR1(r1)
1175         std     r11,_CCR(r1)
1176         mfspr   r10,SPRN_DEAR
1177         mfspr   r11,SPRN_ESR
1178         std     r10,_DAR(r1)
1179         std     r11,_DSISR(r1)
1180         std     r0,GPR0(r1);            /* save r0 in stackframe */         \
1181         std     r2,GPR2(r1);            /* save r2 in stackframe */         \
1182         SAVE_4GPRS(3, r1);              /* save r3 - r6 in stackframe */    \
1183         SAVE_2GPRS(7, r1);              /* save r7, r8 in stackframe */     \
1184         std     r9,GPR9(r1);            /* save r9 in stackframe */         \
1185         ld      r3,PACA_EXGEN+EX_R10(r13);/* get back r10 */                \
1186         ld      r4,PACA_EXGEN+EX_R11(r13);/* get back r11 */                \
1187         mfspr   r5,SPRN_SPRG_GEN_SCRATCH;/* get back r13 XXX can be wrong */ \
1188         std     r3,GPR10(r1);           /* save r10 to stackframe */        \
1189         std     r4,GPR11(r1);           /* save r11 to stackframe */        \
1190         std     r12,GPR12(r1);          /* save r12 in stackframe */        \
1191         std     r5,GPR13(r1);           /* save it to stackframe */         \
1192         mflr    r10
1193         mfctr   r11
1194         mfxer   r12
1195         std     r10,_LINK(r1)
1196         std     r11,_CTR(r1)
1197         std     r12,_XER(r1)
1198         SAVE_10GPRS(14,r1)
1199         SAVE_8GPRS(24,r1)
1200         lhz     r12,PACA_TRAP_SAVE(r13)
1201         std     r12,_TRAP(r1)
1202         addi    r11,r1,INT_FRAME_SIZE
1203         std     r11,0(r1)
1204         li      r12,0
1205         std     r12,0(r11)
1206         ld      r2,PACATOC(r13)
1207 1:      addi    r3,r1,STACK_FRAME_OVERHEAD
1208         bl      kernel_bad_stack
1209         b       1b
1210 
1211 /*
1212  * Setup the initial TLB for a core. This current implementation
1213  * assume that whatever we are running off will not conflict with
1214  * the new mapping at PAGE_OFFSET.
1215  */
1216 _GLOBAL(initial_tlb_book3e)
1217 
1218         /* Look for the first TLB with IPROT set */
1219         mfspr   r4,SPRN_TLB0CFG
1220         andi.   r3,r4,TLBnCFG_IPROT
1221         lis     r3,MAS0_TLBSEL(0)@h
1222         bne     found_iprot
1223 
1224         mfspr   r4,SPRN_TLB1CFG
1225         andi.   r3,r4,TLBnCFG_IPROT
1226         lis     r3,MAS0_TLBSEL(1)@h
1227         bne     found_iprot
1228 
1229         mfspr   r4,SPRN_TLB2CFG
1230         andi.   r3,r4,TLBnCFG_IPROT
1231         lis     r3,MAS0_TLBSEL(2)@h
1232         bne     found_iprot
1233 
1234         lis     r3,MAS0_TLBSEL(3)@h
1235         mfspr   r4,SPRN_TLB3CFG
1236         /* fall through */
1237 
1238 found_iprot:
1239         andi.   r5,r4,TLBnCFG_HES
1240         bne     have_hes
1241 
1242         mflr    r8                              /* save LR */
1243 /* 1. Find the index of the entry we're executing in
1244  *
1245  * r3 = MAS0_TLBSEL (for the iprot array)
1246  * r4 = SPRN_TLBnCFG
1247  */
1248         bl      invstr                          /* Find our address */
1249 invstr: mflr    r6                              /* Make it accessible */
1250         mfmsr   r7
1251         rlwinm  r5,r7,27,31,31                  /* extract MSR[IS] */
1252         mfspr   r7,SPRN_PID
1253         slwi    r7,r7,16
1254         or      r7,r7,r5
1255         mtspr   SPRN_MAS6,r7
1256         tlbsx   0,r6                            /* search MSR[IS], SPID=PID */
1257 
1258         mfspr   r3,SPRN_MAS0
1259         rlwinm  r5,r3,16,20,31                  /* Extract MAS0(Entry) */
1260 
1261         mfspr   r7,SPRN_MAS1                    /* Insure IPROT set */
1262         oris    r7,r7,MAS1_IPROT@h
1263         mtspr   SPRN_MAS1,r7
1264         tlbwe
1265 
1266 /* 2. Invalidate all entries except the entry we're executing in
1267  *
1268  * r3 = MAS0 w/TLBSEL & ESEL for the entry we are running in
1269  * r4 = SPRN_TLBnCFG
1270  * r5 = ESEL of entry we are running in
1271  */
1272         andi.   r4,r4,TLBnCFG_N_ENTRY           /* Extract # entries */
1273         li      r6,0                            /* Set Entry counter to 0 */
1274 1:      mr      r7,r3                           /* Set MAS0(TLBSEL) */
1275         rlwimi  r7,r6,16,4,15                   /* Setup MAS0 = TLBSEL | ESEL(r6) */
1276         mtspr   SPRN_MAS0,r7
1277         tlbre
1278         mfspr   r7,SPRN_MAS1
1279         rlwinm  r7,r7,0,2,31                    /* Clear MAS1 Valid and IPROT */
1280         cmpw    r5,r6
1281         beq     skpinv                          /* Dont update the current execution TLB */
1282         mtspr   SPRN_MAS1,r7
1283         tlbwe
1284         isync
1285 skpinv: addi    r6,r6,1                         /* Increment */
1286         cmpw    r6,r4                           /* Are we done? */
1287         bne     1b                              /* If not, repeat */
1288 
1289         /* Invalidate all TLBs */
1290         PPC_TLBILX_ALL(0,R0)
1291         sync
1292         isync
1293 
1294 /* 3. Setup a temp mapping and jump to it
1295  *
1296  * r3 = MAS0 w/TLBSEL & ESEL for the entry we are running in
1297  * r5 = ESEL of entry we are running in
1298  */
1299         andi.   r7,r5,0x1       /* Find an entry not used and is non-zero */
1300         addi    r7,r7,0x1
1301         mr      r4,r3           /* Set MAS0(TLBSEL) = 1 */
1302         mtspr   SPRN_MAS0,r4
1303         tlbre
1304 
1305         rlwimi  r4,r7,16,4,15   /* Setup MAS0 = TLBSEL | ESEL(r7) */
1306         mtspr   SPRN_MAS0,r4
1307 
1308         mfspr   r7,SPRN_MAS1
1309         xori    r6,r7,MAS1_TS           /* Setup TMP mapping in the other Address space */
1310         mtspr   SPRN_MAS1,r6
1311 
1312         tlbwe
1313 
1314         mfmsr   r6
1315         xori    r6,r6,MSR_IS
1316         mtspr   SPRN_SRR1,r6
1317         bl      1f              /* Find our address */
1318 1:      mflr    r6
1319         addi    r6,r6,(2f - 1b)
1320         mtspr   SPRN_SRR0,r6
1321         rfi
1322 2:
1323 
1324 /* 4. Clear out PIDs & Search info
1325  *
1326  * r3 = MAS0 w/TLBSEL & ESEL for the entry we started in
1327  * r4 = MAS0 w/TLBSEL & ESEL for the temp mapping
1328  * r5 = MAS3
1329  */
1330         li      r6,0
1331         mtspr   SPRN_MAS6,r6
1332         mtspr   SPRN_PID,r6
1333 
1334 /* 5. Invalidate mapping we started in
1335  *
1336  * r3 = MAS0 w/TLBSEL & ESEL for the entry we started in
1337  * r4 = MAS0 w/TLBSEL & ESEL for the temp mapping
1338  * r5 = MAS3
1339  */
1340         mtspr   SPRN_MAS0,r3
1341         tlbre
1342         mfspr   r6,SPRN_MAS1
1343         rlwinm  r6,r6,0,2,31    /* clear IPROT and VALID */
1344         mtspr   SPRN_MAS1,r6
1345         tlbwe
1346         sync
1347         isync
1348 
1349 /*
1350  * The mapping only needs to be cache-coherent on SMP, except on
1351  * Freescale e500mc derivatives where it's also needed for coherent DMA.
1352  */
1353 #if defined(CONFIG_SMP) || defined(CONFIG_PPC_E500MC)
1354 #define M_IF_NEEDED     MAS2_M
1355 #else
1356 #define M_IF_NEEDED     0
1357 #endif
1358 
1359 /* 6. Setup KERNELBASE mapping in TLB[0]
1360  *
1361  * r3 = MAS0 w/TLBSEL & ESEL for the entry we started in
1362  * r4 = MAS0 w/TLBSEL & ESEL for the temp mapping
1363  * r5 = MAS3
1364  */
1365         rlwinm  r3,r3,0,16,3    /* clear ESEL */
1366         mtspr   SPRN_MAS0,r3
1367         lis     r6,(MAS1_VALID|MAS1_IPROT)@h
1368         ori     r6,r6,(MAS1_TSIZE(BOOK3E_PAGESZ_1GB))@l
1369         mtspr   SPRN_MAS1,r6
1370 
1371         LOAD_REG_IMMEDIATE(r6, PAGE_OFFSET | M_IF_NEEDED)
1372         mtspr   SPRN_MAS2,r6
1373 
1374         rlwinm  r5,r5,0,0,25
1375         ori     r5,r5,MAS3_SR | MAS3_SW | MAS3_SX
1376         mtspr   SPRN_MAS3,r5
1377         li      r5,-1
1378         rlwinm  r5,r5,0,0,25
1379 
1380         tlbwe
1381 
1382 /* 7. Jump to KERNELBASE mapping
1383  *
1384  * r4 = MAS0 w/TLBSEL & ESEL for the temp mapping
1385  */
1386         /* Now we branch the new virtual address mapped by this entry */
1387         bl      1f              /* Find our address */
1388 1:      mflr    r6
1389         addi    r6,r6,(2f - 1b)
1390         tovirt(r6,r6)
1391         lis     r7,MSR_KERNEL@h
1392         ori     r7,r7,MSR_KERNEL@l
1393         mtspr   SPRN_SRR0,r6
1394         mtspr   SPRN_SRR1,r7
1395         rfi                             /* start execution out of TLB1[0] entry */
1396 2:
1397 
1398 /* 8. Clear out the temp mapping
1399  *
1400  * r4 = MAS0 w/TLBSEL & ESEL for the entry we are running in
1401  */
1402         mtspr   SPRN_MAS0,r4
1403         tlbre
1404         mfspr   r5,SPRN_MAS1
1405         rlwinm  r5,r5,0,2,31    /* clear IPROT and VALID */
1406         mtspr   SPRN_MAS1,r5
1407         tlbwe
1408         sync
1409         isync
1410 
1411         /* We translate LR and return */
1412         tovirt(r8,r8)
1413         mtlr    r8
1414         blr
1415 
1416 have_hes:
1417         /* Setup MAS 0,1,2,3 and 7 for tlbwe of a 1G entry that maps the
1418          * kernel linear mapping. We also set MAS8 once for all here though
1419          * that will have to be made dependent on whether we are running under
1420          * a hypervisor I suppose.
1421          */
1422 
1423         /* BEWARE, MAGIC
1424          * This code is called as an ordinary function on the boot CPU. But to
1425          * avoid duplication, this code is also used in SCOM bringup of
1426          * secondary CPUs. We read the code between the initial_tlb_code_start
1427          * and initial_tlb_code_end labels one instruction at a time and RAM it
1428          * into the new core via SCOM. That doesn't process branches, so there
1429          * must be none between those two labels. It also means if this code
1430          * ever takes any parameters, the SCOM code must also be updated to
1431          * provide them.
1432          */
1433         .globl a2_tlbinit_code_start
1434 a2_tlbinit_code_start:
1435 
1436         ori     r11,r3,MAS0_WQ_ALLWAYS
1437         oris    r11,r11,MAS0_ESEL(3)@h /* Use way 3: workaround A2 erratum 376 */
1438         mtspr   SPRN_MAS0,r11
1439         lis     r3,(MAS1_VALID | MAS1_IPROT)@h
1440         ori     r3,r3,BOOK3E_PAGESZ_1GB << MAS1_TSIZE_SHIFT
1441         mtspr   SPRN_MAS1,r3
1442         LOAD_REG_IMMEDIATE(r3, PAGE_OFFSET | MAS2_M)
1443         mtspr   SPRN_MAS2,r3
1444         li      r3,MAS3_SR | MAS3_SW | MAS3_SX
1445         mtspr   SPRN_MAS7_MAS3,r3
1446         li      r3,0
1447         mtspr   SPRN_MAS8,r3
1448 
1449         /* Write the TLB entry */
1450         tlbwe
1451 
1452         .globl a2_tlbinit_after_linear_map
1453 a2_tlbinit_after_linear_map:
1454 
1455         /* Now we branch the new virtual address mapped by this entry */
1456         LOAD_REG_IMMEDIATE_SYM(r3, r5, 1f)
1457         mtctr   r3
1458         bctr
1459 
1460 1:      /* We are now running at PAGE_OFFSET, clean the TLB of everything
1461          * else (including IPROTed things left by firmware)
1462          * r4 = TLBnCFG
1463          * r3 = current address (more or less)
1464          */
1465 
1466         li      r5,0
1467         mtspr   SPRN_MAS6,r5
1468         tlbsx   0,r3
1469 
1470         rlwinm  r9,r4,0,TLBnCFG_N_ENTRY
1471         rlwinm  r10,r4,8,0xff
1472         addi    r10,r10,-1      /* Get inner loop mask */
1473 
1474         li      r3,1
1475 
1476         mfspr   r5,SPRN_MAS1
1477         rlwinm  r5,r5,0,(~(MAS1_VALID|MAS1_IPROT))
1478 
1479         mfspr   r6,SPRN_MAS2
1480         rldicr  r6,r6,0,51              /* Extract EPN */
1481 
1482         mfspr   r7,SPRN_MAS0
1483         rlwinm  r7,r7,0,0xffff0fff      /* Clear HES and WQ */
1484 
1485         rlwinm  r8,r7,16,0xfff          /* Extract ESEL */
1486 
1487 2:      add     r4,r3,r8
1488         and     r4,r4,r10
1489 
1490         rlwimi  r7,r4,16,MAS0_ESEL_MASK
1491 
1492         mtspr   SPRN_MAS0,r7
1493         mtspr   SPRN_MAS1,r5
1494         mtspr   SPRN_MAS2,r6
1495         tlbwe
1496 
1497         addi    r3,r3,1
1498         and.    r4,r3,r10
1499 
1500         bne     3f
1501         addis   r6,r6,(1<<30)@h
1502 3:
1503         cmpw    r3,r9
1504         blt     2b
1505 
1506         .globl  a2_tlbinit_after_iprot_flush
1507 a2_tlbinit_after_iprot_flush:
1508 
1509         PPC_TLBILX(0,0,R0)
1510         sync
1511         isync
1512 
1513         .globl a2_tlbinit_code_end
1514 a2_tlbinit_code_end:
1515 
1516         /* We translate LR and return */
1517         mflr    r3
1518         tovirt(r3,r3)
1519         mtlr    r3
1520         blr
1521 
1522 /*
1523  * Main entry (boot CPU, thread 0)
1524  *
1525  * We enter here from head_64.S, possibly after the prom_init trampoline
1526  * with r3 and r4 already saved to r31 and 30 respectively and in 64 bits
1527  * mode. Anything else is as it was left by the bootloader
1528  *
1529  * Initial requirements of this port:
1530  *
1531  * - Kernel loaded at 0 physical
1532  * - A good lump of memory mapped 0:0 by UTLB entry 0
1533  * - MSR:IS & MSR:DS set to 0
1534  *
1535  * Note that some of the above requirements will be relaxed in the future
1536  * as the kernel becomes smarter at dealing with different initial conditions
1537  * but for now you have to be careful
1538  */
1539 _GLOBAL(start_initialization_book3e)
1540         mflr    r28
1541 
1542         /* First, we need to setup some initial TLBs to map the kernel
1543          * text, data and bss at PAGE_OFFSET. We don't have a real mode
1544          * and always use AS 0, so we just set it up to match our link
1545          * address and never use 0 based addresses.
1546          */
1547         bl      initial_tlb_book3e
1548 
1549         /* Init global core bits */
1550         bl      init_core_book3e
1551 
1552         /* Init per-thread bits */
1553         bl      init_thread_book3e
1554 
1555         /* Return to common init code */
1556         tovirt(r28,r28)
1557         mtlr    r28
1558         blr
1559 
1560 
1561 /*
1562  * Secondary core/processor entry
1563  *
1564  * This is entered for thread 0 of a secondary core, all other threads
1565  * are expected to be stopped. It's similar to start_initialization_book3e
1566  * except that it's generally entered from the holding loop in head_64.S
1567  * after CPUs have been gathered by Open Firmware.
1568  *
1569  * We assume we are in 32 bits mode running with whatever TLB entry was
1570  * set for us by the firmware or POR engine.
1571  */
1572 _GLOBAL(book3e_secondary_core_init_tlb_set)
1573         li      r4,1
1574         b       generic_secondary_smp_init
1575 
1576 _GLOBAL(book3e_secondary_core_init)
1577         mflr    r28
1578 
1579         /* Do we need to setup initial TLB entry ? */
1580         cmplwi  r4,0
1581         bne     2f
1582 
1583         /* Setup TLB for this core */
1584         bl      initial_tlb_book3e
1585 
1586         /* We can return from the above running at a different
1587          * address, so recalculate r2 (TOC)
1588          */
1589         bl      relative_toc
1590 
1591         /* Init global core bits */
1592 2:      bl      init_core_book3e
1593 
1594         /* Init per-thread bits */
1595 3:      bl      init_thread_book3e
1596 
1597         /* Return to common init code at proper virtual address.
1598          *
1599          * Due to various previous assumptions, we know we entered this
1600          * function at either the final PAGE_OFFSET mapping or using a
1601          * 1:1 mapping at 0, so we don't bother doing a complicated check
1602          * here, we just ensure the return address has the right top bits.
1603          *
1604          * Note that if we ever want to be smarter about where we can be
1605          * started from, we have to be careful that by the time we reach
1606          * the code below we may already be running at a different location
1607          * than the one we were called from since initial_tlb_book3e can
1608          * have moved us already.
1609          */
1610         cmpdi   cr0,r28,0
1611         blt     1f
1612         lis     r3,PAGE_OFFSET@highest
1613         sldi    r3,r3,32
1614         or      r28,r28,r3
1615 1:      mtlr    r28
1616         blr
1617 
1618 _GLOBAL(book3e_secondary_thread_init)
1619         mflr    r28
1620         b       3b
1621 
1622         .globl init_core_book3e
1623 init_core_book3e:
1624         /* Establish the interrupt vector base */
1625         tovirt(r2,r2)
1626         LOAD_REG_ADDR(r3, interrupt_base_book3e)
1627         mtspr   SPRN_IVPR,r3
1628         sync
1629         blr
1630 
1631 init_thread_book3e:
1632         lis     r3,(SPRN_EPCR_ICM | SPRN_EPCR_GICM)@h
1633         mtspr   SPRN_EPCR,r3
1634 
1635         /* Make sure interrupts are off */
1636         wrteei  0
1637 
1638         /* disable all timers and clear out status */
1639         li      r3,0
1640         mtspr   SPRN_TCR,r3
1641         mfspr   r3,SPRN_TSR
1642         mtspr   SPRN_TSR,r3
1643 
1644         blr
1645 
1646 _GLOBAL(__setup_base_ivors)
1647         SET_IVOR(0, 0x020) /* Critical Input */
1648         SET_IVOR(1, 0x000) /* Machine Check */
1649         SET_IVOR(2, 0x060) /* Data Storage */ 
1650         SET_IVOR(3, 0x080) /* Instruction Storage */
1651         SET_IVOR(4, 0x0a0) /* External Input */ 
1652         SET_IVOR(5, 0x0c0) /* Alignment */ 
1653         SET_IVOR(6, 0x0e0) /* Program */ 
1654         SET_IVOR(7, 0x100) /* FP Unavailable */ 
1655         SET_IVOR(8, 0x120) /* System Call */ 
1656         SET_IVOR(9, 0x140) /* Auxiliary Processor Unavailable */ 
1657         SET_IVOR(10, 0x160) /* Decrementer */ 
1658         SET_IVOR(11, 0x180) /* Fixed Interval Timer */ 
1659         SET_IVOR(12, 0x1a0) /* Watchdog Timer */ 
1660         SET_IVOR(13, 0x1c0) /* Data TLB Error */ 
1661         SET_IVOR(14, 0x1e0) /* Instruction TLB Error */
1662         SET_IVOR(15, 0x040) /* Debug */
1663 
1664         sync
1665 
1666         blr
1667 
1668 _GLOBAL(setup_altivec_ivors)
1669         SET_IVOR(32, 0x200) /* AltiVec Unavailable */
1670         SET_IVOR(33, 0x220) /* AltiVec Assist */
1671         blr
1672 
1673 _GLOBAL(setup_perfmon_ivor)
1674         SET_IVOR(35, 0x260) /* Performance Monitor */
1675         blr
1676 
1677 _GLOBAL(setup_doorbell_ivors)
1678         SET_IVOR(36, 0x280) /* Processor Doorbell */
1679         SET_IVOR(37, 0x2a0) /* Processor Doorbell Crit */
1680         blr
1681 
1682 _GLOBAL(setup_ehv_ivors)
1683         SET_IVOR(40, 0x300) /* Embedded Hypervisor System Call */
1684         SET_IVOR(41, 0x320) /* Embedded Hypervisor Privilege */
1685         SET_IVOR(38, 0x2c0) /* Guest Processor Doorbell */
1686         SET_IVOR(39, 0x2e0) /* Guest Processor Doorbell Crit/MC */
1687         blr
1688 
1689 _GLOBAL(setup_lrat_ivor)
1690         SET_IVOR(42, 0x340) /* LRAT Error */
1691         blr