root/include/drm/drm_scdc_helper.h

INCLUDED FROM

DEFINITIONS

1. drm_scdc_readb
2. drm_scdc_writeb

   1 /*
   2  * Copyright (c) 2015 NVIDIA Corporation. All rights reserved.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sub license,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the
  12  * next paragraph) shall be included in all copies or substantial portions
  13  * of the Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  21  * DEALINGS IN THE SOFTWARE.
  22  */
  23 
  24 #ifndef DRM_SCDC_HELPER_H
  25 #define DRM_SCDC_HELPER_H
  26 
  27 #include <linux/i2c.h>
  28 #include <linux/types.h>
  29 
  30 #define SCDC_SINK_VERSION 0x01
  31 
  32 #define SCDC_SOURCE_VERSION 0x02
  33 
  34 #define SCDC_UPDATE_0 0x10
  35 #define  SCDC_READ_REQUEST_TEST (1 << 2)
  36 #define  SCDC_CED_UPDATE (1 << 1)
  37 #define  SCDC_STATUS_UPDATE (1 << 0)
  38 
  39 #define SCDC_UPDATE_1 0x11
  40 
  41 #define SCDC_TMDS_CONFIG 0x20
  42 #define  SCDC_TMDS_BIT_CLOCK_RATIO_BY_40 (1 << 1)
  43 #define  SCDC_TMDS_BIT_CLOCK_RATIO_BY_10 (0 << 1)
  44 #define  SCDC_SCRAMBLING_ENABLE (1 << 0)
  45 
  46 #define SCDC_SCRAMBLER_STATUS 0x21
  47 #define  SCDC_SCRAMBLING_STATUS (1 << 0)
  48 
  49 #define SCDC_CONFIG_0 0x30
  50 #define  SCDC_READ_REQUEST_ENABLE (1 << 0)
  51 
  52 #define SCDC_STATUS_FLAGS_0 0x40
  53 #define  SCDC_CH2_LOCK (1 < 3)
  54 #define  SCDC_CH1_LOCK (1 < 2)
  55 #define  SCDC_CH0_LOCK (1 < 1)
  56 #define  SCDC_CH_LOCK_MASK (SCDC_CH2_LOCK | SCDC_CH1_LOCK | SCDC_CH0_LOCK)
  57 #define  SCDC_CLOCK_DETECT (1 << 0)
  58 
  59 #define SCDC_STATUS_FLAGS_1 0x41
  60 
  61 #define SCDC_ERR_DET_0_L 0x50
  62 #define SCDC_ERR_DET_0_H 0x51
  63 #define SCDC_ERR_DET_1_L 0x52
  64 #define SCDC_ERR_DET_1_H 0x53
  65 #define SCDC_ERR_DET_2_L 0x54
  66 #define SCDC_ERR_DET_2_H 0x55
  67 #define  SCDC_CHANNEL_VALID (1 << 7)
  68 
  69 #define SCDC_ERR_DET_CHECKSUM 0x56
  70 
  71 #define SCDC_TEST_CONFIG_0 0xc0
  72 #define  SCDC_TEST_READ_REQUEST (1 << 7)
  73 #define  SCDC_TEST_READ_REQUEST_DELAY(x) ((x) & 0x7f)
  74 
  75 #define SCDC_MANUFACTURER_IEEE_OUI 0xd0
  76 #define SCDC_MANUFACTURER_IEEE_OUI_SIZE 3
  77 
  78 #define SCDC_DEVICE_ID 0xd3
  79 #define SCDC_DEVICE_ID_SIZE 8
  80 
  81 #define SCDC_DEVICE_HARDWARE_REVISION 0xdb
  82 #define  SCDC_GET_DEVICE_HARDWARE_REVISION_MAJOR(x) (((x) >> 4) & 0xf)
  83 #define  SCDC_GET_DEVICE_HARDWARE_REVISION_MINOR(x) (((x) >> 0) & 0xf)
  84 
  85 #define SCDC_DEVICE_SOFTWARE_MAJOR_REVISION 0xdc
  86 #define SCDC_DEVICE_SOFTWARE_MINOR_REVISION 0xdd
  87 
  88 #define SCDC_MANUFACTURER_SPECIFIC 0xde
  89 #define SCDC_MANUFACTURER_SPECIFIC_SIZE 34
  90 
  91 ssize_t drm_scdc_read(struct i2c_adapter *adapter, u8 offset, void *buffer,
  92                       size_t size);
  93 ssize_t drm_scdc_write(struct i2c_adapter *adapter, u8 offset,
  94                        const void *buffer, size_t size);
  95 
  96 /**
  97  * drm_scdc_readb - read a single byte from SCDC
  98  * @adapter: I2C adapter
  99  * @offset: offset of register to read
 100  * @value: return location for the register value
 101  *
 102  * Reads a single byte from SCDC. This is a convenience wrapper around the
 103  * drm_scdc_read() function.
 104  *
 105  * Returns:
 106  * 0 on success or a negative error code on failure.
 107  */
 108 static inline int drm_scdc_readb(struct i2c_adapter *adapter, u8 offset,
 109                                  u8 *value)
 110 {
 111         return drm_scdc_read(adapter, offset, value, sizeof(*value));
 112 }
 113 
 114 /**
 115  * drm_scdc_writeb - write a single byte to SCDC
 116  * @adapter: I2C adapter
 117  * @offset: offset of register to read
 118  * @value: return location for the register value
 119  *
 120  * Writes a single byte to SCDC. This is a convenience wrapper around the
 121  * drm_scdc_write() function.
 122  *
 123  * Returns:
 124  * 0 on success or a negative error code on failure.
 125  */
 126 static inline int drm_scdc_writeb(struct i2c_adapter *adapter, u8 offset,
 127                                   u8 value)
 128 {
 129         return drm_scdc_write(adapter, offset, &value, sizeof(value));
 130 }
 131 
 132 bool drm_scdc_get_scrambling_status(struct i2c_adapter *adapter);
 133 
 134 bool drm_scdc_set_scrambling(struct i2c_adapter *adapter, bool enable);
 135 bool drm_scdc_set_high_tmds_clock_ratio(struct i2c_adapter *adapter, bool set);
 136 #endif