root/arch/powerpc/kernel/cpu_setup_power.S

   1 /* SPDX-License-Identifier: GPL-2.0-or-later */
   2 /*
   3  * This file contains low level CPU setup functions.
   4  *    Copyright (C) 2003 Benjamin Herrenschmidt (benh@kernel.crashing.org)
   5  */
   6 
   7 #include <asm/processor.h>
   8 #include <asm/page.h>
   9 #include <asm/cputable.h>
  10 #include <asm/ppc_asm.h>
  11 #include <asm/asm-offsets.h>
  12 #include <asm/cache.h>
  13 #include <asm/book3s/64/mmu-hash.h>
  14 
  15 /* Entry: r3 = crap, r4 = ptr to cputable entry
  16  *
  17  * Note that we can be called twice for pseudo-PVRs
  18  */
  19 _GLOBAL(__setup_cpu_power7)
  20         mflr    r11
  21         bl      __init_hvmode_206
  22         mtlr    r11
  23         beqlr
  24         li      r0,0
  25         mtspr   SPRN_LPID,r0
  26         LOAD_REG_IMMEDIATE(r0, PCR_MASK)
  27         mtspr   SPRN_PCR,r0
  28         mfspr   r3,SPRN_LPCR
  29         li      r4,(LPCR_LPES1 >> LPCR_LPES_SH)
  30         bl      __init_LPCR_ISA206
  31         mtlr    r11
  32         blr
  33 
  34 _GLOBAL(__restore_cpu_power7)
  35         mflr    r11
  36         mfmsr   r3
  37         rldicl. r0,r3,4,63
  38         beqlr
  39         li      r0,0
  40         mtspr   SPRN_LPID,r0
  41         LOAD_REG_IMMEDIATE(r0, PCR_MASK)
  42         mtspr   SPRN_PCR,r0
  43         mfspr   r3,SPRN_LPCR
  44         li      r4,(LPCR_LPES1 >> LPCR_LPES_SH)
  45         bl      __init_LPCR_ISA206
  46         mtlr    r11
  47         blr
  48 
  49 _GLOBAL(__setup_cpu_power8)
  50         mflr    r11
  51         bl      __init_FSCR
  52         bl      __init_PMU
  53         bl      __init_PMU_ISA207
  54         bl      __init_hvmode_206
  55         mtlr    r11
  56         beqlr
  57         li      r0,0
  58         mtspr   SPRN_LPID,r0
  59         LOAD_REG_IMMEDIATE(r0, PCR_MASK)
  60         mtspr   SPRN_PCR,r0
  61         mfspr   r3,SPRN_LPCR
  62         ori     r3, r3, LPCR_PECEDH
  63         li      r4,0 /* LPES = 0 */
  64         bl      __init_LPCR_ISA206
  65         bl      __init_HFSCR
  66         bl      __init_PMU_HV
  67         bl      __init_PMU_HV_ISA207
  68         mtlr    r11
  69         blr
  70 
  71 _GLOBAL(__restore_cpu_power8)
  72         mflr    r11
  73         bl      __init_FSCR
  74         bl      __init_PMU
  75         bl      __init_PMU_ISA207
  76         mfmsr   r3
  77         rldicl. r0,r3,4,63
  78         mtlr    r11
  79         beqlr
  80         li      r0,0
  81         mtspr   SPRN_LPID,r0
  82         LOAD_REG_IMMEDIATE(r0, PCR_MASK)
  83         mtspr   SPRN_PCR,r0
  84         mfspr   r3,SPRN_LPCR
  85         ori     r3, r3, LPCR_PECEDH
  86         li      r4,0 /* LPES = 0 */
  87         bl      __init_LPCR_ISA206
  88         bl      __init_HFSCR
  89         bl      __init_PMU_HV
  90         bl      __init_PMU_HV_ISA207
  91         mtlr    r11
  92         blr
  93 
  94 _GLOBAL(__setup_cpu_power9)
  95         mflr    r11
  96         bl      __init_FSCR
  97         bl      __init_PMU
  98         bl      __init_hvmode_206
  99         mtlr    r11
 100         beqlr
 101         li      r0,0
 102         mtspr   SPRN_PSSCR,r0
 103         mtspr   SPRN_LPID,r0
 104         mtspr   SPRN_PID,r0
 105         LOAD_REG_IMMEDIATE(r0, PCR_MASK)
 106         mtspr   SPRN_PCR,r0
 107         mfspr   r3,SPRN_LPCR
 108         LOAD_REG_IMMEDIATE(r4, LPCR_PECEDH | LPCR_PECE_HVEE | LPCR_HVICE  | LPCR_HEIC)
 109         or      r3, r3, r4
 110         LOAD_REG_IMMEDIATE(r4, LPCR_UPRT | LPCR_HR)
 111         andc    r3, r3, r4
 112         li      r4,0 /* LPES = 0 */
 113         bl      __init_LPCR_ISA300
 114         bl      __init_HFSCR
 115         bl      __init_PMU_HV
 116         mtlr    r11
 117         blr
 118 
 119 _GLOBAL(__restore_cpu_power9)
 120         mflr    r11
 121         bl      __init_FSCR
 122         bl      __init_PMU
 123         mfmsr   r3
 124         rldicl. r0,r3,4,63
 125         mtlr    r11
 126         beqlr
 127         li      r0,0
 128         mtspr   SPRN_PSSCR,r0
 129         mtspr   SPRN_LPID,r0
 130         mtspr   SPRN_PID,r0
 131         LOAD_REG_IMMEDIATE(r0, PCR_MASK)
 132         mtspr   SPRN_PCR,r0
 133         mfspr   r3,SPRN_LPCR
 134         LOAD_REG_IMMEDIATE(r4, LPCR_PECEDH | LPCR_PECE_HVEE | LPCR_HVICE | LPCR_HEIC)
 135         or      r3, r3, r4
 136         LOAD_REG_IMMEDIATE(r4, LPCR_UPRT | LPCR_HR)
 137         andc    r3, r3, r4
 138         li      r4,0 /* LPES = 0 */
 139         bl      __init_LPCR_ISA300
 140         bl      __init_HFSCR
 141         bl      __init_PMU_HV
 142         mtlr    r11
 143         blr
 144 
 145 __init_hvmode_206:
 146         /* Disable CPU_FTR_HVMODE and exit if MSR:HV is not set */
 147         mfmsr   r3
 148         rldicl. r0,r3,4,63
 149         bnelr
 150         ld      r5,CPU_SPEC_FEATURES(r4)
 151         LOAD_REG_IMMEDIATE(r6,CPU_FTR_HVMODE | CPU_FTR_P9_TM_HV_ASSIST)
 152         andc    r5,r5,r6
 153         std     r5,CPU_SPEC_FEATURES(r4)
 154         blr
 155 
 156 __init_LPCR_ISA206:
 157         /* Setup a sane LPCR:
 158          *   Called with initial LPCR in R3 and desired LPES 2-bit value in R4
 159          *
 160          *   LPES = 0b01 (HSRR0/1 used for 0x500)
 161          *   PECE = 0b111
 162          *   DPFD = 4
 163          *   HDICE = 0
 164          *   VC = 0b100 (VPM0=1, VPM1=0, ISL=0)
 165          *   VRMASD = 0b10000 (L=1, LP=00)
 166          *
 167          * Other bits untouched for now
 168          */
 169         li      r5,0x10
 170         rldimi  r3,r5, LPCR_VRMASD_SH, 64-LPCR_VRMASD_SH-5
 171 
 172         /* POWER9 has no VRMASD */
 173 __init_LPCR_ISA300:
 174         rldimi  r3,r4, LPCR_LPES_SH, 64-LPCR_LPES_SH-2
 175         ori     r3,r3,(LPCR_PECE0|LPCR_PECE1|LPCR_PECE2)
 176         li      r5,4
 177         rldimi  r3,r5, LPCR_DPFD_SH, 64-LPCR_DPFD_SH-3
 178         clrrdi  r3,r3,1         /* clear HDICE */
 179         li      r5,4
 180         rldimi  r3,r5, LPCR_VC_SH, 0
 181         mtspr   SPRN_LPCR,r3
 182         isync
 183         blr
 184 
 185 __init_FSCR:
 186         mfspr   r3,SPRN_FSCR
 187         ori     r3,r3,FSCR_TAR|FSCR_DSCR|FSCR_EBB
 188         mtspr   SPRN_FSCR,r3
 189         blr
 190 
 191 __init_HFSCR:
 192         mfspr   r3,SPRN_HFSCR
 193         ori     r3,r3,HFSCR_TAR|HFSCR_TM|HFSCR_BHRB|HFSCR_PM|\
 194                       HFSCR_DSCR|HFSCR_VECVSX|HFSCR_FP|HFSCR_EBB|HFSCR_MSGP
 195         mtspr   SPRN_HFSCR,r3
 196         blr
 197 
 198 __init_PMU_HV:
 199         li      r5,0
 200         mtspr   SPRN_MMCRC,r5
 201         blr
 202 
 203 __init_PMU_HV_ISA207:
 204         li      r5,0
 205         mtspr   SPRN_MMCRH,r5
 206         blr
 207 
 208 __init_PMU:
 209         li      r5,0
 210         mtspr   SPRN_MMCRA,r5
 211         mtspr   SPRN_MMCR0,r5
 212         mtspr   SPRN_MMCR1,r5
 213         mtspr   SPRN_MMCR2,r5
 214         blr
 215 
 216 __init_PMU_ISA207:
 217         li      r5,0
 218         mtspr   SPRN_MMCRS,r5
 219         blr