1 /* 2 * drivers/video/clgenfb.h - Cirrus Logic chipset constants 3 * 4 * Copyright 1999 Jeff Garzik <jgarzik@pobox.com> 5 * 6 * Original clgenfb author: Frank Neumann 7 * 8 * Based on retz3fb.c and clgen.c: 9 * Copyright (C) 1997 Jes Sorensen 10 * Copyright (C) 1996 Frank Neumann 11 * 12 *************************************************************** 13 * 14 * Format this code with GNU indent '-kr -i8 -pcs' options. 15 * 16 * This file is subject to the terms and conditions of the GNU General Public 17 * License. See the file COPYING in the main directory of this archive 18 * for more details. 19 * 20 */ 21 22 #ifndef __CLGENFB_H__ 23 #define __CLGENFB_H__ 24 25 /* OLD COMMENT: definitions for Piccolo/SD64 VGA controller chip */ 26 /* OLD COMMENT: these definitions might most of the time also work */ 27 /* OLD COMMENT: for other CL-GD542x/543x based boards.. */ 28 29 /*** External/General Registers ***/ 30 #define CL_POS102 0x102 /* POS102 register */ 31 #define CL_VSSM 0x46e8 /* Adapter Sleep */ 32 #define CL_VSSM2 0x3c3 /* Motherboard Sleep */ 33 34 /*** VGA Sequencer Registers ***/ 35 /* the following are from the "extension registers" group */ 36 #define CL_SEQR6 0x6 /* Unlock ALL Extensions */ 37 #define CL_SEQR7 0x7 /* Extended Sequencer Mode */ 38 #define CL_SEQR8 0x8 /* EEPROM Control */ 39 #define CL_SEQR9 0x9 /* Scratch Pad 0 (do not access!) */ 40 #define CL_SEQRA 0xa /* Scratch Pad 1 (do not access!) */ 41 #define CL_SEQRB 0xb /* VCLK0 Numerator */ 42 #define CL_SEQRC 0xc /* VCLK1 Numerator */ 43 #define CL_SEQRD 0xd /* VCLK2 Numerator */ 44 #define CL_SEQRE 0xe /* VCLK3 Numerator */ 45 #define CL_SEQRF 0xf /* DRAM Control */ 46 #define CL_SEQR10 0x10 /* Graphics Cursor X Position */ 47 #define CL_SEQR11 0x11 /* Graphics Cursor Y Position */ 48 #define CL_SEQR12 0x12 /* Graphics Cursor Attributes */ 49 #define CL_SEQR13 0x13 /* Graphics Cursor Pattern Address Offset */ 50 #define CL_SEQR14 0x14 /* Scratch Pad 2 (CL-GD5426/'28 Only) (do not access!) */ 51 #define CL_SEQR15 0x15 /* Scratch Pad 3 (CL-GD5426/'28 Only) (do not access!) */ 52 #define CL_SEQR16 0x16 /* Performance Tuning (CL-GD5424/'26/'28 Only) */ 53 #define CL_SEQR17 0x17 /* Configuration ReadBack and Extended Control (CL-GF5428 Only) */ 54 #define CL_SEQR18 0x18 /* Signature Generator Control (Not CL-GD5420) */ 55 #define CL_SEQR19 0x19 /* Signature Generator Result Low Byte (Not CL-GD5420) */ 56 #define CL_SEQR1A 0x1a /* Signature Generator Result High Byte (Not CL-GD5420) */ 57 #define CL_SEQR1B 0x1b /* VCLK0 Denominator and Post-Scalar Value */ 58 #define CL_SEQR1C 0x1c /* VCLK1 Denominator and Post-Scalar Value */ 59 #define CL_SEQR1D 0x1d /* VCLK2 Denominator and Post-Scalar Value */ 60 #define CL_SEQR1E 0x1e /* VCLK3 Denominator and Post-Scalar Value */ 61 #define CL_SEQR1F 0x1f /* BIOS ROM write enable and MCLK Select */ 62 63 /*** CRT Controller Registers ***/ 64 #define CL_CRT22 0x22 /* Graphics Data Latches ReadBack */ 65 #define CL_CRT24 0x24 /* Attribute Controller Toggle ReadBack */ 66 #define CL_CRT26 0x26 /* Attribute Controller Index ReadBack */ 67 /* the following are from the "extension registers" group */ 68 #define CL_CRT19 0x19 /* Interlace End */ 69 #define CL_CRT1A 0x1a /* Interlace Control */ 70 #define CL_CRT1B 0x1b /* Extended Display Controls */ 71 #define CL_CRT1C 0x1c /* Sync adjust and genlock register */ 72 #define CL_CRT1D 0x1d /* Overlay Extended Control register */ 73 #define CL_CRT1E 0x1e /* Another overflow register */ 74 #define CL_CRT25 0x25 /* Part Status Register */ 75 #define CL_CRT27 0x27 /* ID Register */ 76 #define CL_CRT51 0x51 /* P4 disable "flicker fixer" */ 77 78 /*** Graphics Controller Registers ***/ 79 /* the following are from the "extension registers" group */ 80 #define CL_GR9 0x9 /* Offset Register 0 */ 81 #define CL_GRA 0xa /* Offset Register 1 */ 82 #define CL_GRB 0xb /* Graphics Controller Mode Extensions */ 83 #define CL_GRC 0xc /* Color Key (CL-GD5424/'26/'28 Only) */ 84 #define CL_GRD 0xd /* Color Key Mask (CL-GD5424/'26/'28 Only) */ 85 #define CL_GRE 0xe /* Miscellaneous Control (Cl-GD5428 Only) */ 86 #define CL_GRF 0xf /* Display Compression Control register */ 87 #define CL_GR10 0x10 /* 16-bit Pixel BG Color High Byte (Not CL-GD5420) */ 88 #define CL_GR11 0x11 /* 16-bit Pixel FG Color High Byte (Not CL-GD5420) */ 89 #define CL_GR12 0x12 /* Background Color Byte 2 Register */ 90 #define CL_GR13 0x13 /* Foreground Color Byte 2 Register */ 91 #define CL_GR14 0x14 /* Background Color Byte 3 Register */ 92 #define CL_GR15 0x15 /* Foreground Color Byte 3 Register */ 93 /* the following are CL-GD5426/'28 specific blitter registers */ 94 #define CL_GR20 0x20 /* BLT Width Low */ 95 #define CL_GR21 0x21 /* BLT Width High */ 96 #define CL_GR22 0x22 /* BLT Height Low */ 97 #define CL_GR23 0x23 /* BLT Height High */ 98 #define CL_GR24 0x24 /* BLT Destination Pitch Low */ 99 #define CL_GR25 0x25 /* BLT Destination Pitch High */ 100 #define CL_GR26 0x26 /* BLT Source Pitch Low */ 101 #define CL_GR27 0x27 /* BLT Source Pitch High */ 102 #define CL_GR28 0x28 /* BLT Destination Start Low */ 103 #define CL_GR29 0x29 /* BLT Destination Start Mid */ 104 #define CL_GR2A 0x2a /* BLT Destination Start High */ 105 #define CL_GR2C 0x2c /* BLT Source Start Low */ 106 #define CL_GR2D 0x2d /* BLT Source Start Mid */ 107 #define CL_GR2E 0x2e /* BLT Source Start High */ 108 #define CL_GR2F 0x2f /* Picasso IV Blitter compat mode..? */ 109 #define CL_GR30 0x30 /* BLT Mode */ 110 #define CL_GR31 0x31 /* BLT Start/Status */ 111 #define CL_GR32 0x32 /* BLT Raster Operation */ 112 #define CL_GR33 0x33 /* another P4 "compat" register.. */ 113 #define CL_GR34 0x34 /* Transparent Color Select Low */ 114 #define CL_GR35 0x35 /* Transparent Color Select High */ 115 #define CL_GR38 0x38 /* Source Transparent Color Mask Low */ 116 #define CL_GR39 0x39 /* Source Transparent Color Mask High */ 117 118 /*** Attribute Controller Registers ***/ 119 #define CL_AR33 0x33 /* The "real" Pixel Panning register (?) */ 120 #define CL_AR34 0x34 /* TEST */ 121 122 #endif /* __CLGENFB_H__ */