root/include/uapi/rdma/mlx5-abi.h

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   1 /* SPDX-License-Identifier: ((GPL-2.0 WITH Linux-syscall-note) OR Linux-OpenIB) */
   2 /*
   3  * Copyright (c) 2013-2015, Mellanox Technologies. All rights reserved.
   4  *
   5  * This software is available to you under a choice of one of two
   6  * licenses.  You may choose to be licensed under the terms of the GNU
   7  * General Public License (GPL) Version 2, available from the file
   8  * COPYING in the main directory of this source tree, or the
   9  * OpenIB.org BSD license below:
  10  *
  11  *     Redistribution and use in source and binary forms, with or
  12  *     without modification, are permitted provided that the following
  13  *     conditions are met:
  14  *
  15  *      - Redistributions of source code must retain the above
  16  *        copyright notice, this list of conditions and the following
  17  *        disclaimer.
  18  *
  19  *      - Redistributions in binary form must reproduce the above
  20  *        copyright notice, this list of conditions and the following
  21  *        disclaimer in the documentation and/or other materials
  22  *        provided with the distribution.
  23  *
  24  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  25  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  26  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  27  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  28  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  29  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  30  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  31  * SOFTWARE.
  32  */
  33 
  34 #ifndef MLX5_ABI_USER_H
  35 #define MLX5_ABI_USER_H
  36 
  37 #include <linux/types.h>
  38 #include <linux/if_ether.h>     /* For ETH_ALEN. */
  39 #include <rdma/ib_user_ioctl_verbs.h>
  40 
  41 enum {
  42         MLX5_QP_FLAG_SIGNATURE          = 1 << 0,
  43         MLX5_QP_FLAG_SCATTER_CQE        = 1 << 1,
  44         MLX5_QP_FLAG_TUNNEL_OFFLOADS    = 1 << 2,
  45         MLX5_QP_FLAG_BFREG_INDEX        = 1 << 3,
  46         MLX5_QP_FLAG_TYPE_DCT           = 1 << 4,
  47         MLX5_QP_FLAG_TYPE_DCI           = 1 << 5,
  48         MLX5_QP_FLAG_TIR_ALLOW_SELF_LB_UC = 1 << 6,
  49         MLX5_QP_FLAG_TIR_ALLOW_SELF_LB_MC = 1 << 7,
  50         MLX5_QP_FLAG_ALLOW_SCATTER_CQE  = 1 << 8,
  51         MLX5_QP_FLAG_PACKET_BASED_CREDIT_MODE   = 1 << 9,
  52 };
  53 
  54 enum {
  55         MLX5_SRQ_FLAG_SIGNATURE         = 1 << 0,
  56 };
  57 
  58 enum {
  59         MLX5_WQ_FLAG_SIGNATURE          = 1 << 0,
  60 };
  61 
  62 /* Increment this value if any changes that break userspace ABI
  63  * compatibility are made.
  64  */
  65 #define MLX5_IB_UVERBS_ABI_VERSION      1
  66 
  67 /* Make sure that all structs defined in this file remain laid out so
  68  * that they pack the same way on 32-bit and 64-bit architectures (to
  69  * avoid incompatibility between 32-bit userspace and 64-bit kernels).
  70  * In particular do not use pointer types -- pass pointers in __u64
  71  * instead.
  72  */
  73 
  74 struct mlx5_ib_alloc_ucontext_req {
  75         __u32   total_num_bfregs;
  76         __u32   num_low_latency_bfregs;
  77 };
  78 
  79 enum mlx5_lib_caps {
  80         MLX5_LIB_CAP_4K_UAR     = (__u64)1 << 0,
  81 };
  82 
  83 enum mlx5_ib_alloc_uctx_v2_flags {
  84         MLX5_IB_ALLOC_UCTX_DEVX = 1 << 0,
  85 };
  86 struct mlx5_ib_alloc_ucontext_req_v2 {
  87         __u32   total_num_bfregs;
  88         __u32   num_low_latency_bfregs;
  89         __u32   flags;
  90         __u32   comp_mask;
  91         __u8    max_cqe_version;
  92         __u8    reserved0;
  93         __u16   reserved1;
  94         __u32   reserved2;
  95         __aligned_u64 lib_caps;
  96 };
  97 
  98 enum mlx5_ib_alloc_ucontext_resp_mask {
  99         MLX5_IB_ALLOC_UCONTEXT_RESP_MASK_CORE_CLOCK_OFFSET = 1UL << 0,
 100         MLX5_IB_ALLOC_UCONTEXT_RESP_MASK_DUMP_FILL_MKEY    = 1UL << 1,
 101 };
 102 
 103 enum mlx5_user_cmds_supp_uhw {
 104         MLX5_USER_CMDS_SUPP_UHW_QUERY_DEVICE = 1 << 0,
 105         MLX5_USER_CMDS_SUPP_UHW_CREATE_AH    = 1 << 1,
 106 };
 107 
 108 /* The eth_min_inline response value is set to off-by-one vs the FW
 109  * returned value to allow user-space to deal with older kernels.
 110  */
 111 enum mlx5_user_inline_mode {
 112         MLX5_USER_INLINE_MODE_NA,
 113         MLX5_USER_INLINE_MODE_NONE,
 114         MLX5_USER_INLINE_MODE_L2,
 115         MLX5_USER_INLINE_MODE_IP,
 116         MLX5_USER_INLINE_MODE_TCP_UDP,
 117 };
 118 
 119 enum {
 120         MLX5_USER_ALLOC_UCONTEXT_FLOW_ACTION_FLAGS_ESP_AES_GCM = 1 << 0,
 121         MLX5_USER_ALLOC_UCONTEXT_FLOW_ACTION_FLAGS_ESP_AES_GCM_REQ_METADATA = 1 << 1,
 122         MLX5_USER_ALLOC_UCONTEXT_FLOW_ACTION_FLAGS_ESP_AES_GCM_SPI_STEERING = 1 << 2,
 123         MLX5_USER_ALLOC_UCONTEXT_FLOW_ACTION_FLAGS_ESP_AES_GCM_FULL_OFFLOAD = 1 << 3,
 124         MLX5_USER_ALLOC_UCONTEXT_FLOW_ACTION_FLAGS_ESP_AES_GCM_TX_IV_IS_ESN = 1 << 4,
 125 };
 126 
 127 struct mlx5_ib_alloc_ucontext_resp {
 128         __u32   qp_tab_size;
 129         __u32   bf_reg_size;
 130         __u32   tot_bfregs;
 131         __u32   cache_line_size;
 132         __u16   max_sq_desc_sz;
 133         __u16   max_rq_desc_sz;
 134         __u32   max_send_wqebb;
 135         __u32   max_recv_wr;
 136         __u32   max_srq_recv_wr;
 137         __u16   num_ports;
 138         __u16   flow_action_flags;
 139         __u32   comp_mask;
 140         __u32   response_length;
 141         __u8    cqe_version;
 142         __u8    cmds_supp_uhw;
 143         __u8    eth_min_inline;
 144         __u8    clock_info_versions;
 145         __aligned_u64 hca_core_clock_offset;
 146         __u32   log_uar_size;
 147         __u32   num_uars_per_page;
 148         __u32   num_dyn_bfregs;
 149         __u32   dump_fill_mkey;
 150 };
 151 
 152 struct mlx5_ib_alloc_pd_resp {
 153         __u32   pdn;
 154 };
 155 
 156 struct mlx5_ib_tso_caps {
 157         __u32 max_tso; /* Maximum tso payload size in bytes */
 158 
 159         /* Corresponding bit will be set if qp type from
 160          * 'enum ib_qp_type' is supported, e.g.
 161          * supported_qpts |= 1 << IB_QPT_UD
 162          */
 163         __u32 supported_qpts;
 164 };
 165 
 166 struct mlx5_ib_rss_caps {
 167         __aligned_u64 rx_hash_fields_mask; /* enum mlx5_rx_hash_fields */
 168         __u8 rx_hash_function; /* enum mlx5_rx_hash_function_flags */
 169         __u8 reserved[7];
 170 };
 171 
 172 enum mlx5_ib_cqe_comp_res_format {
 173         MLX5_IB_CQE_RES_FORMAT_HASH     = 1 << 0,
 174         MLX5_IB_CQE_RES_FORMAT_CSUM     = 1 << 1,
 175         MLX5_IB_CQE_RES_FORMAT_CSUM_STRIDX = 1 << 2,
 176 };
 177 
 178 struct mlx5_ib_cqe_comp_caps {
 179         __u32 max_num;
 180         __u32 supported_format; /* enum mlx5_ib_cqe_comp_res_format */
 181 };
 182 
 183 enum mlx5_ib_packet_pacing_cap_flags {
 184         MLX5_IB_PP_SUPPORT_BURST        = 1 << 0,
 185 };
 186 
 187 struct mlx5_packet_pacing_caps {
 188         __u32 qp_rate_limit_min;
 189         __u32 qp_rate_limit_max; /* In kpbs */
 190 
 191         /* Corresponding bit will be set if qp type from
 192          * 'enum ib_qp_type' is supported, e.g.
 193          * supported_qpts |= 1 << IB_QPT_RAW_PACKET
 194          */
 195         __u32 supported_qpts;
 196         __u8  cap_flags; /* enum mlx5_ib_packet_pacing_cap_flags */
 197         __u8  reserved[3];
 198 };
 199 
 200 enum mlx5_ib_mpw_caps {
 201         MPW_RESERVED            = 1 << 0,
 202         MLX5_IB_ALLOW_MPW       = 1 << 1,
 203         MLX5_IB_SUPPORT_EMPW    = 1 << 2,
 204 };
 205 
 206 enum mlx5_ib_sw_parsing_offloads {
 207         MLX5_IB_SW_PARSING = 1 << 0,
 208         MLX5_IB_SW_PARSING_CSUM = 1 << 1,
 209         MLX5_IB_SW_PARSING_LSO = 1 << 2,
 210 };
 211 
 212 struct mlx5_ib_sw_parsing_caps {
 213         __u32 sw_parsing_offloads; /* enum mlx5_ib_sw_parsing_offloads */
 214 
 215         /* Corresponding bit will be set if qp type from
 216          * 'enum ib_qp_type' is supported, e.g.
 217          * supported_qpts |= 1 << IB_QPT_RAW_PACKET
 218          */
 219         __u32 supported_qpts;
 220 };
 221 
 222 struct mlx5_ib_striding_rq_caps {
 223         __u32 min_single_stride_log_num_of_bytes;
 224         __u32 max_single_stride_log_num_of_bytes;
 225         __u32 min_single_wqe_log_num_of_strides;
 226         __u32 max_single_wqe_log_num_of_strides;
 227 
 228         /* Corresponding bit will be set if qp type from
 229          * 'enum ib_qp_type' is supported, e.g.
 230          * supported_qpts |= 1 << IB_QPT_RAW_PACKET
 231          */
 232         __u32 supported_qpts;
 233         __u32 reserved;
 234 };
 235 
 236 enum mlx5_ib_query_dev_resp_flags {
 237         /* Support 128B CQE compression */
 238         MLX5_IB_QUERY_DEV_RESP_FLAGS_CQE_128B_COMP = 1 << 0,
 239         MLX5_IB_QUERY_DEV_RESP_FLAGS_CQE_128B_PAD  = 1 << 1,
 240         MLX5_IB_QUERY_DEV_RESP_PACKET_BASED_CREDIT_MODE = 1 << 2,
 241         MLX5_IB_QUERY_DEV_RESP_FLAGS_SCAT2CQE_DCT = 1 << 3,
 242 };
 243 
 244 enum mlx5_ib_tunnel_offloads {
 245         MLX5_IB_TUNNELED_OFFLOADS_VXLAN  = 1 << 0,
 246         MLX5_IB_TUNNELED_OFFLOADS_GRE    = 1 << 1,
 247         MLX5_IB_TUNNELED_OFFLOADS_GENEVE = 1 << 2,
 248         MLX5_IB_TUNNELED_OFFLOADS_MPLS_GRE = 1 << 3,
 249         MLX5_IB_TUNNELED_OFFLOADS_MPLS_UDP = 1 << 4,
 250 };
 251 
 252 struct mlx5_ib_query_device_resp {
 253         __u32   comp_mask;
 254         __u32   response_length;
 255         struct  mlx5_ib_tso_caps tso_caps;
 256         struct  mlx5_ib_rss_caps rss_caps;
 257         struct  mlx5_ib_cqe_comp_caps cqe_comp_caps;
 258         struct  mlx5_packet_pacing_caps packet_pacing_caps;
 259         __u32   mlx5_ib_support_multi_pkt_send_wqes;
 260         __u32   flags; /* Use enum mlx5_ib_query_dev_resp_flags */
 261         struct mlx5_ib_sw_parsing_caps sw_parsing_caps;
 262         struct mlx5_ib_striding_rq_caps striding_rq_caps;
 263         __u32   tunnel_offloads_caps; /* enum mlx5_ib_tunnel_offloads */
 264         __u32   reserved;
 265 };
 266 
 267 enum mlx5_ib_create_cq_flags {
 268         MLX5_IB_CREATE_CQ_FLAGS_CQE_128B_PAD    = 1 << 0,
 269 };
 270 
 271 struct mlx5_ib_create_cq {
 272         __aligned_u64 buf_addr;
 273         __aligned_u64 db_addr;
 274         __u32   cqe_size;
 275         __u8    cqe_comp_en;
 276         __u8    cqe_comp_res_format;
 277         __u16   flags;
 278 };
 279 
 280 struct mlx5_ib_create_cq_resp {
 281         __u32   cqn;
 282         __u32   reserved;
 283 };
 284 
 285 struct mlx5_ib_resize_cq {
 286         __aligned_u64 buf_addr;
 287         __u16   cqe_size;
 288         __u16   reserved0;
 289         __u32   reserved1;
 290 };
 291 
 292 struct mlx5_ib_create_srq {
 293         __aligned_u64 buf_addr;
 294         __aligned_u64 db_addr;
 295         __u32   flags;
 296         __u32   reserved0; /* explicit padding (optional on i386) */
 297         __u32   uidx;
 298         __u32   reserved1;
 299 };
 300 
 301 struct mlx5_ib_create_srq_resp {
 302         __u32   srqn;
 303         __u32   reserved;
 304 };
 305 
 306 struct mlx5_ib_create_qp {
 307         __aligned_u64 buf_addr;
 308         __aligned_u64 db_addr;
 309         __u32   sq_wqe_count;
 310         __u32   rq_wqe_count;
 311         __u32   rq_wqe_shift;
 312         __u32   flags;
 313         __u32   uidx;
 314         __u32   bfreg_index;
 315         union {
 316                 __aligned_u64 sq_buf_addr;
 317                 __aligned_u64 access_key;
 318         };
 319 };
 320 
 321 /* RX Hash function flags */
 322 enum mlx5_rx_hash_function_flags {
 323         MLX5_RX_HASH_FUNC_TOEPLITZ      = 1 << 0,
 324 };
 325 
 326 /*
 327  * RX Hash flags, these flags allows to set which incoming packet's field should
 328  * participates in RX Hash. Each flag represent certain packet's field,
 329  * when the flag is set the field that is represented by the flag will
 330  * participate in RX Hash calculation.
 331  * Note: *IPV4 and *IPV6 flags can't be enabled together on the same QP
 332  * and *TCP and *UDP flags can't be enabled together on the same QP.
 333 */
 334 enum mlx5_rx_hash_fields {
 335         MLX5_RX_HASH_SRC_IPV4   = 1 << 0,
 336         MLX5_RX_HASH_DST_IPV4   = 1 << 1,
 337         MLX5_RX_HASH_SRC_IPV6   = 1 << 2,
 338         MLX5_RX_HASH_DST_IPV6   = 1 << 3,
 339         MLX5_RX_HASH_SRC_PORT_TCP       = 1 << 4,
 340         MLX5_RX_HASH_DST_PORT_TCP       = 1 << 5,
 341         MLX5_RX_HASH_SRC_PORT_UDP       = 1 << 6,
 342         MLX5_RX_HASH_DST_PORT_UDP       = 1 << 7,
 343         MLX5_RX_HASH_IPSEC_SPI          = 1 << 8,
 344         /* Save bits for future fields */
 345         MLX5_RX_HASH_INNER              = (1UL << 31),
 346 };
 347 
 348 struct mlx5_ib_create_qp_rss {
 349         __aligned_u64 rx_hash_fields_mask; /* enum mlx5_rx_hash_fields */
 350         __u8 rx_hash_function; /* enum mlx5_rx_hash_function_flags */
 351         __u8 rx_key_len; /* valid only for Toeplitz */
 352         __u8 reserved[6];
 353         __u8 rx_hash_key[128]; /* valid only for Toeplitz */
 354         __u32   comp_mask;
 355         __u32   flags;
 356 };
 357 
 358 enum mlx5_ib_create_qp_resp_mask {
 359         MLX5_IB_CREATE_QP_RESP_MASK_TIRN = 1UL << 0,
 360         MLX5_IB_CREATE_QP_RESP_MASK_TISN = 1UL << 1,
 361         MLX5_IB_CREATE_QP_RESP_MASK_RQN  = 1UL << 2,
 362         MLX5_IB_CREATE_QP_RESP_MASK_SQN  = 1UL << 3,
 363         MLX5_IB_CREATE_QP_RESP_MASK_TIR_ICM_ADDR  = 1UL << 4,
 364 };
 365 
 366 struct mlx5_ib_create_qp_resp {
 367         __u32   bfreg_index;
 368         __u32   reserved;
 369         __u32   comp_mask;
 370         __u32   tirn;
 371         __u32   tisn;
 372         __u32   rqn;
 373         __u32   sqn;
 374         __u32   reserved1;
 375         __u64   tir_icm_addr;
 376 };
 377 
 378 struct mlx5_ib_alloc_mw {
 379         __u32   comp_mask;
 380         __u8    num_klms;
 381         __u8    reserved1;
 382         __u16   reserved2;
 383 };
 384 
 385 enum mlx5_ib_create_wq_mask {
 386         MLX5_IB_CREATE_WQ_STRIDING_RQ   = (1 << 0),
 387 };
 388 
 389 struct mlx5_ib_create_wq {
 390         __aligned_u64 buf_addr;
 391         __aligned_u64 db_addr;
 392         __u32   rq_wqe_count;
 393         __u32   rq_wqe_shift;
 394         __u32   user_index;
 395         __u32   flags;
 396         __u32   comp_mask;
 397         __u32   single_stride_log_num_of_bytes;
 398         __u32   single_wqe_log_num_of_strides;
 399         __u32   two_byte_shift_en;
 400 };
 401 
 402 struct mlx5_ib_create_ah_resp {
 403         __u32   response_length;
 404         __u8    dmac[ETH_ALEN];
 405         __u8    reserved[6];
 406 };
 407 
 408 struct mlx5_ib_burst_info {
 409         __u32       max_burst_sz;
 410         __u16       typical_pkt_sz;
 411         __u16       reserved;
 412 };
 413 
 414 struct mlx5_ib_modify_qp {
 415         __u32                      comp_mask;
 416         struct mlx5_ib_burst_info  burst_info;
 417         __u32                      reserved;
 418 };
 419 
 420 struct mlx5_ib_modify_qp_resp {
 421         __u32   response_length;
 422         __u32   dctn;
 423 };
 424 
 425 struct mlx5_ib_create_wq_resp {
 426         __u32   response_length;
 427         __u32   reserved;
 428 };
 429 
 430 struct mlx5_ib_create_rwq_ind_tbl_resp {
 431         __u32   response_length;
 432         __u32   reserved;
 433 };
 434 
 435 struct mlx5_ib_modify_wq {
 436         __u32   comp_mask;
 437         __u32   reserved;
 438 };
 439 
 440 struct mlx5_ib_clock_info {
 441         __u32 sign;
 442         __u32 resv;
 443         __aligned_u64 nsec;
 444         __aligned_u64 cycles;
 445         __aligned_u64 frac;
 446         __u32 mult;
 447         __u32 shift;
 448         __aligned_u64 mask;
 449         __aligned_u64 overflow_period;
 450 };
 451 
 452 enum mlx5_ib_mmap_cmd {
 453         MLX5_IB_MMAP_REGULAR_PAGE               = 0,
 454         MLX5_IB_MMAP_GET_CONTIGUOUS_PAGES       = 1,
 455         MLX5_IB_MMAP_WC_PAGE                    = 2,
 456         MLX5_IB_MMAP_NC_PAGE                    = 3,
 457         /* 5 is chosen in order to be compatible with old versions of libmlx5 */
 458         MLX5_IB_MMAP_CORE_CLOCK                 = 5,
 459         MLX5_IB_MMAP_ALLOC_WC                   = 6,
 460         MLX5_IB_MMAP_CLOCK_INFO                 = 7,
 461         MLX5_IB_MMAP_DEVICE_MEM                 = 8,
 462 };
 463 
 464 enum {
 465         MLX5_IB_CLOCK_INFO_KERNEL_UPDATING = 1,
 466 };
 467 
 468 /* Bit indexes for the mlx5_alloc_ucontext_resp.clock_info_versions bitmap */
 469 enum {
 470         MLX5_IB_CLOCK_INFO_V1              = 0,
 471 };
 472 
 473 struct mlx5_ib_flow_counters_desc {
 474         __u32   description;
 475         __u32   index;
 476 };
 477 
 478 struct mlx5_ib_flow_counters_data {
 479         RDMA_UAPI_PTR(struct mlx5_ib_flow_counters_desc *, counters_data);
 480         __u32   ncounters;
 481         __u32   reserved;
 482 };
 483 
 484 struct mlx5_ib_create_flow {
 485         __u32   ncounters_data;
 486         __u32   reserved;
 487         /*
 488          * Following are counters data based on ncounters_data, each
 489          * entry in the data[] should match a corresponding counter object
 490          * that was pointed by a counters spec upon the flow creation
 491          */
 492         struct mlx5_ib_flow_counters_data data[];
 493 };
 494 
 495 #endif /* MLX5_ABI_USER_H */
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