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8 #ifndef _UAPI_HDLCDRV_H
9 #define _UAPI_HDLCDRV_H
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16 struct hdlcdrv_params {
17 int iobase;
18 int irq;
19 int dma;
20 int dma2;
21 int seriobase;
22 int pariobase;
23 int midiiobase;
24 };
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26 struct hdlcdrv_channel_params {
27 int tx_delay;
28 int tx_tail;
29 int slottime;
30 int ppersist;
31 int fulldup;
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33 };
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35 struct hdlcdrv_old_channel_state {
36 int ptt;
37 int dcd;
38 int ptt_keyed;
39 };
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41 struct hdlcdrv_channel_state {
42 int ptt;
43 int dcd;
44 int ptt_keyed;
45 unsigned long tx_packets;
46 unsigned long tx_errors;
47 unsigned long rx_packets;
48 unsigned long rx_errors;
49 };
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51 struct hdlcdrv_ioctl {
52 int cmd;
53 union {
54 struct hdlcdrv_params mp;
55 struct hdlcdrv_channel_params cp;
56 struct hdlcdrv_channel_state cs;
57 struct hdlcdrv_old_channel_state ocs;
58 unsigned int calibrate;
59 unsigned char bits;
60 char modename[128];
61 char drivername[32];
62 } data;
63 };
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70 #define HDLCDRVCTL_GETMODEMPAR 0
71 #define HDLCDRVCTL_SETMODEMPAR 1
72 #define HDLCDRVCTL_MODEMPARMASK 2
73 #define HDLCDRVCTL_GETCHANNELPAR 10
74 #define HDLCDRVCTL_SETCHANNELPAR 11
75 #define HDLCDRVCTL_OLDGETSTAT 20
76 #define HDLCDRVCTL_CALIBRATE 21
77 #define HDLCDRVCTL_GETSTAT 22
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82 #define HDLCDRVCTL_GETSAMPLES 30
83 #define HDLCDRVCTL_GETBITS 31
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88 #define HDLCDRVCTL_GETMODE 40
89 #define HDLCDRVCTL_SETMODE 41
90 #define HDLCDRVCTL_MODELIST 42
91 #define HDLCDRVCTL_DRIVERNAME 43
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96 #define HDLCDRV_PARMASK_IOBASE (1<<0)
97 #define HDLCDRV_PARMASK_IRQ (1<<1)
98 #define HDLCDRV_PARMASK_DMA (1<<2)
99 #define HDLCDRV_PARMASK_DMA2 (1<<3)
100 #define HDLCDRV_PARMASK_SERIOBASE (1<<4)
101 #define HDLCDRV_PARMASK_PARIOBASE (1<<5)
102 #define HDLCDRV_PARMASK_MIDIIOBASE (1<<6)
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109 #endif
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